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8#ifndef __ASM_ARCH_TEGRA_DC_H
9#define __ASM_ARCH_TEGRA_DC_H
10
11
12
13
14struct dc_cmd_reg {
15
16 uint gen_incr_syncpt;
17 uint gen_incr_syncpt_ctrl;
18 uint gen_incr_syncpt_err;
19
20 uint reserved0[5];
21
22
23 uint win_a_incr_syncpt;
24 uint win_a_incr_syncpt_ctrl;
25 uint win_a_incr_syncpt_err;
26
27 uint reserved1[5];
28
29
30 uint win_b_incr_syncpt;
31 uint win_b_incr_syncpt_ctrl;
32 uint win_b_incr_syncpt_err;
33
34 uint reserved2[5];
35
36
37 uint win_c_incr_syncpt;
38 uint win_c_incr_syncpt_ctrl;
39 uint win_c_incr_syncpt_err;
40
41 uint reserved3[13];
42
43
44 uint cont_syncpt_vsync;
45
46 uint reserved4[7];
47
48
49 uint ctxsw;
50 uint disp_cmd_opt0;
51 uint disp_cmd;
52 uint sig_raise;
53
54 uint reserved5[2];
55
56
57 uint disp_pow_ctrl;
58 uint int_stat;
59 uint int_mask;
60 uint int_enb;
61 uint int_type;
62 uint int_polarity;
63 uint sig_raise1;
64 uint sig_raise2;
65 uint sig_raise3;
66
67 uint reserved6;
68
69
70 uint state_access;
71 uint state_ctrl;
72 uint disp_win_header;
73 uint reg_act_ctrl;
74};
75
76enum {
77 PIN_REG_COUNT = 4,
78 PIN_OUTPUT_SEL_COUNT = 7,
79};
80
81
82struct dc_com_reg {
83
84 uint crc_ctrl;
85 uint crc_checksum;
86
87
88 uint pin_output_enb[PIN_REG_COUNT];
89
90
91 uint pin_output_polarity[PIN_REG_COUNT];
92
93
94 uint pin_output_data[PIN_REG_COUNT];
95
96
97 uint pin_input_enb[PIN_REG_COUNT];
98
99
100 uint pin_input_data0;
101 uint pin_input_data1;
102
103
104 uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
105
106
107 uint pin_misc_ctrl;
108 uint pm0_ctrl;
109 uint pm0_duty_cycle;
110 uint pm1_ctrl;
111 uint pm1_duty_cycle;
112 uint spi_ctrl;
113 uint spi_start_byte;
114 uint hspi_wr_data_ab;
115 uint hspi_wr_data_cd;
116 uint hspi_cs_dc;
117 uint scratch_reg_a;
118 uint scratch_reg_b;
119 uint gpio_ctrl;
120 uint gpio_debounce_cnt;
121 uint crc_checksum_latched;
122};
123
124enum dc_disp_h_pulse_pos {
125 H_PULSE0_POSITION_A,
126 H_PULSE0_POSITION_B,
127 H_PULSE0_POSITION_C,
128 H_PULSE0_POSITION_D,
129 H_PULSE0_POSITION_COUNT,
130};
131
132struct _disp_h_pulse {
133
134 uint h_pulse_ctrl;
135
136 uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
137};
138
139enum dc_disp_v_pulse_pos {
140 V_PULSE0_POSITION_A,
141 V_PULSE0_POSITION_B,
142 V_PULSE0_POSITION_C,
143 V_PULSE0_POSITION_COUNT,
144};
145
146struct _disp_v_pulse0 {
147
148 uint v_pulse_ctrl;
149
150 uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
151};
152
153struct _disp_v_pulse2 {
154
155 uint v_pulse_ctrl;
156
157 uint v_pulse_pos_a;
158};
159
160enum dc_disp_h_pulse_reg {
161 H_PULSE0,
162 H_PULSE1,
163 H_PULSE2,
164 H_PULSE_COUNT,
165};
166
167enum dc_disp_pp_select {
168 PP_SELECT_A,
169 PP_SELECT_B,
170 PP_SELECT_C,
171 PP_SELECT_D,
172 PP_SELECT_COUNT,
173};
174
175
176struct dc_disp_reg {
177
178 uint disp_signal_opt0;
179 uint disp_signal_opt1;
180 uint disp_win_opt;
181 uint mem_high_pri;
182 uint mem_high_pri_timer;
183 uint disp_timing_opt;
184 uint ref_to_sync;
185 uint sync_width;
186 uint back_porch;
187 uint disp_active;
188 uint front_porch;
189
190
191 struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
192
193
194 struct _disp_v_pulse0 v_pulse0;
195 struct _disp_v_pulse0 v_pulse1;
196
197
198 struct _disp_v_pulse2 v_pulse3;
199 struct _disp_v_pulse2 v_pulse4;
200
201
202 uint m0_ctrl;
203 uint m1_ctrl;
204 uint di_ctrl;
205 uint pp_ctrl;
206
207
208 uint pp_select[PP_SELECT_COUNT];
209
210
211 uint disp_clk_ctrl;
212 uint disp_interface_ctrl;
213 uint disp_color_ctrl;
214 uint shift_clk_opt;
215 uint data_enable_opt;
216 uint serial_interface_opt;
217 uint lcd_spi_opt;
218 uint border_color;
219
220
221 uint color_key0_lower;
222 uint color_key0_upper;
223 uint color_key1_lower;
224 uint color_key1_upper;
225
226 uint reserved0[2];
227
228
229 uint cursor_foreground;
230 uint cursor_background;
231 uint cursor_start_addr;
232 uint cursor_start_addr_ns;
233 uint cursor_pos;
234 uint cursor_pos_ns;
235 uint seq_ctrl;
236
237
238 uint spi_init_seq_data_a;
239 uint spi_init_seq_data_b;
240 uint spi_init_seq_data_c;
241 uint spi_init_seq_data_d;
242
243 uint reserved1[0x39];
244
245
246 uint dc_mccif_fifoctrl;
247 uint mccif_disp0a_hyst;
248 uint mccif_disp0b_hyst;
249 uint mccif_disp0c_hyst;
250 uint mccif_disp1b_hyst;
251
252 uint reserved2[0x3b];
253
254
255 uint dac_crt_ctrl;
256 uint disp_misc_ctrl;
257
258 u32 rsvd_4c2[34];
259
260
261 u32 blend_background_color;
262};
263
264enum dc_winc_filter_p {
265 WINC_FILTER_COUNT = 0x10,
266};
267
268
269struct dc_winc_reg {
270
271
272 uint color_palette;
273
274 uint reserved0[0xff];
275
276
277 uint palette_color_ext;
278
279
280
281 uint h_filter_p[WINC_FILTER_COUNT];
282
283
284 uint csc_yof;
285 uint csc_kyrgb;
286 uint csc_kur;
287 uint csc_kvr;
288 uint csc_kug;
289 uint csc_kvg;
290 uint csc_kub;
291 uint csc_kvb;
292
293
294 uint v_filter_p[WINC_FILTER_COUNT];
295};
296
297
298struct dc_win_reg {
299
300 uint win_opt;
301 uint byte_swap;
302 uint buffer_ctrl;
303 uint color_depth;
304 uint pos;
305 uint size;
306 uint prescaled_size;
307 uint h_initial_dda;
308 uint v_initial_dda;
309 uint dda_increment;
310 uint line_stride;
311 uint buf_stride;
312 uint uv_buf_stride;
313 uint buffer_addr_mode;
314 uint dv_ctrl;
315 uint blend_nokey;
316 uint blend_1win;
317 uint blend_2win_x;
318 uint blend_2win_y;
319 uint blend_3win_xy;
320 uint hp_fetch_ctrl;
321 uint global_alpha;
322 uint blend_layer_ctrl;
323 uint blend_match_select;
324 uint blend_nomatch_select;
325 uint blend_alpha_1bit;
326};
327
328
329struct dc_winbuf_reg {
330
331 uint start_addr;
332 uint start_addr_ns;
333 uint start_addr_u;
334 uint start_addr_u_ns;
335 uint start_addr_v;
336 uint start_addr_v_ns;
337 uint addr_h_offset;
338 uint addr_h_offset_ns;
339 uint addr_v_offset;
340 uint addr_v_offset_ns;
341 uint uflow_status;
342 uint buffer_surface_kind;
343 uint rsvd_80c;
344 uint start_addr_hi;
345};
346
347
348struct dc_ctlr {
349 struct dc_cmd_reg cmd;
350 uint reserved0[0x2bc];
351
352 struct dc_com_reg com;
353 uint reserved1[0xd6];
354
355 struct dc_disp_reg disp;
356 uint reserved2[0x1b];
357
358 struct dc_winc_reg winc;
359 uint reserved3[0xd7];
360
361 struct dc_win_reg win;
362 uint reserved4[0xe6];
363
364 struct dc_winbuf_reg winbuf;
365};
366
367
368#define CTRL_MODE_SHIFT 5
369#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
370enum {
371 CTRL_MODE_STOP,
372 CTRL_MODE_C_DISPLAY,
373 CTRL_MODE_NC_DISPLAY,
374};
375
376
377enum win_color_depth_id {
378 COLOR_DEPTH_P1,
379 COLOR_DEPTH_P2,
380 COLOR_DEPTH_P4,
381 COLOR_DEPTH_P8,
382 COLOR_DEPTH_B4G4R4A4,
383 COLOR_DEPTH_B5G5R5A,
384 COLOR_DEPTH_B5G6R5,
385 COLOR_DEPTH_AB5G5R5,
386 COLOR_DEPTH_B8G8R8A8 = 12,
387 COLOR_DEPTH_R8G8B8A8,
388 COLOR_DEPTH_B6x2G6x2R6x2A8,
389 COLOR_DEPTH_R6x2G6x2B6x2A8,
390 COLOR_DEPTH_YCbCr422,
391 COLOR_DEPTH_YUV422,
392 COLOR_DEPTH_YCbCr420P,
393 COLOR_DEPTH_YUV420P,
394 COLOR_DEPTH_YCbCr422P,
395 COLOR_DEPTH_YUV422P,
396 COLOR_DEPTH_YCbCr422R,
397 COLOR_DEPTH_YUV422R,
398 COLOR_DEPTH_YCbCr422RA,
399 COLOR_DEPTH_YUV422RA,
400};
401
402
403#define PW0_ENABLE BIT(0)
404#define PW1_ENABLE BIT(2)
405#define PW2_ENABLE BIT(4)
406#define PW3_ENABLE BIT(6)
407#define PW4_ENABLE BIT(8)
408#define PM0_ENABLE BIT(16)
409#define PM1_ENABLE BIT(18)
410#define SPI_ENABLE BIT(24)
411#define HSPI_ENABLE BIT(25)
412
413
414#define READ_MUX_ASSEMBLY (0 << 0)
415#define READ_MUX_ACTIVE (1 << 0)
416#define WRITE_MUX_ASSEMBLY (0 << 2)
417#define WRITE_MUX_ACTIVE (1 << 2)
418
419
420#define GENERAL_ACT_REQ BIT(0)
421#define WIN_A_ACT_REQ BIT(1)
422#define WIN_B_ACT_REQ BIT(2)
423#define WIN_C_ACT_REQ BIT(3)
424#define WIN_D_ACT_REQ BIT(4)
425#define WIN_H_ACT_REQ BIT(5)
426#define CURSOR_ACT_REQ BIT(7)
427#define GENERAL_UPDATE BIT(8)
428#define WIN_A_UPDATE BIT(9)
429#define WIN_B_UPDATE BIT(10)
430#define WIN_C_UPDATE BIT(11)
431#define WIN_D_UPDATE BIT(12)
432#define WIN_H_UPDATE BIT(13)
433#define CURSOR_UPDATE BIT(15)
434#define NC_HOST_TRIG BIT(24)
435
436
437#define WINDOW_A_SELECT BIT(4)
438#define WINDOW_B_SELECT BIT(5)
439#define WINDOW_C_SELECT BIT(6)
440#define WINDOW_D_SELECT BIT(7)
441#define WINDOW_H_SELECT BIT(8)
442
443
444#define CURSOR_ENABLE BIT(16)
445#define SOR_ENABLE BIT(25)
446#define TVO_ENABLE BIT(28)
447#define DSI_ENABLE BIT(29)
448#define HDMI_ENABLE BIT(30)
449
450
451#define VSYNC_H_POSITION(x) ((x) & 0xfff)
452
453
454#define SHIFT_CLK_DIVIDER_SHIFT 0
455#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
456#define PIXEL_CLK_DIVIDER_SHIFT 8
457#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT)
458enum {
459 PIXEL_CLK_DIVIDER_PCD1,
460 PIXEL_CLK_DIVIDER_PCD1H,
461 PIXEL_CLK_DIVIDER_PCD2,
462 PIXEL_CLK_DIVIDER_PCD3,
463 PIXEL_CLK_DIVIDER_PCD4,
464 PIXEL_CLK_DIVIDER_PCD6,
465 PIXEL_CLK_DIVIDER_PCD8,
466 PIXEL_CLK_DIVIDER_PCD9,
467 PIXEL_CLK_DIVIDER_PCD12,
468 PIXEL_CLK_DIVIDER_PCD16,
469 PIXEL_CLK_DIVIDER_PCD18,
470 PIXEL_CLK_DIVIDER_PCD24,
471 PIXEL_CLK_DIVIDER_PCD13,
472};
473
474
475#define DATA_FORMAT_SHIFT 0
476#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT)
477enum {
478 DATA_FORMAT_DF1P1C,
479 DATA_FORMAT_DF1P2C24B,
480 DATA_FORMAT_DF1P2C18B,
481 DATA_FORMAT_DF1P2C16B,
482 DATA_FORMAT_DF2S,
483 DATA_FORMAT_DF3S,
484 DATA_FORMAT_DFSPI,
485 DATA_FORMAT_DF1P3C24B,
486 DATA_FORMAT_DF1P3C18B,
487};
488#define DATA_ALIGNMENT_SHIFT 8
489enum {
490 DATA_ALIGNMENT_MSB,
491 DATA_ALIGNMENT_LSB,
492};
493#define DATA_ORDER_SHIFT 9
494enum {
495 DATA_ORDER_RED_BLUE,
496 DATA_ORDER_BLUE_RED,
497};
498
499
500#define DE_SELECT_SHIFT 0
501#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
502#define DE_SELECT_ACTIVE_BLANK 0x0
503#define DE_SELECT_ACTIVE 0x1
504#define DE_SELECT_ACTIVE_IS 0x2
505#define DE_CONTROL_SHIFT 2
506#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT)
507enum {
508 DE_CONTROL_ONECLK,
509 DE_CONTROL_NORMAL,
510 DE_CONTROL_EARLY_EXT,
511 DE_CONTROL_EARLY,
512 DE_CONTROL_ACTIVE_BLANK,
513};
514
515
516#define H_DIRECTION BIT(0)
517enum {
518 H_DIRECTION_INCREMENT,
519 H_DIRECTION_DECREMENT,
520};
521#define V_DIRECTION BIT(2)
522enum {
523 V_DIRECTION_INCREMENT,
524 V_DIRECTION_DECREMENT,
525};
526#define COLOR_EXPAND BIT(6)
527#define CP_ENABLE BIT(16)
528#define DV_ENABLE BIT(20)
529#define WIN_ENABLE BIT(30)
530
531
532#define BYTE_SWAP_SHIFT 0
533#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT)
534enum {
535 BYTE_SWAP_NOSWAP,
536 BYTE_SWAP_SWAP2,
537 BYTE_SWAP_SWAP4,
538 BYTE_SWAP_SWAP4HW
539};
540
541
542#define H_POSITION_SHIFT 0
543#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT)
544#define V_POSITION_SHIFT 16
545#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT)
546
547
548#define H_SIZE_SHIFT 0
549#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT)
550#define V_SIZE_SHIFT 16
551#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT)
552
553
554#define H_PRESCALED_SIZE_SHIFT 0
555#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE)
556#define V_PRESCALED_SIZE_SHIFT 16
557#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE)
558
559
560#define H_DDA_INC_SHIFT 0
561#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT)
562#define V_DDA_INC_SHIFT 16
563#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
564
565#define DC_POLL_TIMEOUT_MS 50
566#define DC_N_WINDOWS 5
567#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
568
569#endif
570