LXR uboot/arch/powerpc/cpu/mpc512x/speed.c

   1/*
   2 * (C) Copyright 2000-2009
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 *
   9 * Based on the MPC83xx code.
  10 */
  11
  12#include <common.h>
  13#include <command.h>
  14#include <asm/io.h>
  15#include <asm/processor.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19static int spmf_mult[] = {
  20        68, 1, 12, 16,
  21        20, 24, 28, 32,
  22        36, 40, 44, 48,
  23        52, 56, 60, 64
  24};
  25
  26static int cpmf_mult[][2] = {
  27        {0, 1}, {0, 1}, /* 0 and 1 are not valid */
  28        {1, 1}, {3, 2},
  29        {2, 1}, {5, 2},
  30        {3, 1}, {7, 2},
  31        {0, 1}, {0, 1}, /* and all above 7 are not valid too */
  32        {0, 1}, {0, 1},
  33        {0, 1}, {0, 1},
  34        {0, 1}, {0, 1}
  35};
  36
  37static int sys_dividors[][2] = {
  38        {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
  39        {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
  40        {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
  41        {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
  42        {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
  43        {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
  44        {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
  45};
  46
  47int get_clocks (void)
  48{
  49        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  50        u8 spmf;
  51        u8 cpmf;
  52        u8 sys_div;
  53        u8 ips_div;
  54        u8 pci_div;
  55        u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
  56        u32 spll;
  57        u32 sys_clk;
  58        u32 core_clk;
  59        u32 csb_clk;
  60        u32 ips_clk;
  61        u32 pci_clk;
  62        u32 reg;
  63
  64        reg = in_be32(&im->sysconf.immrbar);
  65        if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
  66                return -1;
  67
  68        reg = in_be32(&im->clk.spmr);
  69        spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  70        spll = ref_clk * spmf_mult[spmf];
  71
  72        reg = in_be32(&im->clk.scfr[1]);
  73        sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
  74        sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
  75
  76        csb_clk = sys_clk / 2;
  77
  78        reg = in_be32(&im->clk.spmr);
  79        cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
  80        core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
  81
  82        reg = in_be32(&im->clk.scfr[0]);
  83        ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
  84        if (ips_div != 0) {
  85                ips_clk = csb_clk / ips_div;
  86        } else {
  87                /* in case we cannot get a sane IPS divisor, fail gracefully */
  88                ips_clk = 0;
  89        }
  90
  91        reg = in_be32(&im->clk.scfr[0]);
  92        pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
  93        if (pci_div != 0) {
  94                pci_clk = csb_clk / pci_div;
  95        } else {
  96                /* in case we cannot get a sane IPS divisor, fail gracefully */
  97                pci_clk = 333333;
  98        }
  99
 100        gd->arch.ips_clk = ips_clk;
 101        gd->pci_clk = pci_clk;
 102        gd->arch.csb_clk = csb_clk;
 103        gd->cpu_clk = core_clk;
 104        gd->bus_clk = csb_clk;
 105        return 0;
 106
 107}
 108
 109/********************************************
 110 * get_bus_freq
 111 * return system bus freq in Hz
 112 *********************************************/
 113ulong get_bus_freq (ulong dummy)
 114{
 115        return gd->arch.csb_clk;
 116}
 117
 118int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 119{
 120        char buf[32];
 121
 122        printf("Clock configuration:\n");
 123        printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
 124        printf("  Coherent System Bus: %-4s MHz\n",
 125               strmhz(buf, gd->arch.csb_clk));
 126        printf("  IPS Bus:             %-4s MHz\n",
 127               strmhz(buf, gd->arch.ips_clk));
 128        printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
 129        printf("  DDR:                 %-4s MHz\n",
 130               strmhz(buf, 2 * gd->arch.csb_clk));
 131        return 0;
 132}
 133
 134U_BOOT_CMD(clocks, 1, 0, do_clocks,
 135        "print clock configuration",
 136        "    clocks"
 137);
 138