LXR uboot/arch/powerpc/cpu/mpc85xx/p1021

   1/*
   2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <config.h>
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/immap_85xx.h>
  11#include <asm/fsl_serdes.h>
  12
  13typedef struct serdes_85xx {
  14        u32     srdscr0;        /* 0x00 - SRDS Control Register 0 */
  15        u32     srdscr1;        /* 0x04 - SRDS Control Register 1 */
  16        u32     srdscr2;        /* 0x08 - SRDS Control Register 2 */
  17        u32     srdscr3;        /* 0x0C - SRDS Control Register 3 */
  18        u32     srdscr4;        /* 0x10 - SRDS Control Register 4 */
  19} serdes_85xx_t;
  20#define FSL_SRDSCR3_EIC0(x)     (((x) & 0x1f) << 8)
  21#define FSL_SRDSCR3_EIC0_MASK   FSL_SRDSCR3_EIC0(0x1f)
  22#define FSL_SRDSCR3_EIC1(x)     (((x) & 0x1f) << 0)
  23#define FSL_SRDSCR3_EIC1_MASK   FSL_SRDSCR3_EIC1(0x1f)
  24#define FSL_SRDSCR4_EIC2(x)     (((x) & 0x1f) << 8)
  25#define FSL_SRDSCR4_EIC2_MASK   FSL_SRDSCR4_EIC2(0x1f)
  26#define FSL_SRDSCR4_EIC3(x)     (((x) & 0x1f) << 0)
  27#define FSL_SRDSCR4_EIC3_MASK   FSL_SRDSCR4_EIC3(0x1f)
  28#define EIC_PCIE        0x13
  29#define EIC_SGMII       0x04
  30
  31#define SRDS1_MAX_LANES         4
  32
  33static u32 serdes1_prtcl_map;
  34
  35static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  36        [0x0] = {PCIE1, NONE, NONE, NONE},
  37        [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
  38        [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
  39        [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
  40};
  41
  42int is_serdes_configured(enum srds_prtcl prtcl)
  43{
  44        if (!(serdes1_prtcl_map & (1 << NONE)))
  45                fsl_serdes_init();
  46
  47        return (1 << prtcl) & serdes1_prtcl_map;
  48}
  49
  50void fsl_serdes_init(void)
  51{
  52        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  53        serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
  54
  55        u32 pordevsr = in_be32(&gur->pordevsr);
  56        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  57                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  58        int lane;
  59        u32 mask, val;
  60
  61        if (serdes1_prtcl_map & (1 << NONE))
  62                return;
  63
  64        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  65
  66        if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  67                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  68                return;
  69        }
  70
  71        for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  72                enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  73                serdes1_prtcl_map |= (1 << lane_prtcl);
  74        }
  75
  76        /* Set the first bit to indicate serdes has been initialized */
  77        serdes1_prtcl_map |= (1 << NONE);
  78
  79        /* Init SERDES Receiver electrical idle detection control for PCIe */
  80
  81        /* Lane 0 is always PCIe 1 */
  82        mask = FSL_SRDSCR3_EIC0_MASK;
  83        val = FSL_SRDSCR3_EIC0(EIC_PCIE);
  84
  85        /* Lane 1 */
  86        if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
  87            (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
  88                mask |= FSL_SRDSCR3_EIC1_MASK;
  89                val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
  90        }
  91
  92        /* Handle lanes 0 & 1 */
  93        clrsetbits_be32(&serdes->srdscr3, mask, val);
  94
  95        /* Handle lanes 2 & 3 */
  96        if (srds_cfg == 0x6) {
  97                mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
  98                val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
  99                clrsetbits_be32(&serdes->srdscr4, mask, val);
 100        }
 101
 102        /* 100 ms delay */
 103        udelay(100000);
 104}
 105