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14#ifndef __CPM_85XX__
15#define __CPM_85XX__
16
17#include <asm/immap_85xx.h>
18
19
20
21#define CPM_CR_RST ((uint)0x80000000)
22#define CPM_CR_PAGE ((uint)0x7c000000)
23#define CPM_CR_SBLOCK ((uint)0x03e00000)
24#define CPM_CR_FLG ((uint)0x00010000)
25#define CPM_CR_MCN ((uint)0x00003fc0)
26#define CPM_CR_OPCODE ((uint)0x0000000f)
27
28
29
30#define CPM_CR_SCC1_SBLOCK (0x04)
31#define CPM_CR_SCC2_SBLOCK (0x05)
32#define CPM_CR_SCC3_SBLOCK (0x06)
33#define CPM_CR_SCC4_SBLOCK (0x07)
34#define CPM_CR_SMC1_SBLOCK (0x08)
35#define CPM_CR_SMC2_SBLOCK (0x09)
36#define CPM_CR_SPI_SBLOCK (0x0a)
37#define CPM_CR_I2C_SBLOCK (0x0b)
38#define CPM_CR_TIMER_SBLOCK (0x0f)
39#define CPM_CR_RAND_SBLOCK (0x0e)
40#define CPM_CR_FCC1_SBLOCK (0x10)
41#define CPM_CR_FCC2_SBLOCK (0x11)
42#define CPM_CR_FCC3_SBLOCK (0x12)
43#define CPM_CR_MCC1_SBLOCK (0x1c)
44
45#define CPM_CR_SCC1_PAGE (0x00)
46#define CPM_CR_SCC2_PAGE (0x01)
47#define CPM_CR_SCC3_PAGE (0x02)
48#define CPM_CR_SCC4_PAGE (0x03)
49#define CPM_CR_SPI_PAGE (0x09)
50#define CPM_CR_I2C_PAGE (0x0a)
51#define CPM_CR_TIMER_PAGE (0x0a)
52#define CPM_CR_RAND_PAGE (0x0a)
53#define CPM_CR_FCC1_PAGE (0x04)
54#define CPM_CR_FCC2_PAGE (0x05)
55#define CPM_CR_FCC3_PAGE (0x06)
56#define CPM_CR_MCC1_PAGE (0x07)
57#define CPM_CR_MCC2_PAGE (0x08)
58
59
60
61#define CPM_CR_INIT_TRX ((ushort)0x0000)
62#define CPM_CR_INIT_RX ((ushort)0x0001)
63#define CPM_CR_INIT_TX ((ushort)0x0002)
64#define CPM_CR_HUNT_MODE ((ushort)0x0003)
65#define CPM_CR_STOP_TX ((ushort)0x0004)
66#define CPM_CR_RESTART_TX ((ushort)0x0006)
67#define CPM_CR_SET_GADDR ((ushort)0x0008)
68
69#define mk_cr_cmd(PG, SBC, MCN, OP) \
70 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
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76
77
78#define CPM_DATAONLY_BASE ((uint)128)
79#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
80#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
81#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
82#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
83#else
84#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
85#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
86#endif
87
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90
91
92#define NUM_CPM_HOST_PAGES 2
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96
97
98uint m8560_cpm_dpalloc(uint size, uint align);
99uint m8560_cpm_hostalloc(uint size, uint align);
100void m8560_cpm_setbrg(uint brg, uint rate);
101void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
102void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
103
104
105
106typedef struct cpm_buf_desc {
107 ushort cbd_sc;
108 ushort cbd_datlen;
109 uint cbd_bufaddr;
110} cbd_t;
111
112#define BD_SC_EMPTY ((ushort)0x8000)
113#define BD_SC_READY ((ushort)0x8000)
114#define BD_SC_WRAP ((ushort)0x2000)
115#define BD_SC_INTRPT ((ushort)0x1000)
116#define BD_SC_LAST ((ushort)0x0800)
117#define BD_SC_CM ((ushort)0x0200)
118#define BD_SC_ID ((ushort)0x0100)
119#define BD_SC_P ((ushort)0x0100)
120#define BD_SC_BR ((ushort)0x0020)
121#define BD_SC_FR ((ushort)0x0010)
122#define BD_SC_PR ((ushort)0x0008)
123#define BD_SC_OV ((ushort)0x0002)
124#define BD_SC_CD ((ushort)0x0001)
125
126
127
128#define CPMFCR_GBL ((u_char)0x20)
129#define CPMFCR_EB ((u_char)0x10)
130#define CPMFCR_TC2 ((u_char)0x04)
131#define CPMFCR_DTB ((u_char)0x02)
132#define CPMFCR_BDB ((u_char)0x01)
133
134
135
136#define CPM_POST_WORD_ADDR 0x80FC
137#define PROFF_SCC1 ((uint)0x8000)
138#define PROFF_SCC2 ((uint)0x8100)
139#define PROFF_SCC3 ((uint)0x8200)
140#define PROFF_SCC4 ((uint)0x8300)
141#define PROFF_FCC1 ((uint)0x8400)
142#define PROFF_FCC2 ((uint)0x8500)
143#define PROFF_FCC3 ((uint)0x8600)
144#define PROFF_MCC1 ((uint)0x8700)
145#define PROFF_MCC2 ((uint)0x8800)
146#define PROFF_SPI_BASE ((uint)0x89fc)
147#define PROFF_TIMERS ((uint)0x8ae0)
148#define PROFF_REVNUM ((uint)0x8af0)
149#define PROFF_RAND ((uint)0x8af8)
150#define PROFF_I2C_BASE ((uint)0x8afc)
151
152
153
154#define CPM_BRG_RST ((uint)0x00020000)
155#define CPM_BRG_EN ((uint)0x00010000)
156#define CPM_BRG_EXTC_INT ((uint)0x00000000)
157#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
158#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
159#define CPM_BRG_ATB ((uint)0x00002000)
160#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
161#define CPM_BRG_DIV16 ((uint)0x00000001)
162
163
164
165#define SCC_GSMRH_IRP ((uint)0x00040000)
166#define SCC_GSMRH_GDE ((uint)0x00010000)
167#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
168#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
169#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
170#define SCC_GSMRH_REVD ((uint)0x00002000)
171#define SCC_GSMRH_TRX ((uint)0x00001000)
172#define SCC_GSMRH_TTX ((uint)0x00000800)
173#define SCC_GSMRH_CDP ((uint)0x00000400)
174#define SCC_GSMRH_CTSP ((uint)0x00000200)
175#define SCC_GSMRH_CDS ((uint)0x00000100)
176#define SCC_GSMRH_CTSS ((uint)0x00000080)
177#define SCC_GSMRH_TFL ((uint)0x00000040)
178#define SCC_GSMRH_RFW ((uint)0x00000020)
179#define SCC_GSMRH_TXSY ((uint)0x00000010)
180#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
181#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
182#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
183#define SCC_GSMRH_RTSM ((uint)0x00000002)
184#define SCC_GSMRH_RSYN ((uint)0x00000001)
185
186#define SCC_GSMRL_SIR ((uint)0x80000000)
187#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
188#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
189#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
190#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
191#define SCC_GSMRL_TCI ((uint)0x10000000)
192#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
193#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
194#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
195#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
196#define SCC_GSMRL_RINV ((uint)0x02000000)
197#define SCC_GSMRL_TINV ((uint)0x01000000)
198#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
199#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
200#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
201#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
202#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
203#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
204#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
205#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
206#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
207#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
208#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
209#define SCC_GSMRL_TEND ((uint)0x00040000)
210#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
211#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
212#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
213#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
214#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
215#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
216#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
217#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
218#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
219#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
220#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
221#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
222#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
223#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
224#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
225#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
226#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
227#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
228#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0)
229#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
230#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
231#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
232#define SCC_GSMRL_ENR ((uint)0x00000020)
233#define SCC_GSMRL_ENT ((uint)0x00000010)
234#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
235#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
236#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
237#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
238#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
239#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
240#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
241#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
242#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
243#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
244
245#define SCC_TODR_TOD ((ushort)0x8000)
246
247
248
249#define SCCM_TXE ((unsigned char)0x10)
250#define SCCM_BSY ((unsigned char)0x04)
251#define SCCM_TX ((unsigned char)0x02)
252#define SCCM_RX ((unsigned char)0x01)
253
254typedef struct scc_param {
255 ushort scc_rbase;
256 ushort scc_tbase;
257 u_char scc_rfcr;
258 u_char scc_tfcr;
259 ushort scc_mrblr;
260 uint scc_rstate;
261 uint scc_idp;
262 ushort scc_rbptr;
263 ushort scc_ibc;
264 uint scc_rxtmp;
265 uint scc_tstate;
266 uint scc_tdp;
267 ushort scc_tbptr;
268 ushort scc_tbc;
269 uint scc_txtmp;
270 uint scc_rcrc;
271 uint scc_tcrc;
272} sccp_t;
273
274
275
276typedef struct scc_enet {
277 sccp_t sen_genscc;
278 uint sen_cpres;
279 uint sen_cmask;
280 uint sen_crcec;
281 uint sen_alec;
282 uint sen_disfc;
283 ushort sen_pads;
284 ushort sen_retlim;
285 ushort sen_retcnt;
286 ushort sen_maxflr;
287 ushort sen_minflr;
288 ushort sen_maxd1;
289 ushort sen_maxd2;
290 ushort sen_maxd;
291 ushort sen_dmacnt;
292 ushort sen_maxb;
293 ushort sen_gaddr1;
294 ushort sen_gaddr2;
295 ushort sen_gaddr3;
296 ushort sen_gaddr4;
297 uint sen_tbuf0data0;
298 uint sen_tbuf0data1;
299 uint sen_tbuf0rba;
300 uint sen_tbuf0crc;
301 ushort sen_tbuf0bcnt;
302 ushort sen_paddrh;
303 ushort sen_paddrm;
304 ushort sen_paddrl;
305 ushort sen_pper;
306 ushort sen_rfbdptr;
307 ushort sen_tfbdptr;
308 ushort sen_tlbdptr;
309 uint sen_tbuf1data0;
310 uint sen_tbuf1data1;
311 uint sen_tbuf1rba;
312 uint sen_tbuf1crc;
313 ushort sen_tbuf1bcnt;
314 ushort sen_txlen;
315 ushort sen_iaddr1;
316 ushort sen_iaddr2;
317 ushort sen_iaddr3;
318 ushort sen_iaddr4;
319 ushort sen_boffcnt;
320
321
322
323
324 ushort sen_taddrh;
325 ushort sen_taddrm;
326 ushort sen_taddrl;
327} scc_enet_t;
328
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330
331
332#define SCCE_ENET_GRA ((ushort)0x0080)
333#define SCCE_ENET_TXE ((ushort)0x0010)
334#define SCCE_ENET_RXF ((ushort)0x0008)
335#define SCCE_ENET_BSY ((ushort)0x0004)
336#define SCCE_ENET_TXB ((ushort)0x0002)
337#define SCCE_ENET_RXB ((ushort)0x0001)
338
339
340
341#define SCC_PSMR_HBC ((ushort)0x8000)
342#define SCC_PSMR_FC ((ushort)0x4000)
343#define SCC_PSMR_RSH ((ushort)0x2000)
344#define SCC_PSMR_IAM ((ushort)0x1000)
345#define SCC_PSMR_ENCRC ((ushort)0x0800)
346#define SCC_PSMR_PRO ((ushort)0x0200)
347#define SCC_PSMR_BRO ((ushort)0x0100)
348#define SCC_PSMR_SBT ((ushort)0x0080)
349#define SCC_PSMR_LPB ((ushort)0x0040)
350#define SCC_PSMR_SIP ((ushort)0x0020)
351#define SCC_PSMR_LCW ((ushort)0x0010)
352#define SCC_PSMR_NIB22 ((ushort)0x000a)
353#define SCC_PSMR_FDE ((ushort)0x0001)
354
355
356
357
358#define BD_ENET_RX_EMPTY ((ushort)0x8000)
359#define BD_ENET_RX_WRAP ((ushort)0x2000)
360#define BD_ENET_RX_INTR ((ushort)0x1000)
361#define BD_ENET_RX_LAST ((ushort)0x0800)
362#define BD_ENET_RX_FIRST ((ushort)0x0400)
363#define BD_ENET_RX_MISS ((ushort)0x0100)
364#define BD_ENET_RX_BC ((ushort)0x0080)
365#define BD_ENET_RX_MC ((ushort)0x0040)
366#define BD_ENET_RX_LG ((ushort)0x0020)
367#define BD_ENET_RX_NO ((ushort)0x0010)
368#define BD_ENET_RX_SH ((ushort)0x0008)
369#define BD_ENET_RX_CR ((ushort)0x0004)
370#define BD_ENET_RX_OV ((ushort)0x0002)
371#define BD_ENET_RX_CL ((ushort)0x0001)
372#define BD_ENET_RX_STATS ((ushort)0x01ff)
373
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375
376
377#define BD_ENET_TX_READY ((ushort)0x8000)
378#define BD_ENET_TX_PAD ((ushort)0x4000)
379#define BD_ENET_TX_WRAP ((ushort)0x2000)
380#define BD_ENET_TX_INTR ((ushort)0x1000)
381#define BD_ENET_TX_LAST ((ushort)0x0800)
382#define BD_ENET_TX_TC ((ushort)0x0400)
383#define BD_ENET_TX_DEF ((ushort)0x0200)
384#define BD_ENET_TX_HB ((ushort)0x0100)
385#define BD_ENET_TX_LC ((ushort)0x0080)
386#define BD_ENET_TX_RL ((ushort)0x0040)
387#define BD_ENET_TX_RCMASK ((ushort)0x003c)
388#define BD_ENET_TX_UN ((ushort)0x0002)
389#define BD_ENET_TX_CSL ((ushort)0x0001)
390#define BD_ENET_TX_STATS ((ushort)0x03ff)
391
392
393
394typedef struct scc_uart {
395 sccp_t scc_genscc;
396 uint scc_res1;
397 uint scc_res2;
398 ushort scc_maxidl;
399 ushort scc_idlc;
400 ushort scc_brkcr;
401 ushort scc_parec;
402 ushort scc_frmec;
403 ushort scc_nosec;
404 ushort scc_brkec;
405 ushort scc_brkln;
406 ushort scc_uaddr1;
407 ushort scc_uaddr2;
408 ushort scc_rtemp;
409 ushort scc_toseq;
410 ushort scc_char1;
411 ushort scc_char2;
412 ushort scc_char3;
413 ushort scc_char4;
414 ushort scc_char5;
415 ushort scc_char6;
416 ushort scc_char7;
417 ushort scc_char8;
418 ushort scc_rccm;
419 ushort scc_rccr;
420 ushort scc_rlbc;
421} scc_uart_t;
422
423
424
425#define UART_SCCM_GLR ((ushort)0x1000)
426#define UART_SCCM_GLT ((ushort)0x0800)
427#define UART_SCCM_AB ((ushort)0x0200)
428#define UART_SCCM_IDL ((ushort)0x0100)
429#define UART_SCCM_GRA ((ushort)0x0080)
430#define UART_SCCM_BRKE ((ushort)0x0040)
431#define UART_SCCM_BRKS ((ushort)0x0020)
432#define UART_SCCM_CCR ((ushort)0x0008)
433#define UART_SCCM_BSY ((ushort)0x0004)
434#define UART_SCCM_TX ((ushort)0x0002)
435#define UART_SCCM_RX ((ushort)0x0001)
436
437
438
439#define SCU_PSMR_FLC ((ushort)0x8000)
440#define SCU_PSMR_SL ((ushort)0x4000)
441#define SCU_PSMR_CL ((ushort)0x3000)
442#define SCU_PSMR_UM ((ushort)0x0c00)
443#define SCU_PSMR_FRZ ((ushort)0x0200)
444#define SCU_PSMR_RZS ((ushort)0x0100)
445#define SCU_PSMR_SYN ((ushort)0x0080)
446#define SCU_PSMR_DRT ((ushort)0x0040)
447#define SCU_PSMR_PEN ((ushort)0x0010)
448#define SCU_PSMR_RPM ((ushort)0x000c)
449#define SCU_PSMR_REVP ((ushort)0x0008)
450#define SCU_PSMR_TPM ((ushort)0x0003)
451#define SCU_PSMR_TEVP ((ushort)0x0003)
452
453
454
455typedef struct scc_trans {
456 sccp_t st_genscc;
457 uint st_cpres;
458 uint st_cmask;
459} scc_trans_t;
460
461#define BD_SCC_TX_LAST ((ushort)0x0800)
462
463
464
465#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
466#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
467#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
468#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
469#define FCC_GFMR_TCI ((uint)0x20000000)
470#define FCC_GFMR_TRX ((uint)0x10000000)
471#define FCC_GFMR_TTX ((uint)0x08000000)
472#define FCC_GFMR_TTX ((uint)0x08000000)
473#define FCC_GFMR_CDP ((uint)0x04000000)
474#define FCC_GFMR_CTSP ((uint)0x02000000)
475#define FCC_GFMR_CDS ((uint)0x01000000)
476#define FCC_GFMR_CTSS ((uint)0x00800000)
477#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
478#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
479#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
480#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
481#define FCC_GFMR_RTSM ((uint)0x00002000)
482#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
483#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
484#define FCC_GFMR_REVD ((uint)0x00000400)
485#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
486#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
487#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
488#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
489#define FCC_GFMR_ENR ((uint)0x00000020)
490#define FCC_GFMR_ENT ((uint)0x00000010)
491#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
492#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
493#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
494
495
496
497typedef struct fcc_param {
498 ushort fcc_riptr;
499 ushort fcc_tiptr;
500 ushort fcc_res1;
501 ushort fcc_mrblr;
502 uint fcc_rstate;
503 uint fcc_rbase;
504 ushort fcc_rbdstat;
505 ushort fcc_rbdlen;
506 uint fcc_rdptr;
507 uint fcc_tstate;
508 uint fcc_tbase;
509 ushort fcc_tbdstat;
510 ushort fcc_tbdlen;
511 uint fcc_tdptr;
512 uint fcc_rbptr;
513 uint fcc_tbptr;
514 uint fcc_rcrc;
515 uint fcc_res2;
516 uint fcc_tcrc;
517} fccp_t;
518
519
520
521
522typedef struct fcc_enet {
523 fccp_t fen_genfcc;
524 uint fen_statbuf;
525 uint fen_camptr;
526 uint fen_cmask;
527 uint fen_cpres;
528 uint fen_crcec;
529 uint fen_alec;
530 uint fen_disfc;
531 ushort fen_retlim;
532 ushort fen_retcnt;
533 ushort fen_pper;
534 ushort fen_boffcnt;
535 uint fen_gaddrh;
536 uint fen_gaddrl;
537 ushort fen_tfcstat;
538 ushort fen_tfclen;
539 uint fen_tfcptr;
540 ushort fen_mflr;
541 ushort fen_paddrh;
542 ushort fen_paddrm;
543 ushort fen_paddrl;
544 ushort fen_ibdcount;
545 ushort fen_ibdstart;
546 ushort fen_ibdend;
547 ushort fen_txlen;
548 uint fen_ibdbase[8];
549 uint fen_iaddrh;
550 uint fen_iaddrl;
551 ushort fen_minflr;
552 ushort fen_taddrh;
553 ushort fen_taddrm;
554 ushort fen_taddrl;
555 ushort fen_padptr;
556 ushort fen_cftype;
557 ushort fen_cfrange;
558 ushort fen_maxb;
559 ushort fen_maxd1;
560 ushort fen_maxd2;
561 ushort fen_maxd;
562 ushort fen_dmacnt;
563 uint fen_octc;
564 uint fen_colc;
565 uint fen_broc;
566 uint fen_mulc;
567 uint fen_uspc;
568 uint fen_frgc;
569 uint fen_ospc;
570 uint fen_jbrc;
571 uint fen_p64c;
572 uint fen_p65c;
573 uint fen_p128c;
574 uint fen_p256c;
575 uint fen_p512c;
576 uint fen_p1024c;
577 uint fen_cambuf;
578 ushort fen_rfthr;
579 ushort fen_rfcnt;
580} fcc_enet_t;
581
582
583
584#define FCC_ENET_GRA ((ushort)0x0080)
585#define FCC_ENET_RXC ((ushort)0x0040)
586#define FCC_ENET_TXC ((ushort)0x0020)
587#define FCC_ENET_TXE ((ushort)0x0010)
588#define FCC_ENET_RXF ((ushort)0x0008)
589#define FCC_ENET_BSY ((ushort)0x0004)
590#define FCC_ENET_TXB ((ushort)0x0002)
591#define FCC_ENET_RXB ((ushort)0x0001)
592
593
594
595#define FCC_PSMR_HBC ((uint)0x80000000)
596#define FCC_PSMR_FC ((uint)0x40000000)
597#define FCC_PSMR_SBT ((uint)0x20000000)
598#define FCC_PSMR_LPB ((uint)0x10000000)
599#define FCC_PSMR_LCW ((uint)0x08000000)
600#define FCC_PSMR_FDE ((uint)0x04000000)
601#define FCC_PSMR_MON ((uint)0x02000000)
602#define FCC_PSMR_PRO ((uint)0x00400000)
603#define FCC_PSMR_FCE ((uint)0x00200000)
604#define FCC_PSMR_RSH ((uint)0x00100000)
605#define FCC_PSMR_CAM ((uint)0x00000400)
606#define FCC_PSMR_BRO ((uint)0x00000200)
607#define FCC_PSMR_ENCRC ((uint)0x00000080)
608
609
610
611typedef struct iic {
612 ushort iic_rbase;
613 ushort iic_tbase;
614 u_char iic_rfcr;
615 u_char iic_tfcr;
616 ushort iic_mrblr;
617 uint iic_rstate;
618 uint iic_rdp;
619 ushort iic_rbptr;
620 ushort iic_rbc;
621 uint iic_rxtmp;
622 uint iic_tstate;
623 uint iic_tdp;
624 ushort iic_tbptr;
625 ushort iic_tbc;
626 uint iic_txtmp;
627} iic_t;
628
629
630
631typedef struct spi {
632 ushort spi_rbase;
633 ushort spi_tbase;
634 u_char spi_rfcr;
635 u_char spi_tfcr;
636 ushort spi_mrblr;
637 uint spi_rstate;
638 uint spi_rdp;
639 ushort spi_rbptr;
640 ushort spi_rbc;
641 uint spi_rxtmp;
642 uint spi_tstate;
643 uint spi_tdp;
644 ushort spi_tbptr;
645 ushort spi_tbc;
646 uint spi_txtmp;
647 uint spi_res;
648 uint spi_res1[4];
649} spi_t;
650
651
652
653#define SPMODE_LOOP ((ushort)0x4000)
654#define SPMODE_CI ((ushort)0x2000)
655#define SPMODE_CP ((ushort)0x1000)
656#define SPMODE_DIV16 ((ushort)0x0800)
657#define SPMODE_REV ((ushort)0x0400)
658#define SPMODE_MSTR ((ushort)0x0200)
659#define SPMODE_EN ((ushort)0x0100)
660#define SPMODE_LENMSK ((ushort)0x00f0)
661#define SPMODE_PMMSK ((ushort)0x000f)
662
663#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
664#define SPMODE_PM(x) ((x) &0xF)
665
666#define SPI_EB ((u_char)0x10)
667
668#define BD_IIC_START ((ushort)0x0400)
669
670
671
672
673#define CMXFCR_FC1 0x40000000
674#define CMXFCR_RF1CS_MSK 0x38000000
675#define CMXFCR_TF1CS_MSK 0x07000000
676#define CMXFCR_FC2 0x00400000
677#define CMXFCR_RF2CS_MSK 0x00380000
678#define CMXFCR_TF2CS_MSK 0x00070000
679#define CMXFCR_FC3 0x00004000
680#define CMXFCR_RF3CS_MSK 0x00003800
681#define CMXFCR_TF3CS_MSK 0x00000700
682
683#define CMXFCR_RF1CS_BRG5 0x00000000
684#define CMXFCR_RF1CS_BRG6 0x08000000
685#define CMXFCR_RF1CS_BRG7 0x10000000
686#define CMXFCR_RF1CS_BRG8 0x18000000
687#define CMXFCR_RF1CS_CLK9 0x20000000
688#define CMXFCR_RF1CS_CLK10 0x28000000
689#define CMXFCR_RF1CS_CLK11 0x30000000
690#define CMXFCR_RF1CS_CLK12 0x38000000
691
692#define CMXFCR_TF1CS_BRG5 0x00000000
693#define CMXFCR_TF1CS_BRG6 0x01000000
694#define CMXFCR_TF1CS_BRG7 0x02000000
695#define CMXFCR_TF1CS_BRG8 0x03000000
696#define CMXFCR_TF1CS_CLK9 0x04000000
697#define CMXFCR_TF1CS_CLK10 0x05000000
698#define CMXFCR_TF1CS_CLK11 0x06000000
699#define CMXFCR_TF1CS_CLK12 0x07000000
700
701#define CMXFCR_RF2CS_BRG5 0x00000000
702#define CMXFCR_RF2CS_BRG6 0x00080000
703#define CMXFCR_RF2CS_BRG7 0x00100000
704#define CMXFCR_RF2CS_BRG8 0x00180000
705#define CMXFCR_RF2CS_CLK13 0x00200000
706#define CMXFCR_RF2CS_CLK14 0x00280000
707#define CMXFCR_RF2CS_CLK15 0x00300000
708#define CMXFCR_RF2CS_CLK16 0x00380000
709
710#define CMXFCR_TF2CS_BRG5 0x00000000
711#define CMXFCR_TF2CS_BRG6 0x00010000
712#define CMXFCR_TF2CS_BRG7 0x00020000
713#define CMXFCR_TF2CS_BRG8 0x00030000
714#define CMXFCR_TF2CS_CLK13 0x00040000
715#define CMXFCR_TF2CS_CLK14 0x00050000
716#define CMXFCR_TF2CS_CLK15 0x00060000
717#define CMXFCR_TF2CS_CLK16 0x00070000
718
719#define CMXFCR_RF3CS_BRG5 0x00000000
720#define CMXFCR_RF3CS_BRG6 0x00000800
721#define CMXFCR_RF3CS_BRG7 0x00001000
722#define CMXFCR_RF3CS_BRG8 0x00001800
723#define CMXFCR_RF3CS_CLK13 0x00002000
724#define CMXFCR_RF3CS_CLK14 0x00002800
725#define CMXFCR_RF3CS_CLK15 0x00003000
726#define CMXFCR_RF3CS_CLK16 0x00003800
727
728#define CMXFCR_TF3CS_BRG5 0x00000000
729#define CMXFCR_TF3CS_BRG6 0x00000100
730#define CMXFCR_TF3CS_BRG7 0x00000200
731#define CMXFCR_TF3CS_BRG8 0x00000300
732#define CMXFCR_TF3CS_CLK13 0x00000400
733#define CMXFCR_TF3CS_CLK14 0x00000500
734#define CMXFCR_TF3CS_CLK15 0x00000600
735#define CMXFCR_TF3CS_CLK16 0x00000700
736
737
738
739
740#define CMXSCR_GR1 0x80000000
741#define CMXSCR_SC1 0x40000000
742#define CMXSCR_RS1CS_MSK 0x38000000
743#define CMXSCR_TS1CS_MSK 0x07000000
744#define CMXSCR_GR2 0x00800000
745#define CMXSCR_SC2 0x00400000
746#define CMXSCR_RS2CS_MSK 0x00380000
747#define CMXSCR_TS2CS_MSK 0x00070000
748#define CMXSCR_GR3 0x00008000
749#define CMXSCR_SC3 0x00004000
750#define CMXSCR_RS3CS_MSK 0x00003800
751#define CMXSCR_TS3CS_MSK 0x00000700
752#define CMXSCR_GR4 0x00000080
753#define CMXSCR_SC4 0x00000040
754#define CMXSCR_RS4CS_MSK 0x00000038
755#define CMXSCR_TS4CS_MSK 0x00000007
756
757#define CMXSCR_RS1CS_BRG1 0x00000000
758#define CMXSCR_RS1CS_BRG2 0x08000000
759#define CMXSCR_RS1CS_BRG3 0x10000000
760#define CMXSCR_RS1CS_BRG4 0x18000000
761#define CMXSCR_RS1CS_CLK11 0x20000000
762#define CMXSCR_RS1CS_CLK12 0x28000000
763#define CMXSCR_RS1CS_CLK3 0x30000000
764#define CMXSCR_RS1CS_CLK4 0x38000000
765
766#define CMXSCR_TS1CS_BRG1 0x00000000
767#define CMXSCR_TS1CS_BRG2 0x01000000
768#define CMXSCR_TS1CS_BRG3 0x02000000
769#define CMXSCR_TS1CS_BRG4 0x03000000
770#define CMXSCR_TS1CS_CLK11 0x04000000
771#define CMXSCR_TS1CS_CLK12 0x05000000
772#define CMXSCR_TS1CS_CLK3 0x06000000
773#define CMXSCR_TS1CS_CLK4 0x07000000
774
775#define CMXSCR_RS2CS_BRG1 0x00000000
776#define CMXSCR_RS2CS_BRG2 0x00080000
777#define CMXSCR_RS2CS_BRG3 0x00100000
778#define CMXSCR_RS2CS_BRG4 0x00180000
779#define CMXSCR_RS2CS_CLK11 0x00200000
780#define CMXSCR_RS2CS_CLK12 0x00280000
781#define CMXSCR_RS2CS_CLK3 0x00300000
782#define CMXSCR_RS2CS_CLK4 0x00380000
783
784#define CMXSCR_TS2CS_BRG1 0x00000000
785#define CMXSCR_TS2CS_BRG2 0x00010000
786#define CMXSCR_TS2CS_BRG3 0x00020000
787#define CMXSCR_TS2CS_BRG4 0x00030000
788#define CMXSCR_TS2CS_CLK11 0x00040000
789#define CMXSCR_TS2CS_CLK12 0x00050000
790#define CMXSCR_TS2CS_CLK3 0x00060000
791#define CMXSCR_TS2CS_CLK4 0x00070000
792
793#define CMXSCR_RS3CS_BRG1 0x00000000
794#define CMXSCR_RS3CS_BRG2 0x00000800
795#define CMXSCR_RS3CS_BRG3 0x00001000
796#define CMXSCR_RS3CS_BRG4 0x00001800
797#define CMXSCR_RS3CS_CLK5 0x00002000
798#define CMXSCR_RS3CS_CLK6 0x00002800
799#define CMXSCR_RS3CS_CLK7 0x00003000
800#define CMXSCR_RS3CS_CLK8 0x00003800
801
802#define CMXSCR_TS3CS_BRG1 0x00000000
803#define CMXSCR_TS3CS_BRG2 0x00000100
804#define CMXSCR_TS3CS_BRG3 0x00000200
805#define CMXSCR_TS3CS_BRG4 0x00000300
806#define CMXSCR_TS3CS_CLK5 0x00000400
807#define CMXSCR_TS3CS_CLK6 0x00000500
808#define CMXSCR_TS3CS_CLK7 0x00000600
809#define CMXSCR_TS3CS_CLK8 0x00000700
810
811#define CMXSCR_RS4CS_BRG1 0x00000000
812#define CMXSCR_RS4CS_BRG2 0x00000008
813#define CMXSCR_RS4CS_BRG3 0x00000010
814#define CMXSCR_RS4CS_BRG4 0x00000018
815#define CMXSCR_RS4CS_CLK5 0x00000020
816#define CMXSCR_RS4CS_CLK6 0x00000028
817#define CMXSCR_RS4CS_CLK7 0x00000030
818#define CMXSCR_RS4CS_CLK8 0x00000038
819
820#define CMXSCR_TS4CS_BRG1 0x00000000
821#define CMXSCR_TS4CS_BRG2 0x00000001
822#define CMXSCR_TS4CS_BRG3 0x00000002
823#define CMXSCR_TS4CS_BRG4 0x00000003
824#define CMXSCR_TS4CS_CLK5 0x00000004
825#define CMXSCR_TS4CS_CLK6 0x00000005
826#define CMXSCR_TS4CS_CLK7 0x00000006
827#define CMXSCR_TS4CS_CLK8 0x00000007
828
829#endif
830