1/* 2 * Copyright 2004-2011 Freescale Semiconductor, Inc. 3 * 4 * MPC83xx Internal Memory Map 5 * 6 * Contributors: 7 * Dave Liu <daveliu@freescale.com> 8 * Tanya Jiang <tanya.jiang@freescale.com> 9 * Mandy Lavi <mandy.lavi@freescale.com> 10 * Eran Liberty <liberty@freescale.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14#ifndef __IMMAP_83xx__ 15#define __IMMAP_83xx__ 16 17#include <fsl_immap.h> 18#include <asm/types.h> 19#include <asm/fsl_i2c.h> 20#include <asm/mpc8xxx_spi.h> 21#include <asm/fsl_lbc.h> 22#include <asm/fsl_dma.h> 23 24/* 25 * Local Access Window 26 */ 27typedef struct law83xx { 28 u32 bar; /* LBIU local access window base address register */ 29 u32 ar; /* LBIU local access window attribute register */ 30} law83xx_t; 31 32/* 33 * System configuration registers 34 */ 35typedef struct sysconf83xx { 36 u32 immrbar; /* Internal memory map base address register */ 37 u8 res0[0x04]; 38 u32 altcbar; /* Alternate configuration base address register */ 39 u8 res1[0x14]; 40 law83xx_t lblaw[4]; /* LBIU local access window */ 41 u8 res2[0x20]; 42 law83xx_t pcilaw[2]; /* PCI local access window */ 43 u8 res3[0x10]; 44 law83xx_t pcielaw[2]; /* PCI Express local access window */ 45 u8 res4[0x10]; 46 law83xx_t ddrlaw[2]; /* DDR local access window */ 47 u8 res5[0x50]; 48 u32 sgprl; /* System General Purpose Register Low */ 49 u32 sgprh; /* System General Purpose Register High */ 50 u32 spridr; /* System Part and Revision ID Register */ 51 u8 res6[0x04]; 52 u32 spcr; /* System Priority Configuration Register */ 53 u32 sicrl; /* System I/O Configuration Register Low */ 54 u32 sicrh; /* System I/O Configuration Register High */ 55 u8 res7[0x04]; 56 u32 sidcr0; /* System I/O Delay Configuration Register 0 */ 57 u32 sidcr1; /* System I/O Delay Configuration Register 1 */ 58 u32 ddrcdr; /* DDR Control Driver Register */ 59 u32 ddrdsr; /* DDR Debug Status Register */ 60 u32 obir; /* Output Buffer Impedance Register */ 61 u8 res8[0xC]; 62 u32 pecr1; /* PCI Express control register 1 */ 63#if defined(CONFIG_MPC830x) 64 u32 sdhccr; /* eSDHC Control Registers for MPC830x */ 65#else 66 u32 pecr2; /* PCI Express control register 2 */ 67#endif 68#if defined(CONFIG_MPC8309) 69 u32 can_dbg_ctrl; 70 u32 res9a; 71 u32 gpr1; 72 u8 res9b[0xAC]; 73#else 74 u8 res9[0xB8]; 75#endif 76} sysconf83xx_t; 77 78/* 79 * Watch Dog Timer (WDT) Registers 80 */ 81typedef struct wdt83xx { 82 u8 res0[4]; 83 u32 swcrr; /* System watchdog control register */ 84 u32 swcnr; /* System watchdog count register */ 85 u8 res1[2]; 86 u16 swsrr; /* System watchdog service register */ 87 u8 res2[0xF0]; 88} wdt83xx_t; 89 90/* 91 * RTC/PIT Module Registers 92 */ 93typedef struct rtclk83xx { 94 u32 cnr; /* control register */ 95 u32 ldr; /* load register */ 96 u32 psr; /* prescale register */ 97 u32 ctr; /* counter value field register */ 98 u32 evr; /* event register */ 99 u32 alr; /* alarm register */ 100 u8 res0[0xE8]; 101} rtclk83xx_t; 102 103/* 104 * Global timer module 105 */ 106typedef struct gtm83xx { 107 u8 cfr1; /* Timer1/2 Configuration */ 108 u8 res0[3]; 109 u8 cfr2; /* Timer3/4 Configuration */ 110 u8 res1[11]; 111 u16 mdr1; /* Timer1 Mode Register */ 112 u16 mdr2; /* Timer2 Mode Register */ 113 u16 rfr1; /* Timer1 Reference Register */ 114 u16 rfr2; /* Timer2 Reference Register */ 115 u16 cpr1; /* Timer1 Capture Register */ 116 u16 cpr2; /* Timer2 Capture Register */ 117 u16 cnr1; /* Timer1 Counter Register */ 118 u16 cnr2; /* Timer2 Counter Register */ 119 u16 mdr3; /* Timer3 Mode Register */ 120 u16 mdr4; /* Timer4 Mode Register */ 121 u16 rfr3; /* Timer3 Reference Register */ 122 u16 rfr4; /* Timer4 Reference Register */ 123 u16 cpr3; /* Timer3 Capture Register */ 124 u16 cpr4; /* Timer4 Capture Register */ 125 u16 cnr3; /* Timer3 Counter Register */ 126 u16 cnr4; /* Timer4 Counter Register */ 127 u16 evr1; /* Timer1 Event Register */ 128 u16 evr2; /* Timer2 Event Register */ 129 u16 evr3; /* Timer3 Event Register */ 130 u16 evr4; /* Timer4 Event Register */ 131 u16 psr1; /* Timer1 Prescaler Register */ 132 u16 psr2; /* Timer2 Prescaler Register */ 133 u16 psr3; /* Timer3 Prescaler Register */ 134 u16 psr4; /* Timer4 Prescaler Register */ 135 u8 res[0xC0]; 136} gtm83xx_t; 137 138/* 139 * Integrated Programmable Interrupt Controller 140 */ 141typedef struct ipic83xx { 142 u32 sicfr; /* System Global Interrupt Configuration Register */ 143 u32 sivcr; /* System Global Interrupt Vector Register */ 144 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ 145 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ 146 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ 147 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */ 148 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */ 149 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ 150 u32 simsr_h; /* System Internal Interrupt Mask Register - High */ 151 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ 152 u32 sicnr; /* System Internal Interrupt Control Register */ 153 u32 sepnr; /* System External Interrupt Pending Register */ 154 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ 155 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ 156 u32 semsr; /* System External Interrupt Mask Register */ 157 u32 secnr; /* System External Interrupt Control Register */ 158 u32 sersr; /* System Error Status Register */ 159 u32 sermr; /* System Error Mask Register */ 160 u32 sercr; /* System Error Control Register */ 161 u32 sepcr; /* System External Interrupt Polarity Control Register */ 162 u32 sifcr_h; /* System Internal Interrupt Force Register - High */ 163 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ 164 u32 sefcr; /* System External Interrupt Force Register */ 165 u32 serfr; /* System Error Force Register */ 166 u32 scvcr; /* System Critical Interrupt Vector Register */ 167 u32 smvcr; /* System Management Interrupt Vector Register */ 168 u8 res[0x98]; 169} ipic83xx_t; 170 171/* 172 * System Arbiter Registers 173 */ 174typedef struct arbiter83xx { 175 u32 acr; /* Arbiter Configuration Register */ 176 u32 atr; /* Arbiter Timers Register */ 177 u8 res[4]; 178 u32 aer; /* Arbiter Event Register */ 179 u32 aidr; /* Arbiter Interrupt Definition Register */ 180 u32 amr; /* Arbiter Mask Register */ 181 u32 aeatr; /* Arbiter Event Attributes Register */ 182 u32 aeadr; /* Arbiter Event Address Register */ 183 u32 aerr; /* Arbiter Event Response Register */ 184 u8 res1[0xDC]; 185} arbiter83xx_t; 186 187/* 188 * Reset Module 189 */ 190typedef struct reset83xx { 191 u32 rcwl; /* Reset Configuration Word Low Register */ 192 u32 rcwh; /* Reset Configuration Word High Register */ 193 u8 res0[8]; 194 u32 rsr; /* Reset Status Register */ 195 u32 rmr; /* Reset Mode Register */ 196 u32 rpr; /* Reset protection Register */ 197 u32 rcr; /* Reset Control Register */ 198 u32 rcer; /* Reset Control Enable Register */ 199 u8 res1[0xDC]; 200} reset83xx_t; 201 202/* 203 * Clock Module 204 */ 205typedef struct clk83xx { 206 u32 spmr; /* system PLL mode Register */ 207 u32 occr; /* output clock control Register */ 208 u32 sccr; /* system clock control Register */ 209 u8 res0[0xF4]; 210} clk83xx_t; 211 212/* 213 * Power Management Control Module 214 */ 215typedef struct pmc83xx { 216 u32 pmccr; /* PMC Configuration Register */ 217 u32 pmcer; /* PMC Event Register */ 218 u32 pmcmr; /* PMC Mask Register */ 219 u32 pmccr1; /* PMC Configuration Register 1 */ 220 u32 pmccr2; /* PMC Configuration Register 2 */ 221 u8 res0[0xEC]; 222} pmc83xx_t; 223 224/* 225 * General purpose I/O module 226 */ 227typedef struct gpio83xx { 228 u32 dir; /* direction register */ 229 u32 odr; /* open drain register */ 230 u32 dat; /* data register */ 231 u32 ier; /* interrupt event register */ 232 u32 imr; /* interrupt mask register */ 233 u32 icr; /* external interrupt control register */ 234 u8 res0[0xE8]; 235} gpio83xx_t; 236 237/* 238 * QE Ports Interrupts Registers 239 */ 240typedef struct qepi83xx { 241 u8 res0[0xC]; 242 u32 qepier; /* QE Ports Interrupt Event Register */ 243 u32 qepimr; /* QE Ports Interrupt Mask Register */ 244 u32 qepicr; /* QE Ports Interrupt Control Register */ 245 u8 res1[0xE8]; 246} qepi83xx_t; 247 248/* 249 * QE Parallel I/O Ports 250 */ 251typedef struct gpio_n { 252 u32 podr; /* Open Drain Register */ 253 u32 pdat; /* Data Register */ 254 u32 dir1; /* direction register 1 */ 255 u32 dir2; /* direction register 2 */ 256 u32 ppar1; /* Pin Assignment Register 1 */ 257 u32 ppar2; /* Pin Assignment Register 2 */ 258} gpio_n_t; 259 260typedef struct qegpio83xx { 261 gpio_n_t ioport[0x7]; 262 u8 res0[0x358]; 263} qepio83xx_t; 264 265/* 266 * QE Secondary Bus Access Windows 267 */ 268typedef struct qesba83xx { 269 u32 lbmcsar; /* Local bus memory controller start address */ 270 u32 sdmcsar; /* Secondary DDR memory controller start address */ 271 u8 res0[0x38]; 272 u32 lbmcear; /* Local bus memory controller end address */ 273 u32 sdmcear; /* Secondary DDR memory controller end address */ 274 u8 res1[0x38]; 275 u32 lbmcar; /* Local bus memory controller attributes */ 276 u32 sdmcar; /* Secondary DDR memory controller attributes */ 277 u8 res2[0x378]; 278} qesba83xx_t; 279 280/* 281 * DDR Memory Controller Memory Map for DDR1 282 * The structure of DDR2, or DDR3 is defined in fsl_immap.h 283 */ 284#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3) 285typedef struct ddr_cs_bnds { 286 u32 csbnds; 287 u8 res0[4]; 288} ddr_cs_bnds_t; 289 290typedef struct ddr83xx { 291 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ 292 u8 res0[0x60]; 293 u32 cs_config[4]; /* Chip Select x Configuration */ 294 u8 res1[0x70]; 295 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 296 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 297 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 298 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 299 u32 sdram_cfg; /* SDRAM Control Configuration */ 300 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ 301 u32 sdram_mode; /* SDRAM Mode Configuration */ 302 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ 303 u32 sdram_md_cntl; /* SDRAM Mode Control */ 304 u32 sdram_interval; /* SDRAM Interval Configuration */ 305 u32 ddr_data_init; /* SDRAM Data Initialization */ 306 u8 res2[4]; 307 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 308 u8 res3[0x14]; 309 u32 ddr_init_addr; /* DDR training initialization address */ 310 u32 ddr_init_ext_addr; /* DDR training initialization extended address */ 311 u8 res4[0xAA8]; 312 u32 ddr_ip_rev1; /* DDR IP block revision 1 */ 313 u32 ddr_ip_rev2; /* DDR IP block revision 2 */ 314 u8 res5[0x200]; 315 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ 316 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ 317 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ 318 u8 res6[0x14]; 319 u32 capture_data_hi; /* Memory Data Path Read Capture High */ 320 u32 capture_data_lo; /* Memory Data Path Read Capture Low */ 321 u32 capture_ecc; /* Memory Data Path Read Capture ECC */ 322 u8 res7[0x14]; 323 u32 err_detect; /* Memory Error Detect */ 324 u32 err_disable; /* Memory Error Disable */ 325 u32 err_int_en; /* Memory Error Interrupt Enable */ 326 u32 capture_attributes; /* Memory Error Attributes Capture */ 327 u32 capture_address; /* Memory Error Address Capture */ 328 u32 capture_ext_address;/* Memory Error Extended Address Capture */ 329 u32 err_sbe; /* Memory Single-Bit ECC Error Management */ 330 u8 res8[0xA4]; 331 u32 debug_reg; 332 u8 res9[0xFC]; 333} ddr83xx_t; 334#endif 335 336/* 337 * DUART 338 */ 339typedef struct duart83xx { 340 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ 341 u8 uier_udmb; /* combined register for UIER and UDMB */ 342 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ 343 u8 ulcr; /* line control register */ 344 u8 umcr; /* MODEM control register */ 345 u8 ulsr; /* line status register */ 346 u8 umsr; /* MODEM status register */ 347 u8 uscr; /* scratch register */ 348 u8 res0[8]; 349 u8 udsr; /* DMA status register */ 350 u8 res1[3]; 351 u8 res2[0xEC]; 352} duart83xx_t; 353 354/* 355 * DMA/Messaging Unit 356 */ 357typedef struct dma83xx { 358 u32 res0[0xC]; /* 0x0-0x29 reseverd */ 359 u32 omisr; /* 0x30 Outbound message interrupt status register */ 360 u32 omimr; /* 0x34 Outbound message interrupt mask register */ 361 u32 res1[0x6]; /* 0x38-0x49 reserved */ 362 u32 imr0; /* 0x50 Inbound message register 0 */ 363 u32 imr1; /* 0x54 Inbound message register 1 */ 364 u32 omr0; /* 0x58 Outbound message register 0 */ 365 u32 omr1; /* 0x5C Outbound message register 1 */ 366 u32 odr; /* 0x60 Outbound doorbell register */ 367 u32 res2; /* 0x64-0x67 reserved */ 368 u32 idr; /* 0x68 Inbound doorbell register */ 369 u32 res3[0x5]; /* 0x6C-0x79 reserved */ 370 u32 imisr; /* 0x80 Inbound message interrupt status register */ 371 u32 imimr; /* 0x84 Inbound message interrupt mask register */ 372 u32 res4[0x1E]; /* 0x88-0x99 reserved */ 373 struct fsl_dma dma[4]; 374} dma83xx_t; 375 376/* 377 * PCI Software Configuration Registers 378 */ 379typedef struct pciconf83xx { 380 u32 config_address; 381 u32 config_data; 382 u32 int_ack; 383 u8 res[116]; 384} pciconf83xx_t; 385 386/* 387 * PCI Outbound Translation Register 388 */ 389typedef struct pci_outbound_window { 390 u32 potar; 391 u8 res0[4]; 392 u32 pobar; 393 u8 res1[4]; 394 u32 pocmr; 395 u8 res2[4]; 396} pot83xx_t; 397 398/* 399 * Sequencer 400 */ 401typedef struct ios83xx { 402 pot83xx_t pot[6]; 403 u8 res0[0x60]; 404 u32 pmcr; 405 u8 res1[4]; 406 u32 dtcr; 407 u8 res2[4]; 408} ios83xx_t; 409 410/* 411 * PCI Controller Control and Status Registers 412 */ 413typedef struct pcictrl83xx { 414 u32 esr; 415 u32 ecdr; 416 u32 eer; 417 u32 eatcr; 418 u32 eacr; 419 u32 eeacr; 420 u32 edlcr; 421 u32 edhcr; 422 u32 gcr; 423 u32 ecr; 424 u32 gsr; 425 u8 res0[12]; 426 u32 pitar2; 427 u8 res1[4]; 428 u32 pibar2; 429 u32 piebar2; 430 u32 piwar2; 431 u8 res2[4]; 432 u32 pitar1; 433 u8 res3[4]; 434 u32 pibar1; 435 u32 piebar1; 436 u32 piwar1; 437 u8 res4[4]; 438 u32 pitar0; 439 u8 res5[4]; 440 u32 pibar0; 441 u8 res6[4]; 442 u32 piwar0; 443 u8 res7[132]; 444} pcictrl83xx_t; 445 446/* 447 * USB 448 */ 449typedef struct usb83xx { 450 u8 fixme[0x1000]; 451} usb83xx_t; 452 453/* 454 * TSEC 455 */ 456typedef struct tsec83xx { 457 u8 fixme[0x1000]; 458} tsec83xx_t; 459 460/* 461 * Security 462 */ 463typedef struct security83xx { 464 u8 fixme[0x10000]; 465} security83xx_t; 466 467/* 468 * PCI Express 469 */ 470struct pex_inbound_window { 471 u32 ar; 472 u32 tar; 473 u32 barl; 474 u32 barh; 475}; 476 477struct pex_outbound_window { 478 u32 ar; 479 u32 bar; 480 u32 tarl; 481 u32 tarh; 482}; 483 484struct pex_csb_bridge { 485 u32 pex_csb_ver; 486 u32 pex_csb_cab; 487 u32 pex_csb_ctrl; 488 u8 res0[8]; 489 u32 pex_dms_dstmr; 490 u8 res1[4]; 491 u32 pex_cbs_stat; 492 u8 res2[0x20]; 493 u32 pex_csb_obctrl; 494 u32 pex_csb_obstat; 495 u8 res3[0x98]; 496 u32 pex_csb_ibctrl; 497 u32 pex_csb_ibstat; 498 u8 res4[0xb8]; 499 u32 pex_wdma_ctrl; 500 u32 pex_wdma_addr; 501 u32 pex_wdma_stat; 502 u8 res5[0x94]; 503 u32 pex_rdma_ctrl; 504 u32 pex_rdma_addr; 505 u32 pex_rdma_stat; 506 u8 res6[0xd4]; 507 u32 pex_ombcr; 508 u32 pex_ombdr; 509 u8 res7[0x38]; 510 u32 pex_imbcr; 511 u32 pex_imbdr; 512 u8 res8[0x38]; 513 u32 pex_int_enb; 514 u32 pex_int_stat; 515 u32 pex_int_apio_vec1; 516 u32 pex_int_apio_vec2; 517 u8 res9[0x10]; 518 u32 pex_int_ppio_vec1; 519 u32 pex_int_ppio_vec2; 520 u32 pex_int_wdma_vec1; 521 u32 pex_int_wdma_vec2; 522 u32 pex_int_rdma_vec1; 523 u32 pex_int_rdma_vec2; 524 u32 pex_int_misc_vec; 525 u8 res10[4]; 526 u32 pex_int_axi_pio_enb; 527 u32 pex_int_axi_wdma_enb; 528 u32 pex_int_axi_rdma_enb; 529 u32 pex_int_axi_misc_enb; 530 u32 pex_int_axi_pio_stat; 531 u32 pex_int_axi_wdma_stat; 532 u32 pex_int_axi_rdma_stat; 533 u32 pex_int_axi_misc_stat; 534 u8 res11[0xa0]; 535 struct pex_outbound_window pex_outbound_win[4]; 536 u8 res12[0x100]; 537 u32 pex_epiwtar0; 538 u32 pex_epiwtar1; 539 u32 pex_epiwtar2; 540 u32 pex_epiwtar3; 541 u8 res13[0x70]; 542 struct pex_inbound_window pex_inbound_win[4]; 543}; 544 545typedef struct pex83xx { 546 u8 pex_cfg_header[0x404]; 547 u32 pex_ltssm_stat; 548 u8 res0[0x30]; 549 u32 pex_ack_replay_timeout; 550 u8 res1[4]; 551 u32 pex_gclk_ratio; 552 u8 res2[0xc]; 553 u32 pex_pm_timer; 554 u32 pex_pme_timeout; 555 u8 res3[4]; 556 u32 pex_aspm_req_timer; 557 u8 res4[0x18]; 558 u32 pex_ssvid_update; 559 u8 res5[0x34]; 560 u32 pex_cfg_ready; 561 u8 res6[0x24]; 562 u32 pex_bar_sizel; 563 u8 res7[4]; 564 u32 pex_bar_sel; 565 u8 res8[0x20]; 566 u32 pex_bar_pf; 567 u8 res9[0x88]; 568 u32 pex_pme_to_ack_tor; 569 u8 res10[0xc]; 570 u32 pex_ss_intr_mask; 571 u8 res11[0x25c]; 572 struct pex_csb_bridge bridge; 573 u8 res12[0x160]; 574} pex83xx_t; 575 576/* 577 * SATA 578 */ 579typedef struct sata83xx { 580 u8 fixme[0x1000]; 581} sata83xx_t; 582 583/* 584 * eSDHC 585 */ 586typedef struct sdhc83xx { 587 u8 fixme[0x1000]; 588} sdhc83xx_t; 589 590/* 591 * SerDes 592 */ 593typedef struct serdes83xx { 594 u32 srdscr0; 595 u32 srdscr1; 596 u32 srdscr2; 597 u32 srdscr3; 598 u32 srdscr4; 599 u8 res0[0xc]; 600 u32 srdsrstctl; 601 u8 res1[0xdc]; 602} serdes83xx_t; 603 604/* 605 * On Chip ROM 606 */ 607typedef struct rom83xx { 608#if defined(CONFIG_MPC8309) 609 u8 mem[0x8000]; 610#else 611 u8 mem[0x10000]; 612#endif 613} rom83xx_t; 614 615/* 616 * TDM 617 */ 618typedef struct tdm83xx { 619 u8 fixme[0x200]; 620} tdm83xx_t; 621 622/* 623 * TDM DMAC 624 */ 625typedef struct tdmdmac83xx { 626 u8 fixme[0x2000]; 627} tdmdmac83xx_t; 628 629#if defined(CONFIG_MPC834x) 630typedef struct immap { 631 sysconf83xx_t sysconf; /* System configuration */ 632 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 633 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 634 rtclk83xx_t pit; /* Periodic Interval Timer */ 635 gtm83xx_t gtm[2]; /* Global Timers Module */ 636 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 637 arbiter83xx_t arbiter; /* System Arbiter Registers */ 638 reset83xx_t reset; /* Reset Module */ 639 clk83xx_t clk; /* System Clock Module */ 640 pmc83xx_t pmc; /* Power Management Control Module */ 641 gpio83xx_t gpio[2]; /* General purpose I/O module */ 642 u8 res0[0x200]; 643 u8 dll_ddr[0x100]; 644 u8 dll_lbc[0x100]; 645 u8 res1[0xE00]; 646#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) 647 struct ccsr_ddr ddr; /* DDR Memory Controller Memory */ 648#else 649 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 650#endif 651 fsl_i2c_t i2c[2]; /* I2C Controllers */ 652 u8 res2[0x1300]; 653 duart83xx_t duart[2]; /* DUART */ 654 u8 res3[0x900]; 655 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 656 u8 res4[0x1000]; 657 spi8xxx_t spi; /* Serial Peripheral Interface */ 658 dma83xx_t dma; /* DMA */ 659 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ 660 ios83xx_t ios; /* Sequencer */ 661 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ 662 u8 res5[0x19900]; 663 usb83xx_t usb[2]; 664 tsec83xx_t tsec[2]; 665 u8 res6[0xA000]; 666 security83xx_t security; 667 u8 res7[0xC0000]; 668} immap_t; 669 670#ifndef CONFIG_MPC834x 671#ifdef CONFIG_HAS_FSL_MPH_USB 672#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ 673#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 674#else 675#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 676#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ 677#endif 678#else 679#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 680#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 681#endif 682 683#elif defined(CONFIG_MPC8313) 684typedef struct immap { 685 sysconf83xx_t sysconf; /* System configuration */ 686 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 687 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 688 rtclk83xx_t pit; /* Periodic Interval Timer */ 689 gtm83xx_t gtm[2]; /* Global Timers Module */ 690 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 691 arbiter83xx_t arbiter; /* System Arbiter Registers */ 692 reset83xx_t reset; /* Reset Module */ 693 clk83xx_t clk; /* System Clock Module */ 694 pmc83xx_t pmc; /* Power Management Control Module */ 695 gpio83xx_t gpio[1]; /* General purpose I/O module */ 696 u8 res0[0x1300]; 697 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 698 fsl_i2c_t i2c[2]; /* I2C Controllers */ 699 u8 res1[0x1300]; 700 duart83xx_t duart[2]; /* DUART */ 701 u8 res2[0x900]; 702 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 703 u8 res3[0x1000]; 704 spi8xxx_t spi; /* Serial Peripheral Interface */ 705 dma83xx_t dma; /* DMA */ 706 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 707 u8 res4[0x80]; 708 ios83xx_t ios; /* Sequencer */ 709 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 710 u8 res5[0x1aa00]; 711 usb83xx_t usb[1]; 712 tsec83xx_t tsec[2]; 713 u8 res6[0xA000]; 714 security83xx_t security; 715 u8 res7[0xC0000]; 716} immap_t; 717 718#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 719typedef struct immap { 720 sysconf83xx_t sysconf; /* System configuration */ 721 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 722 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 723 rtclk83xx_t pit; /* Periodic Interval Timer */ 724 gtm83xx_t gtm[2]; /* Global Timers Module */ 725 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 726 arbiter83xx_t arbiter; /* System Arbiter Registers */ 727 reset83xx_t reset; /* Reset Module */ 728 clk83xx_t clk; /* System Clock Module */ 729 pmc83xx_t pmc; /* Power Management Control Module */ 730 gpio83xx_t gpio[1]; /* General purpose I/O module */ 731 u8 res0[0x1300]; 732 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 733 fsl_i2c_t i2c[2]; /* I2C Controllers */ 734 u8 res1[0x1300]; 735 duart83xx_t duart[2]; /* DUART */ 736 u8 res2[0x900]; 737 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 738 u8 res3[0x1000]; 739 spi8xxx_t spi; /* Serial Peripheral Interface */ 740 dma83xx_t dma; /* DMA */ 741 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 742 u8 res4[0x80]; 743 ios83xx_t ios; /* Sequencer */ 744 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 745 u8 res5[0xa00]; 746 pex83xx_t pciexp[2]; /* PCI Express Controller */ 747 u8 res6[0xb000]; 748 tdm83xx_t tdm; /* TDM Controller */ 749 u8 res7[0x1e00]; 750 sata83xx_t sata[2]; /* SATA Controller */ 751 u8 res8[0x9000]; 752 usb83xx_t usb[1]; /* USB DR Controller */ 753 tsec83xx_t tsec[2]; 754 u8 res9[0x6000]; 755 tdmdmac83xx_t tdmdmac; /* TDM DMAC */ 756 u8 res10[0x2000]; 757 security83xx_t security; 758 u8 res11[0xA3000]; 759 serdes83xx_t serdes[1]; /* SerDes Registers */ 760 u8 res12[0x1CF00]; 761} immap_t; 762 763#elif defined(CONFIG_MPC837x) 764typedef struct immap { 765 sysconf83xx_t sysconf; /* System configuration */ 766 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 767 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 768 rtclk83xx_t pit; /* Periodic Interval Timer */ 769 gtm83xx_t gtm[2]; /* Global Timers Module */ 770 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 771 arbiter83xx_t arbiter; /* System Arbiter Registers */ 772 reset83xx_t reset; /* Reset Module */ 773 clk83xx_t clk; /* System Clock Module */ 774 pmc83xx_t pmc; /* Power Management Control Module */ 775 gpio83xx_t gpio[2]; /* General purpose I/O module */ 776 u8 res0[0x1200]; 777 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 778 fsl_i2c_t i2c[2]; /* I2C Controllers */ 779 u8 res1[0x1300]; 780 duart83xx_t duart[2]; /* DUART */ 781 u8 res2[0x900]; 782 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 783 u8 res3[0x1000]; 784 spi8xxx_t spi; /* Serial Peripheral Interface */ 785 dma83xx_t dma; /* DMA */ 786 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 787 u8 res4[0x80]; 788 ios83xx_t ios; /* Sequencer */ 789 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 790 u8 res5[0xa00]; 791 pex83xx_t pciexp[2]; /* PCI Express Controller */ 792 u8 res6[0xd000]; 793 sata83xx_t sata[4]; /* SATA Controller */ 794 u8 res7[0x7000]; 795 usb83xx_t usb[1]; /* USB DR Controller */ 796 tsec83xx_t tsec[2]; 797 u8 res8[0x8000]; 798 sdhc83xx_t sdhc; /* SDHC Controller */ 799 u8 res9[0x1000]; 800 security83xx_t security; 801 u8 res10[0xA3000]; 802 serdes83xx_t serdes[2]; /* SerDes Registers */ 803 u8 res11[0xCE00]; 804 rom83xx_t rom; /* On Chip ROM */ 805} immap_t; 806 807#elif defined(CONFIG_MPC8360) 808typedef struct immap { 809 sysconf83xx_t sysconf; /* System configuration */ 810 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 811 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 812 rtclk83xx_t pit; /* Periodic Interval Timer */ 813 u8 res0[0x200]; 814 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 815 arbiter83xx_t arbiter; /* System Arbiter Registers */ 816 reset83xx_t reset; /* Reset Module */ 817 clk83xx_t clk; /* System Clock Module */ 818 pmc83xx_t pmc; /* Power Management Control Module */ 819 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 820 u8 res1[0x300]; 821 u8 dll_ddr[0x100]; 822 u8 dll_lbc[0x100]; 823 u8 res2[0x200]; 824 qepio83xx_t qepio; /* QE Parallel I/O ports */ 825 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ 826 u8 res3[0x400]; 827 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 828 fsl_i2c_t i2c[2]; /* I2C Controllers */ 829 u8 res4[0x1300]; 830 duart83xx_t duart[2]; /* DUART */ 831 u8 res5[0x900]; 832 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 833 u8 res6[0x2000]; 834 dma83xx_t dma; /* DMA */ 835 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 836 u8 res7[128]; 837 ios83xx_t ios; /* Sequencer (IOS) */ 838 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 839 u8 res8[0x4A00]; 840 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ 841 u8 res9[0x22000]; 842 security83xx_t security; 843 u8 res10[0xC0000]; 844 u8 qe[0x100000]; /* QE block */ 845} immap_t; 846 847#elif defined(CONFIG_MPC832x) 848typedef struct immap { 849 sysconf83xx_t sysconf; /* System configuration */ 850 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 851 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 852 rtclk83xx_t pit; /* Periodic Interval Timer */ 853 gtm83xx_t gtm[2]; /* Global Timers Module */ 854 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 855 arbiter83xx_t arbiter; /* System Arbiter Registers */ 856 reset83xx_t reset; /* Reset Module */ 857 clk83xx_t clk; /* System Clock Module */ 858 pmc83xx_t pmc; /* Power Management Control Module */ 859 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 860 u8 res0[0x300]; 861 u8 dll_ddr[0x100]; 862 u8 dll_lbc[0x100]; 863 u8 res1[0x200]; 864 qepio83xx_t qepio; /* QE Parallel I/O ports */ 865 u8 res2[0x800]; 866 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 867 fsl_i2c_t i2c[2]; /* I2C Controllers */ 868 u8 res3[0x1300]; 869 duart83xx_t duart[2]; /* DUART */ 870 u8 res4[0x900]; 871 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 872 u8 res5[0x2000]; 873 dma83xx_t dma; /* DMA */ 874 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 875 u8 res6[128]; 876 ios83xx_t ios; /* Sequencer (IOS) */ 877 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 878 u8 res7[0x27A00]; 879 security83xx_t security; 880 u8 res8[0xC0000]; 881 u8 qe[0x100000]; /* QE block */ 882} immap_t; 883#elif defined(CONFIG_MPC8309) 884typedef struct immap { 885 sysconf83xx_t sysconf; /* System configuration */ 886 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 887 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 888 rtclk83xx_t pit; /* Periodic Interval Timer */ 889 gtm83xx_t gtm[2]; /* Global Timers Module */ 890 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 891 arbiter83xx_t arbiter; /* System Arbiter Registers */ 892 reset83xx_t reset; /* Reset Module */ 893 clk83xx_t clk; /* System Clock Module */ 894 pmc83xx_t pmc; /* Power Management Control Module */ 895 gpio83xx_t gpio[2]; /* General purpose I/O module */ 896 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */ 897 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 898 qepio83xx_t qepio; /* QE Parallel I/O ports */ 899 u8 res1[0x800]; 900 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 901 fsl_i2c_t i2c[2]; /* I2C Controllers */ 902 u8 res2[0x1300]; 903 duart83xx_t duart[2]; /* DUART */ 904 u8 res3[0x200]; 905 duart83xx_t duart1[2]; /* DUART */ 906 u8 res4[0x500]; 907 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 908 u8 res5[0x1000]; 909 u8 spi[0x100]; 910 u8 res6[0xf00]; 911 dma83xx_t dma; /* DMA */ 912 pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */ 913 u8 res7[0x80]; 914 ios83xx_t ios; /* Sequencer (IOS) */ 915 pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */ 916 u8 res8[0x13A00]; 917 u8 can1[0x1000]; /* Flexcan 1 */ 918 u8 can2[0x1000]; /* Flexcan 2 */ 919 u8 res9[0x5000]; 920 usb83xx_t usb; 921 u8 res10[0x5000]; 922 u8 can3[0x1000]; /* Flexcan 3 */ 923 u8 can4[0x1000]; /* Flexcan 4 */ 924 u8 res11[0x1000]; 925 u8 dma1[0x2000]; /* DMA */ 926 sdhc83xx_t sdhc; /* SDHC Controller */ 927 u8 res12[0xC1000]; 928 rom83xx_t rom; /* On Chip ROM */ 929 u8 res13[0x8000]; 930 u8 qe[0x100000]; /* QE block */ 931 u8 res14[0xE00000];/* Added for 8309 */ 932} immap_t; 933#endif 934 935#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) 936#define CONFIG_SYS_FSL_DDR_ADDR \ 937 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 938#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) 939#define CONFIG_SYS_MPC83xx_DMA_ADDR \ 940 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) 941#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) 942#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ 943 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) 944 945#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET 946#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 947#endif 948#define CONFIG_SYS_MPC83xx_USB1_ADDR \ 949 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) 950#if defined(CONFIG_MPC834x) 951#define CONFIG_SYS_MPC83xx_USB2_ADDR \ 952 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) 953#endif 954#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) 955 956#define CONFIG_SYS_TSEC1_OFFSET 0x24000 957#define CONFIG_SYS_MDIO1_OFFSET 0x24000 958 959#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 960#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 961#endif /* __IMMAP_83xx__ */ 962