LXR uboot/board/freescale/ls2080ardb/eth

   1/*
   2 * Copyright 2015 Freescale Semiconductor, Inc.
   3 *
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <command.h>
  10#include <netdev.h>
  11#include <malloc.h>
  12#include <fsl_mdio.h>
  13#include <miiphy.h>
  14#include <phy.h>
  15#include <fm_eth.h>
  16#include <asm/io.h>
  17#include <exports.h>
  18#include <asm/arch/fsl_serdes.h>
  19#include <fsl-mc/ldpaa_wriop.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23#define MC_BOOT_ENV_VAR "mcinitcmd"
  24int board_eth_init(bd_t *bis)
  25{
  26#if defined(CONFIG_FSL_MC_ENET)
  27        char *mc_boot_env_var;
  28        int i, interface;
  29        struct memac_mdio_info mdio_info;
  30        struct mii_dev *dev;
  31        struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  32        u32 srds_s1;
  33        struct memac_mdio_controller *reg;
  34
  35        srds_s1 = in_le32(&gur->rcwsr[28]) &
  36                                FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  37        srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  38
  39        reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  40        mdio_info.regs = reg;
  41        mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  42
  43        /* Register the EMI 1 */
  44        fm_memac_mdio_init(bis, &mdio_info);
  45
  46        reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  47        mdio_info.regs = reg;
  48        mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  49
  50        /* Register the EMI 2 */
  51        fm_memac_mdio_init(bis, &mdio_info);
  52
  53        switch (srds_s1) {
  54        case 0x2A:
  55                wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  56                wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  57                wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  58                wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  59                wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  60                wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  61                wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  62                wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  63
  64                break;
  65        default:
  66                printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
  67                       srds_s1);
  68                break;
  69        }
  70
  71        for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
  72                interface = wriop_get_enet_if(i);
  73                switch (interface) {
  74                case PHY_INTERFACE_MODE_XGMII:
  75                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  76                        wriop_set_mdio(i, dev);
  77                        break;
  78                default:
  79                        break;
  80                }
  81        }
  82
  83        for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
  84                switch (wriop_get_enet_if(i)) {
  85                case PHY_INTERFACE_MODE_XGMII:
  86                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  87                        wriop_set_mdio(i, dev);
  88                        break;
  89                default:
  90                        break;
  91                }
  92        }
  93
  94        mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
  95        if (mc_boot_env_var)
  96                run_command_list(mc_boot_env_var, -1, 0);
  97        cpu_eth_init(bis);
  98#endif /* CONFIG_FMAN_ENET */
  99
 100#ifdef CONFIG_PHY_AQUANTIA
 101        /*
 102         * Export functions to be used by AQ firmware
 103         * upload application
 104         */
 105        gd->jt->strcpy = strcpy;
 106        gd->jt->mdelay = mdelay;
 107        gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 108        gd->jt->phy_find_by_mask = phy_find_by_mask;
 109        gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 110        gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 111#endif
 112        return pci_eth_init(bis);
 113}
 114