LXR uboot/board/freescale/mpc837xemds/pci.c

   1/*
   2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <asm/mmu.h>
   8#include <asm/io.h>
   9#include <common.h>
  10#include <mpc83xx.h>
  11#include <pci.h>
  12#include <i2c.h>
  13#include <fdt_support.h>
  14#include <asm/fsl_i2c.h>
  15#include <asm/fsl_mpc83xx_serdes.h>
  16
  17static struct pci_region pci_regions[] = {
  18        {
  19                bus_start: CONFIG_SYS_PCI_MEM_BASE,
  20                phys_start: CONFIG_SYS_PCI_MEM_PHYS,
  21                size: CONFIG_SYS_PCI_MEM_SIZE,
  22                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  23        },
  24        {
  25                bus_start: CONFIG_SYS_PCI_MMIO_BASE,
  26                phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
  27                size: CONFIG_SYS_PCI_MMIO_SIZE,
  28                flags: PCI_REGION_MEM
  29        },
  30        {
  31                bus_start: CONFIG_SYS_PCI_IO_BASE,
  32                phys_start: CONFIG_SYS_PCI_IO_PHYS,
  33                size: CONFIG_SYS_PCI_IO_SIZE,
  34                flags: PCI_REGION_IO
  35        }
  36};
  37
  38static struct pci_region pcie_regions_0[] = {
  39        {
  40                .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  41                .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  42                .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  43                .flags = PCI_REGION_MEM,
  44        },
  45        {
  46                .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  47                .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  48                .size = CONFIG_SYS_PCIE1_IO_SIZE,
  49                .flags = PCI_REGION_IO,
  50        },
  51};
  52
  53static struct pci_region pcie_regions_1[] = {
  54        {
  55                .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
  56                .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
  57                .size = CONFIG_SYS_PCIE2_MEM_SIZE,
  58                .flags = PCI_REGION_MEM,
  59        },
  60        {
  61                .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
  62                .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
  63                .size = CONFIG_SYS_PCIE2_IO_SIZE,
  64                .flags = PCI_REGION_IO,
  65        },
  66};
  67
  68static int is_pex_x2(void)
  69{
  70        const char *pex_x2 = getenv("pex_x2");
  71
  72        if (pex_x2 && !strcmp(pex_x2, "yes"))
  73                return 1;
  74        return 0;
  75}
  76
  77void pci_init_board(void)
  78{
  79        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  80        volatile sysconf83xx_t *sysconf = &immr->sysconf;
  81        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  82        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  83        volatile law83xx_t *pcie_law = sysconf->pcielaw;
  84        struct pci_region *reg[] = { pci_regions };
  85        struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
  86        u32 spridr = in_be32(&immr->sysconf.spridr);
  87        int pex2 = is_pex_x2();
  88
  89        if (board_pci_host_broken())
  90                goto skip_pci;
  91
  92        /* Enable all 5 PCI_CLK_OUTPUTS */
  93        clk->occr |= 0xf8000000;
  94        udelay(2000);
  95
  96        /* Configure PCI Local Access Windows */
  97        pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
  98        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  99
 100        pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 101        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 102
 103        udelay(2000);
 104
 105        mpc83xx_pci_init(1, reg);
 106skip_pci:
 107        /* There is no PEX in MPC8379 parts. */
 108        if (PARTID_NO_E(spridr) == SPR_8379)
 109                return;
 110
 111        if (pex2)
 112                fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
 113                                 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 114        else
 115                fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 116                                 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 117
 118        /* Configure the clock for PCIE controller */
 119        clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
 120                                    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
 121
 122        /* Deassert the resets in the control register */
 123        out_be32(&sysconf->pecr1, 0xE0008000);
 124        if (!pex2)
 125                out_be32(&sysconf->pecr2, 0xE0008000);
 126        udelay(2000);
 127
 128        /* Configure PCI Express Local Access Windows */
 129        out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
 130        out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
 131
 132        out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
 133        out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
 134
 135        mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
 136}
 137
 138void ft_pcie_fixup(void *blob, bd_t *bd)
 139{
 140        const char *status = "disabled (PCIE1 is x2)";
 141
 142        if (!is_pex_x2())
 143                return;
 144
 145        do_fixup_by_path(blob, "pci2", "status", status,
 146                         strlen(status) + 1, 1);
 147}
 148