LXR uboot/board/imx31_phycore/imx31

   1/*
   2 *
   3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8
   9#include <common.h>
  10#include <s6e63d6.h>
  11#include <netdev.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/imx-regs.h>
  14#include <asm/arch/sys_proto.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18int dram_init(void)
  19{
  20        /* dram_init must store complete ramsize in gd->ram_size */
  21        gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  22                                PHYS_SDRAM_1_SIZE);
  23        return 0;
  24}
  25
  26int board_init(void)
  27{
  28
  29        gd->bd->bi_arch_number = MACH_TYPE_PCM037;      /* board id for linux */
  30        gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
  31
  32        return 0;
  33}
  34
  35int board_early_init_f(void)
  36{
  37        /* CS0: Nor Flash */
  38        static const struct mxc_weimcs cs0 = {
  39                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  40                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 15, 0,  0,  3),
  41                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  42                CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
  43                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  44                CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,  0)
  45        };
  46
  47        /* CS1: Network Controller */
  48        static const struct mxc_weimcs cs1 = {
  49                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  50                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 31, 0,  0,  6),
  51                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  52                CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
  53                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  54                CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,   1,  0)
  55        };
  56
  57        /* CS4: SRAM */
  58        static const struct mxc_weimcs cs4 = {
  59                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  60                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
  61                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  62                CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
  63                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  64                CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
  65        };
  66
  67        mxc_setup_weimcs(0, &cs0);
  68        mxc_setup_weimcs(1, &cs1);
  69        mxc_setup_weimcs(4, &cs4);
  70
  71        /* setup pins for UART1 */
  72        mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  73        mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  74        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  75        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  76
  77        /* setup pins for I2C2 (for EEPROM, RTC) */
  78        mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
  79        mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
  80
  81        return 0;
  82}
  83
  84#ifdef CONFIG_BOARD_LATE_INIT
  85int board_late_init(void)
  86{
  87#ifdef CONFIG_S6E63D6
  88        struct s6e63d6 data = {
  89                /*
  90                 * See comment in mxc_spi.c::decode_cs() for .cs field format.
  91                 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
  92                 * 2 of the SPI controller #1, since it is unused.
  93                 */
  94                .cs = 2 | (57 << 8),
  95                .bus = 0,
  96                .id = 0,
  97        };
  98        int ret;
  99
 100        /* SPI1 */
 101        mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
 102        mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
 103        mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
 104        mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
 105        mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
 106        mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
 107        mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
 108
 109        /* start SPI1 clock */
 110        __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
 111
 112        /* GPIO 57 */
 113        /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
 114        mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
 115
 116        /* SPI1 CS2 is free */
 117        ret = s6e63d6_init(&data);
 118        if (ret)
 119                return ret;
 120
 121        /*
 122         * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
 123         * OLED display connected to a S6E63D6 SPI display controller in the
 124         * 18 bit RGB mode
 125         */
 126        s6e63d6_index(&data, 2);
 127        s6e63d6_param(&data, 0x0182);
 128        s6e63d6_index(&data, 3);
 129        s6e63d6_param(&data, 0x8130);
 130        s6e63d6_index(&data, 0x10);
 131        s6e63d6_param(&data, 0x0000);
 132        s6e63d6_index(&data, 5);
 133        s6e63d6_param(&data, 0x0001);
 134        s6e63d6_index(&data, 0x22);
 135#endif
 136        return 0;
 137}
 138#endif
 139
 140int checkboard (void)
 141{
 142        printf("Board: Phytec phyCore i.MX31\n");
 143        return 0;
 144}
 145
 146int board_eth_init(bd_t *bis)
 147{
 148        int rc = 0;
 149#ifdef CONFIG_SMC911X
 150        rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 151#endif
 152        return rc;
 153}
 154