LXR uboot/board/kosagi/novena/video.c

   1/*
   2 * Novena video output support
   3 *
   4 * IT6251 code based on code Copyright (C) 2014 Sean Cross
   5 * from https://github.com/xobs/novena-linux.git commit
   6 * 3d85836ee1377d445531928361809612aa0a18db
   7 *
   8 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#include <common.h>
  14#include <linux/errno.h>
  15#include <asm/gpio.h>
  16#include <asm/io.h>
  17#include <asm/arch/clock.h>
  18#include <asm/arch/crm_regs.h>
  19#include <asm/arch/imx-regs.h>
  20#include <asm/arch/iomux.h>
  21#include <asm/arch/mxc_hdmi.h>
  22#include <asm/arch/sys_proto.h>
  23#include <asm/imx-common/iomux-v3.h>
  24#include <asm/imx-common/mxc_i2c.h>
  25#include <asm/imx-common/video.h>
  26#include <i2c.h>
  27#include <input.h>
  28#include <ipu_pixfmt.h>
  29#include <linux/fb.h>
  30#include <linux/input.h>
  31#include <malloc.h>
  32#include <stdio_dev.h>
  33
  34#include "novena.h"
  35
  36#define IT6251_VENDOR_ID_LOW                            0x00
  37#define IT6251_VENDOR_ID_HIGH                           0x01
  38#define IT6251_DEVICE_ID_LOW                            0x02
  39#define IT6251_DEVICE_ID_HIGH                           0x03
  40#define IT6251_SYSTEM_STATUS                            0x0d
  41#define IT6251_SYSTEM_STATUS_RINTSTATUS                 (1 << 0)
  42#define IT6251_SYSTEM_STATUS_RHPDSTATUS                 (1 << 1)
  43#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE               (1 << 2)
  44#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK                (1 << 3)
  45#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK                (1 << 4)
  46#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK                (1 << 5)
  47#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK              (1 << 6)
  48#define IT6251_REF_STATE                                0x0e
  49#define IT6251_REF_STATE_MAIN_LINK_DISABLED             (1 << 0)
  50#define IT6251_REF_STATE_AUX_CHANNEL_READ               (1 << 1)
  51#define IT6251_REF_STATE_CR_PATTERN                     (1 << 2)
  52#define IT6251_REF_STATE_EQ_PATTERN                     (1 << 3)
  53#define IT6251_REF_STATE_NORMAL_OPERATION               (1 << 4)
  54#define IT6251_REF_STATE_MUTED                          (1 << 5)
  55
  56#define IT6251_REG_PCLK_CNT_LOW                         0x57
  57#define IT6251_REG_PCLK_CNT_HIGH                        0x58
  58
  59#define IT6521_RETRY_MAX                                20
  60
  61static int it6251_is_stable(void)
  62{
  63        const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  64        const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  65        int status;
  66        int clkcnt;
  67        int rpclkcnt;
  68        int refstate;
  69
  70        rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
  71                   ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
  72        debug("RPCLKCnt: %d\n", rpclkcnt);
  73
  74        status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
  75        debug("System status: 0x%02x\n", status);
  76
  77        clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
  78                 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
  79                  0x0f00);
  80        debug("Clock: 0x%02x\n", clkcnt);
  81
  82        refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
  83        debug("Ref Link State: 0x%02x\n", refstate);
  84
  85        if ((refstate & 0x1f) != 0)
  86                return 0;
  87
  88        /* If video is muted, that's a failure */
  89        if (refstate & IT6251_REF_STATE_MUTED)
  90                return 0;
  91
  92        if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
  93                return 0;
  94
  95        return 1;
  96}
  97
  98static int it6251_ready(void)
  99{
 100        const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 101
 102        /* Test if the IT6251 came out of reset by reading ID regs. */
 103        if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
 104                return 0;
 105        if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
 106                return 0;
 107        if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
 108                return 0;
 109        if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
 110                return 0;
 111
 112        return 1;
 113}
 114
 115static void it6251_program_regs(void)
 116{
 117        const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 118        const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
 119
 120        i2c_reg_write(caddr, 0x05, 0x00);
 121        mdelay(1);
 122
 123        /* set LVDSRX address, and enable */
 124        i2c_reg_write(caddr, 0xfd, 0xbc);
 125        i2c_reg_write(caddr, 0xfe, 0x01);
 126
 127        /*
 128         * LVDSRX
 129         */
 130        /* This write always fails, because the chip goes into reset */
 131        /* reset LVDSRX */
 132        i2c_reg_write(laddr, 0x05, 0xff);
 133        i2c_reg_write(laddr, 0x05, 0x00);
 134
 135        /* reset LVDSRX PLL */
 136        i2c_reg_write(laddr, 0x3b, 0x42);
 137        i2c_reg_write(laddr, 0x3b, 0x43);
 138
 139        /* something with SSC PLL */
 140        i2c_reg_write(laddr, 0x3c, 0x08);
 141        /* don't swap links, but writing reserved registers */
 142        i2c_reg_write(laddr, 0x0b, 0x88);
 143
 144        /* JEIDA, 8-bit depth  0x11, orig 0x42 */
 145        i2c_reg_write(laddr, 0x2c, 0x01);
 146        /* "reserved" */
 147        i2c_reg_write(laddr, 0x32, 0x04);
 148        /* "reserved" */
 149        i2c_reg_write(laddr, 0x35, 0xe0);
 150        /* "reserved" + clock delay */
 151        i2c_reg_write(laddr, 0x2b, 0x24);
 152
 153        /* reset LVDSRX pix clock */
 154        i2c_reg_write(laddr, 0x05, 0x02);
 155        i2c_reg_write(laddr, 0x05, 0x00);
 156
 157        /*
 158         * DPTX
 159         */
 160        /* set for two lane mode, normal op, no swapping, no downspread */
 161        i2c_reg_write(caddr, 0x16, 0x02);
 162
 163        /* some AUX channel EDID magic */
 164        i2c_reg_write(caddr, 0x23, 0x40);
 165
 166        /* power down lanes 3-0 */
 167        i2c_reg_write(caddr, 0x5c, 0xf3);
 168
 169        /* enable DP scrambling, change EQ CR phase */
 170        i2c_reg_write(caddr, 0x5f, 0x06);
 171
 172        /* color mode RGB, pclk/2 */
 173        i2c_reg_write(caddr, 0x60, 0x02);
 174        /* dual pixel input mode, no EO swap, no RGB swap */
 175        i2c_reg_write(caddr, 0x61, 0x04);
 176        /* M444B24 video format */
 177        i2c_reg_write(caddr, 0x62, 0x01);
 178
 179        /* vesa range / not interlace / vsync high / hsync high */
 180        i2c_reg_write(caddr, 0xa0, 0x0F);
 181
 182        /* hpd event timer set to 1.6-ish ms */
 183        i2c_reg_write(caddr, 0xc9, 0xf5);
 184
 185        /* more reserved magic */
 186        i2c_reg_write(caddr, 0xca, 0x4d);
 187        i2c_reg_write(caddr, 0xcb, 0x37);
 188
 189        /* enhanced framing mode, auto video fifo reset, video mute disable */
 190        i2c_reg_write(caddr, 0xd3, 0x03);
 191
 192        /* "vidstmp" and some reserved stuff */
 193        i2c_reg_write(caddr, 0xd4, 0x45);
 194
 195        /* queue number -- reserved */
 196        i2c_reg_write(caddr, 0xe7, 0xa0);
 197        /* info frame packets  and reserved */
 198        i2c_reg_write(caddr, 0xe8, 0x33);
 199        /* more AVI stuff */
 200        i2c_reg_write(caddr, 0xec, 0x00);
 201
 202        /* select PC master reg for aux channel? */
 203        i2c_reg_write(caddr, 0x23, 0x42);
 204
 205        /* send PC request commands */
 206        i2c_reg_write(caddr, 0x24, 0x00);
 207        i2c_reg_write(caddr, 0x25, 0x00);
 208        i2c_reg_write(caddr, 0x26, 0x00);
 209
 210        /* native aux read */
 211        i2c_reg_write(caddr, 0x2b, 0x00);
 212        /* back to internal */
 213        i2c_reg_write(caddr, 0x23, 0x40);
 214
 215        /* voltage swing level 3 */
 216        i2c_reg_write(caddr, 0x19, 0xff);
 217        /* pre-emphasis level 3 */
 218        i2c_reg_write(caddr, 0x1a, 0xff);
 219
 220        /* start link training */
 221        i2c_reg_write(caddr, 0x17, 0x01);
 222}
 223
 224static int it6251_init(void)
 225{
 226        const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
 227        int reg;
 228        int tries, retries = 0;
 229
 230        for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
 231                /* Program the chip. */
 232                it6251_program_regs();
 233
 234                /* Wait for video stable. */
 235                for (tries = 0; tries < 100; tries++) {
 236                        reg = i2c_reg_read(caddr, 0x17);
 237                        /* Test Link CFG, STS, LCS read done. */
 238                        if ((reg & 0xe0) != 0xe0) {
 239                                /* Not yet, wait a bit more. */
 240                                mdelay(2);
 241                                continue;
 242                        }
 243
 244                        /* Test if the video input is stable. */
 245                        if (it6251_is_stable())
 246                                return 0;
 247                }
 248                /*
 249                 * If we couldn't stabilize, requeue and try again,
 250                 * because it means that the LVDS channel isn't
 251                 * stable yet.
 252                 */
 253                printf("Display didn't stabilize.\n");
 254                printf("This may be because the LVDS port is still in powersave mode.\n");
 255                mdelay(50);
 256        }
 257
 258        return -EINVAL;
 259}
 260
 261static void enable_hdmi(struct display_info_t const *dev)
 262{
 263        imx_enable_hdmi_phy();
 264}
 265
 266static int lvds_enabled;
 267
 268static void enable_lvds(struct display_info_t const *dev)
 269{
 270        if (lvds_enabled)
 271                return;
 272
 273        /* ITE IT6251 power enable. */
 274        gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
 275        mdelay(10);
 276        gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
 277        mdelay(20);
 278        lvds_enabled = 1;
 279}
 280
 281static int detect_lvds(struct display_info_t const *dev)
 282{
 283        int ret, loops = 250;
 284
 285        enable_lvds(dev);
 286
 287        ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
 288        if (ret) {
 289                puts("Cannot select IT6251 I2C bus.\n");
 290                return 0;
 291        }
 292
 293        /* Wait up-to ~250 mS for the LVDS to come up. */
 294        while (--loops) {
 295                ret = it6251_ready();
 296                if (ret)
 297                        return ret;
 298
 299                mdelay(1);
 300        }
 301
 302        return 0;
 303}
 304
 305struct display_info_t const displays[] = {
 306        {
 307                /* HDMI Output */
 308                .bus    = -1,
 309                .addr   = 0,
 310                .pixfmt = IPU_PIX_FMT_RGB24,
 311                .detect = detect_hdmi,
 312                .enable = enable_hdmi,
 313                .mode   = {
 314                        .name           = "HDMI",
 315                        .refresh        = 60,
 316                        .xres           = 1024,
 317                        .yres           = 768,
 318                        .pixclock       = 15384,
 319                        .left_margin    = 220,
 320                        .right_margin   = 40,
 321                        .upper_margin   = 21,
 322                        .lower_margin   = 7,
 323                        .hsync_len      = 60,
 324                        .vsync_len      = 10,
 325                        .sync           = FB_SYNC_EXT,
 326                        .vmode          = FB_VMODE_NONINTERLACED
 327                },
 328        }, {
 329                /* LVDS Output: N133HSE-EA1 Rev. C1 */
 330                .bus    = -1,
 331                .pixfmt = IPU_PIX_FMT_RGB24,
 332                .detect = detect_lvds,
 333                .enable = enable_lvds,
 334                .mode   = {
 335                        .name           = "Chimei-FHD",
 336                        .refresh        = 60,
 337                        .xres           = 1920,
 338                        .yres           = 1080,
 339                        .pixclock       = 15384,
 340                        .left_margin    = 148,
 341                        .right_margin   = 88,
 342                        .upper_margin   = 36,
 343                        .lower_margin   = 4,
 344                        .hsync_len      = 44,
 345                        .vsync_len      = 5,
 346                        .sync           = FB_SYNC_HOR_HIGH_ACT |
 347                                          FB_SYNC_VERT_HIGH_ACT |
 348                                          FB_SYNC_EXT,
 349                        .vmode          = FB_VMODE_NONINTERLACED,
 350                },
 351        },
 352};
 353
 354size_t display_count = ARRAY_SIZE(displays);
 355
 356static void enable_vpll(void)
 357{
 358        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 359        int timeout = 100000;
 360
 361        setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 362
 363        clrsetbits_le32(&ccm->analog_pll_video,
 364                        BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 365                        BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 366                        BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 367                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 368
 369        writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 370        writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 371
 372        clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 373
 374        while (timeout--)
 375                if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 376                        break;
 377        if (timeout < 0)
 378                printf("Warning: video pll lock timeout!\n");
 379
 380        clrsetbits_le32(&ccm->analog_pll_video,
 381                        BM_ANADIG_PLL_VIDEO_BYPASS,
 382                        BM_ANADIG_PLL_VIDEO_ENABLE);
 383}
 384
 385void setup_display_clock(void)
 386{
 387        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 388        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 389
 390        enable_ipu_clock();
 391        enable_vpll();
 392        imx_setup_hdmi();
 393
 394        /* Turn on IPU LDB DI0 clocks */
 395        setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 396
 397        /* Switch LDB DI0 to PLL5 (Video PLL) */
 398        clrsetbits_le32(&mxc_ccm->cs2cdr,
 399                        MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 400                        (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 401
 402        /* LDB clock div by 3.5 */
 403        clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 404
 405        /* DI0 clock derived from ldb_di0_clk */
 406        clrsetbits_le32(&mxc_ccm->chsccdr,
 407                        MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 408                        (CHSCCDR_CLK_SEL_LDB_DI0 <<
 409                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 410                        );
 411
 412        /* Enable both LVDS channels, both connected to DI0. */
 413        writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
 414               IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
 415               IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 416               IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
 417               IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 418               IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 419               IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
 420               IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 421               &iomux->gpr[2]);
 422
 423        clrsetbits_le32(&iomux->gpr[3],
 424                        IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 425                        IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
 426                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 427                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
 428                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 429                         IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 430                        );
 431}
 432
 433void setup_display_lvds(void)
 434{
 435        int ret;
 436
 437        ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
 438        if (ret) {
 439                puts("Cannot select LVDS-to-eDP I2C bus.\n");
 440                return;
 441        }
 442
 443        /* The IT6251 should be ready now, if it's not, it's not connected. */
 444        ret = it6251_ready();
 445        if (!ret)
 446                return;
 447
 448        /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
 449        ret = it6251_init();
 450        if (!ret) {
 451                /* Backlight power enable. */
 452                gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
 453                /* PWM backlight pin, always on for full brightness. */
 454                gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
 455        }
 456}
 457