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8
9#include <common.h>
10#include <asm/gpio.h>
11#include <asm/io.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux-mx28.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/sys_proto.h>
16#include <linux/mii.h>
17#include <miiphy.h>
18#include <netdev.h>
19#include <errno.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23
24
25
26int board_early_init_f(void)
27{
28
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
30
31 mxs_set_ioclk(MXC_IOCLK1, 480000);
32
33
34 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
35
36 return 0;
37}
38
39int dram_init(void)
40{
41 return mxs_dram_init();
42}
43
44int board_init(void)
45{
46
47 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
48
49 return 0;
50}
51
52#ifdef CONFIG_CMD_NET
53int board_eth_init(bd_t *bis)
54{
55 struct mxs_clkctrl_regs *clkctrl_regs =
56 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
57 struct eth_device *dev;
58 int ret;
59
60 ret = cpu_eth_init(bis);
61
62
63 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
64 &clkctrl_regs->hw_clkctrl_enet);
65
66
67 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
68 udelay(200);
69 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
70
71 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
72 if (ret) {
73 puts("FEC MXS: Unable to init FEC0\n");
74 return ret;
75 }
76
77 dev = eth_get_dev_by_name("FEC0");
78 if (!dev) {
79 puts("FEC MXS: Unable to get FEC0 device entry\n");
80 return -EINVAL;
81 }
82
83 return ret;
84}
85
86#endif
87