1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <common.h>
15#include <dm.h>
16#include <asm/io.h>
17#include <asm/arch/at91sam9g45_matrix.h>
18#include <asm/arch/at91sam9_smc.h>
19#include <asm/arch/at91_common.h>
20#include <asm/arch/at91_rstc.h>
21#include <asm/arch/atmel_serial.h>
22#include <asm/arch/gpio.h>
23#include <asm/gpio.h>
24#include <asm/arch/clk.h>
25#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
26#include <net.h>
27#endif
28#ifndef CONFIG_DM_ETH
29#include <netdev.h>
30#endif
31#include <spi.h>
32
33#ifdef CONFIG_USB_GADGET_ATMEL_USBA
34#include <asm/arch/atmel_usba_udc.h>
35#endif
36
37DECLARE_GLOBAL_DATA_PTR;
38
39static void corvus_request_gpio(void)
40{
41 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
42 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
43 gpio_request(AT91_PIN_PD7, "d0");
44 gpio_request(AT91_PIN_PD8, "d1");
45 gpio_request(AT91_PIN_PA12, "d2");
46 gpio_request(AT91_PIN_PA13, "d3");
47 gpio_request(AT91_PIN_PA15, "d4");
48 gpio_request(AT91_PIN_PB7, "recovery button");
49 gpio_request(AT91_PIN_PD1, "USB0");
50 gpio_request(AT91_PIN_PD3, "USB1");
51 gpio_request(AT91_PIN_PB18, "SPICS1");
52 gpio_request(AT91_PIN_PB3, "SPICS0");
53 gpio_request(CONFIG_RED_LED, "red led");
54 gpio_request(CONFIG_GREEN_LED, "green led");
55}
56
57static void corvus_nand_hw_init(void)
58{
59 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
60 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
61 unsigned long csa;
62
63
64 csa = readl(&matrix->ebicsa);
65 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
66 writel(csa, &matrix->ebicsa);
67
68
69 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
70 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
71 &smc->cs[3].setup);
72 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
73 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
74 &smc->cs[3].pulse);
75 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
76 &smc->cs[3].cycle);
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
79#ifdef CONFIG_SYS_NAND_DBW_16
80 AT91_SMC_MODE_DBW_16 |
81#else
82 AT91_SMC_MODE_DBW_8 |
83#endif
84 AT91_SMC_MODE_TDF_CYCLE(3),
85 &smc->cs[3].mode);
86
87 at91_periph_clk_enable(ATMEL_ID_PIOC);
88 at91_periph_clk_enable(ATMEL_ID_PIOA);
89
90
91 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
92 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
93}
94
95#if defined(CONFIG_SPL_BUILD)
96#include <spl.h>
97#include <nand.h>
98
99void spl_board_init(void)
100{
101 corvus_request_gpio();
102
103
104
105
106 at91_set_gpio_output(AT91_PIN_PD7, 0);
107 at91_set_gpio_output(AT91_PIN_PD8, 0);
108 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
109 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
110 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
111 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
112 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
113
114 corvus_nand_hw_init();
115
116
117 at91_set_gpio_input(AT91_PIN_PB7, 1);
118
119
120 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
121 u32 boot_device;
122
123 debug("Recovery button pressed\n");
124 boot_device = spl_boot_device();
125 switch (boot_device) {
126#ifdef CONFIG_SPL_NAND_SUPPORT
127 case BOOT_DEVICE_NAND:
128 nand_init();
129 spl_nand_erase_one(0, 0);
130 break;
131#endif
132 }
133 }
134}
135
136#include <asm/arch/atmel_mpddrc.h>
137static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
138{
139 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
140
141 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
142 ATMEL_MPDDRC_CR_NR_ROW_14 |
143 ATMEL_MPDDRC_CR_DIC_DS |
144 ATMEL_MPDDRC_CR_DQMS_SHARED |
145 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
146 ddr2->rtr = 0x24b;
147
148 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
149 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
150 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
151 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
152 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
153 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
154 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
155 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
156
157 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
158 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
159 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
160 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
161
162 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
163 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
164 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
165 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
166}
167
168void mem_init(void)
169{
170 struct atmel_mpddrc_config ddr2;
171
172 ddr2_conf(&ddr2);
173
174 at91_system_clk_enable(AT91_PMC_DDR);
175
176
177 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
178}
179#endif
180
181#ifdef CONFIG_CMD_USB
182static void taurus_usb_hw_init(void)
183{
184 at91_periph_clk_enable(ATMEL_ID_PIODE);
185
186 at91_set_gpio_output(AT91_PIN_PD1, 0);
187 at91_set_gpio_output(AT91_PIN_PD3, 0);
188}
189#endif
190
191#ifdef CONFIG_MACB
192static void corvus_macb_hw_init(void)
193{
194
195 at91_periph_clk_enable(ATMEL_ID_EMAC);
196
197
198
199
200
201
202
203
204
205 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
206 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
207 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
208
209 at91_phy_reset();
210
211
212 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
213 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
214 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
215
216
217 at91_macb_hw_init();
218}
219#endif
220
221int board_early_init_f(void)
222{
223 at91_seriald_hw_init();
224 corvus_request_gpio();
225 return 0;
226}
227
228#ifdef CONFIG_USB_GADGET_ATMEL_USBA
229
230void at91_udp_hw_init(void)
231{
232
233 at91_upll_clk_enable();
234
235
236 at91_periph_clk_enable(ATMEL_ID_UDPHS);
237}
238#endif
239
240int board_init(void)
241{
242
243 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
244
245
246 corvus_request_gpio();
247#ifdef CONFIG_CMD_NAND
248 corvus_nand_hw_init();
249#endif
250#ifdef CONFIG_ATMEL_SPI
251 at91_spi0_hw_init(1 << 4);
252#endif
253#ifdef CONFIG_HAS_DATAFLASH
254 at91_spi0_hw_init(1 << 0);
255#endif
256#ifdef CONFIG_MACB
257 corvus_macb_hw_init();
258#endif
259#ifdef CONFIG_CMD_USB
260 taurus_usb_hw_init();
261#endif
262#ifdef CONFIG_USB_GADGET_ATMEL_USBA
263 at91_udp_hw_init();
264 usba_udc_probe(&pdata);
265#endif
266 return 0;
267}
268
269int dram_init(void)
270{
271 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
272 CONFIG_SYS_SDRAM_SIZE);
273 return 0;
274}
275
276#ifndef CONFIG_DM_ETH
277int board_eth_init(bd_t *bis)
278{
279 int rc = 0;
280#ifdef CONFIG_MACB
281 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
282#endif
283 return rc;
284}
285#endif
286
287
288int spi_cs_is_valid(unsigned int bus, unsigned int cs)
289{
290 return bus == 0 && cs < 2;
291}
292
293void spi_cs_activate(struct spi_slave *slave)
294{
295 switch (slave->cs) {
296 case 1:
297 at91_set_gpio_output(AT91_PIN_PB18, 0);
298 break;
299 case 0:
300 default:
301 at91_set_gpio_output(AT91_PIN_PB3, 0);
302 break;
303 }
304}
305
306void spi_cs_deactivate(struct spi_slave *slave)
307{
308 switch (slave->cs) {
309 case 1:
310 at91_set_gpio_output(AT91_PIN_PB18, 1);
311 break;
312 case 0:
313 default:
314 at91_set_gpio_output(AT91_PIN_PB3, 1);
315 break;
316 }
317}
318
319static struct atmel_serial_platdata at91sam9260_serial_plat = {
320 .base_addr = ATMEL_BASE_DBGU,
321};
322
323U_BOOT_DEVICE(at91sam9260_serial) = {
324 .name = "serial_atmel",
325 .platdata = &at91sam9260_serial_plat,
326};
327