LXR uboot/board/varisys/cyrus/cyrus.c

   1/*
   2 * Based on corenet_ds.c
   3 *
   4 * SPDX-License-Identifier:    GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <command.h>
   9#include <netdev.h>
  10#include <linux/compiler.h>
  11#include <asm/mmu.h>
  12#include <asm/processor.h>
  13#include <asm/cache.h>
  14#include <asm/immap_85xx.h>
  15#include <asm/fsl_law.h>
  16#include <asm/fsl_serdes.h>
  17#include <asm/fsl_portals.h>
  18#include <asm/fsl_liodn.h>
  19#include <fm_eth.h>
  20#include <pci.h>
  21
  22#include "cyrus.h"
  23#include "../common/eeprom.h"
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27#define GPIO_OPENDRAIN 0x30000000
  28#define GPIO_DIR       0x3c000004
  29#define GPIO_INITIAL   0x30000000
  30#define GPIO_VGA_SWITCH 0x00001000
  31
  32int checkboard(void)
  33{
  34        printf("Board: CYRUS\n");
  35
  36        return 0;
  37}
  38
  39int board_early_init_f(void)
  40{
  41        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  42        ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  43
  44        /*
  45         * Only use DDR1_MCK0/3 and DDR2_MCK0/3
  46         * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  47         * the noise introduced by these unterminated and unused clock pairs.
  48         */
  49        setbits_be32(&gur->ddrclkdr, 0x001B001B);
  50
  51        /* Set GPIO reset lines to open-drain, tristate */
  52        setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
  53        setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
  54
  55        /* Set GPIO Direction */
  56        setbits_be32(&pgpio->gpdir, GPIO_DIR);
  57
  58        return 0;
  59}
  60
  61int board_early_init_r(void)
  62{
  63        fsl_lbc_t *lbc = LBC_BASE_ADDR;
  64
  65        out_be32(&lbc->lbcr, 0);
  66        /* 1 clock LALE cycle */
  67        out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
  68
  69        set_liodns();
  70
  71#ifdef CONFIG_SYS_DPAA_QBMAN
  72        setup_portals();
  73#endif
  74        print_lbc_regs();
  75        return 0;
  76}
  77
  78int misc_init_r(void)
  79{
  80        return 0;
  81}
  82
  83int ft_board_setup(void *blob, bd_t *bd)
  84{
  85        phys_addr_t base;
  86        phys_size_t size;
  87
  88        ft_cpu_setup(blob, bd);
  89
  90        base = getenv_bootm_low();
  91        size = getenv_bootm_size();
  92
  93        fdt_fixup_memory(blob, (u64)base, (u64)size);
  94
  95#ifdef CONFIG_PCI
  96        pci_of_setup(blob, bd);
  97#endif
  98
  99        fdt_fixup_liodn(blob);
 100        fsl_fdt_fixup_dr_usb(blob, bd);
 101
 102#ifdef CONFIG_SYS_DPAA_FMAN
 103        fdt_fixup_fman_ethernet(blob);
 104#endif
 105
 106        return 0;
 107}
 108
 109int mac_read_from_eeprom(void)
 110{
 111        init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
 112                CONFIG_SYS_I2C_EEPROM_ADDR,
 113                CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
 114
 115        return mac_read_from_eeprom_common();
 116}
 117