1/****************************************************************************** 2* 3* Copyright (C) 2015 Xilinx, Inc. All rights reserved. 4* 5* This program is free software; you can redistribute it and/or modify 6* it under the terms of the GNU General Public License as published by 7* the Free Software Foundation; either version 2 of the License, or 8* (at your option) any later version. 9* 10* This program is distributed in the hope that it will be useful, 11* but WITHOUT ANY WARRANTY; without even the implied warranty of 12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13* GNU General Public License for more details. 14* 15* You should have received a copy of the GNU General Public License along 16* with this program; if not, see <http://www.gnu.org/licenses/> 17* 18* 19******************************************************************************/ 20/****************************************************************************/ 21/** 22* 23* @file psu_init_gpl.h 24* 25* This file is automatically generated 26* 27*****************************************************************************/ 28 29 30#undef CRL_APB_RPLL_CFG_OFFSET 31#define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034 32#undef CRL_APB_RPLL_CTRL_OFFSET 33#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 34#undef CRL_APB_RPLL_CTRL_OFFSET 35#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 36#undef CRL_APB_RPLL_CTRL_OFFSET 37#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 38#undef CRL_APB_RPLL_CTRL_OFFSET 39#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 40#undef CRL_APB_RPLL_CTRL_OFFSET 41#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 42#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 43#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 44#undef CRL_APB_RPLL_FRAC_CFG_OFFSET 45#define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038 46#undef CRL_APB_IOPLL_CFG_OFFSET 47#define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 48#undef CRL_APB_IOPLL_CTRL_OFFSET 49#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 50#undef CRL_APB_IOPLL_CTRL_OFFSET 51#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 52#undef CRL_APB_IOPLL_CTRL_OFFSET 53#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 54#undef CRL_APB_IOPLL_CTRL_OFFSET 55#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 56#undef CRL_APB_IOPLL_CTRL_OFFSET 57#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 58#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 59#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 60#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET 61#define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028 62#undef CRF_APB_APLL_CFG_OFFSET 63#define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 64#undef CRF_APB_APLL_CTRL_OFFSET 65#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 66#undef CRF_APB_APLL_CTRL_OFFSET 67#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 68#undef CRF_APB_APLL_CTRL_OFFSET 69#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 70#undef CRF_APB_APLL_CTRL_OFFSET 71#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 72#undef CRF_APB_APLL_CTRL_OFFSET 73#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 74#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 75#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 76#undef CRF_APB_APLL_FRAC_CFG_OFFSET 77#define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028 78#undef CRF_APB_DPLL_CFG_OFFSET 79#define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 80#undef CRF_APB_DPLL_CTRL_OFFSET 81#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C 82#undef CRF_APB_DPLL_CTRL_OFFSET 83#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C 84#undef CRF_APB_DPLL_CTRL_OFFSET 85#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C 86#undef CRF_APB_DPLL_CTRL_OFFSET 87#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C 88#undef CRF_APB_DPLL_CTRL_OFFSET 89#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C 90#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 91#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C 92#undef CRF_APB_DPLL_FRAC_CFG_OFFSET 93#define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034 94#undef CRF_APB_VPLL_CFG_OFFSET 95#define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C 96#undef CRF_APB_VPLL_CTRL_OFFSET 97#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 98#undef CRF_APB_VPLL_CTRL_OFFSET 99#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 100#undef CRF_APB_VPLL_CTRL_OFFSET 101#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 102#undef CRF_APB_VPLL_CTRL_OFFSET 103#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 104#undef CRF_APB_VPLL_CTRL_OFFSET 105#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 106#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 107#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 108#undef CRF_APB_VPLL_FRAC_CFG_OFFSET 109#define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040 110 111/*PLL loop filter resistor control*/ 112#undef CRL_APB_RPLL_CFG_RES_DEFVAL 113#undef CRL_APB_RPLL_CFG_RES_SHIFT 114#undef CRL_APB_RPLL_CFG_RES_MASK 115#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 116#define CRL_APB_RPLL_CFG_RES_SHIFT 0 117#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU 118 119/*PLL charge pump control*/ 120#undef CRL_APB_RPLL_CFG_CP_DEFVAL 121#undef CRL_APB_RPLL_CFG_CP_SHIFT 122#undef CRL_APB_RPLL_CFG_CP_MASK 123#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 124#define CRL_APB_RPLL_CFG_CP_SHIFT 5 125#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U 126 127/*PLL loop filter high frequency capacitor control*/ 128#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 129#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 130#undef CRL_APB_RPLL_CFG_LFHF_MASK 131#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 132#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 133#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U 134 135/*Lock circuit counter setting*/ 136#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 137#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 138#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 139#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 140#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 141#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U 142 143/*Lock circuit configuration settings for lock windowsize*/ 144#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 145#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 146#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 147#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 148#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 149#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U 150 151/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ 152 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ 153#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 154#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 155#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 156#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 157#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 158#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U 159 160/*The integer portion of the feedback divider to the PLL*/ 161#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 162#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 163#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 164#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 165#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 166#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U 167 168/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ 169#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 170#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 171#undef CRL_APB_RPLL_CTRL_DIV2_MASK 172#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 173#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 174#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U 175 176/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 177 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 178#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 179#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 180#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 181#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 182#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 183#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U 184 185/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 186#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 187#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 188#undef CRL_APB_RPLL_CTRL_RESET_MASK 189#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 190#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 191#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U 192 193/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 194#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 195#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 196#undef CRL_APB_RPLL_CTRL_RESET_MASK 197#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 198#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 199#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U 200 201/*RPLL is locked*/ 202#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 203#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 204#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 205#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 206#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 207#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U 208#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 209 210/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 211 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 212#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 213#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 214#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 215#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 216#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 217#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U 218 219/*Divisor value for this clock.*/ 220#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 221#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 222#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 223#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 224#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 225#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U 226 227/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona 228 mode and uses DATA of this register for the fractional portion of the feedback divider.*/ 229#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 230#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 231#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 232#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 233#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 234#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U 235 236/*Fractional value for the Feedback value.*/ 237#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 238#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 239#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK 240#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 241#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 242#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU 243 244/*PLL loop filter resistor control*/ 245#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 246#undef CRL_APB_IOPLL_CFG_RES_SHIFT 247#undef CRL_APB_IOPLL_CFG_RES_MASK 248#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 249#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 250#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU 251 252/*PLL charge pump control*/ 253#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 254#undef CRL_APB_IOPLL_CFG_CP_SHIFT 255#undef CRL_APB_IOPLL_CFG_CP_MASK 256#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 257#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 258#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U 259 260/*PLL loop filter high frequency capacitor control*/ 261#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 262#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 263#undef CRL_APB_IOPLL_CFG_LFHF_MASK 264#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 265#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 266#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U 267 268/*Lock circuit counter setting*/ 269#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 270#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 271#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 272#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 273#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 274#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U 275 276/*Lock circuit configuration settings for lock windowsize*/ 277#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 278#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 279#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 280#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 281#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 282#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U 283 284/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ 285 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ 286#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 287#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 288#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 289#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 290#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 291#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U 292 293/*The integer portion of the feedback divider to the PLL*/ 294#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 295#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 296#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 297#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 298#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 299#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U 300 301/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ 302#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 303#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 304#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 305#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 306#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 307#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U 308 309/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 310 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 311#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 312#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 313#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 314#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 315#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 316#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U 317 318/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 319#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 320#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 321#undef CRL_APB_IOPLL_CTRL_RESET_MASK 322#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 323#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 324#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U 325 326/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 327#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 328#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 329#undef CRL_APB_IOPLL_CTRL_RESET_MASK 330#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 331#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 332#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U 333 334/*IOPLL is locked*/ 335#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 336#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 337#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 338#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 339#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 340#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U 341#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 342 343/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 344 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 345#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 346#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 347#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 348#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 349#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 350#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U 351 352/*Divisor value for this clock.*/ 353#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 354#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 355#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 356#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 357#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 358#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U 359 360/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona 361 mode and uses DATA of this register for the fractional portion of the feedback divider.*/ 362#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 363#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 364#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 365#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 366#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 367#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U 368 369/*Fractional value for the Feedback value.*/ 370#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 371#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 372#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 373#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 374#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 375#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU 376 377/*PLL loop filter resistor control*/ 378#undef CRF_APB_APLL_CFG_RES_DEFVAL 379#undef CRF_APB_APLL_CFG_RES_SHIFT 380#undef CRF_APB_APLL_CFG_RES_MASK 381#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 382#define CRF_APB_APLL_CFG_RES_SHIFT 0 383#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU 384 385/*PLL charge pump control*/ 386#undef CRF_APB_APLL_CFG_CP_DEFVAL 387#undef CRF_APB_APLL_CFG_CP_SHIFT 388#undef CRF_APB_APLL_CFG_CP_MASK 389#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 390#define CRF_APB_APLL_CFG_CP_SHIFT 5 391#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U 392 393/*PLL loop filter high frequency capacitor control*/ 394#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 395#undef CRF_APB_APLL_CFG_LFHF_SHIFT 396#undef CRF_APB_APLL_CFG_LFHF_MASK 397#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 398#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 399#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U 400 401/*Lock circuit counter setting*/ 402#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 403#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 404#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 405#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 406#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 407#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U 408 409/*Lock circuit configuration settings for lock windowsize*/ 410#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 411#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 412#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 413#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 414#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 415#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U 416 417/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ 418 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ 419#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 420#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 421#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 422#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 423#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 424#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U 425 426/*The integer portion of the feedback divider to the PLL*/ 427#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 428#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 429#undef CRF_APB_APLL_CTRL_FBDIV_MASK 430#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 431#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 432#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U 433 434/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ 435#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 436#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 437#undef CRF_APB_APLL_CTRL_DIV2_MASK 438#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 439#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 440#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U 441 442/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 443 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 444#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 445#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 446#undef CRF_APB_APLL_CTRL_BYPASS_MASK 447#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 448#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 449#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U 450 451/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 452#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 453#undef CRF_APB_APLL_CTRL_RESET_SHIFT 454#undef CRF_APB_APLL_CTRL_RESET_MASK 455#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 456#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 457#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U 458 459/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 460#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 461#undef CRF_APB_APLL_CTRL_RESET_SHIFT 462#undef CRF_APB_APLL_CTRL_RESET_MASK 463#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 464#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 465#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U 466 467/*APLL is locked*/ 468#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 469#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 470#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 471#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 472#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 473#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U 474#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 475 476/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 477 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 478#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 479#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 480#undef CRF_APB_APLL_CTRL_BYPASS_MASK 481#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 482#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 483#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U 484 485/*Divisor value for this clock.*/ 486#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 487#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 488#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 489#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 490#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 491#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U 492 493/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona 494 mode and uses DATA of this register for the fractional portion of the feedback divider.*/ 495#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 496#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 497#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 498#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 499#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 500#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U 501 502/*Fractional value for the Feedback value.*/ 503#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 504#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 505#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK 506#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000 507#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 508#define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU 509 510/*PLL loop filter resistor control*/ 511#undef CRF_APB_DPLL_CFG_RES_DEFVAL 512#undef CRF_APB_DPLL_CFG_RES_SHIFT 513#undef CRF_APB_DPLL_CFG_RES_MASK 514#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 515#define CRF_APB_DPLL_CFG_RES_SHIFT 0 516#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU 517 518/*PLL charge pump control*/ 519#undef CRF_APB_DPLL_CFG_CP_DEFVAL 520#undef CRF_APB_DPLL_CFG_CP_SHIFT 521#undef CRF_APB_DPLL_CFG_CP_MASK 522#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 523#define CRF_APB_DPLL_CFG_CP_SHIFT 5 524#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U 525 526/*PLL loop filter high frequency capacitor control*/ 527#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 528#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 529#undef CRF_APB_DPLL_CFG_LFHF_MASK 530#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 531#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 532#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U 533 534/*Lock circuit counter setting*/ 535#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 536#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 537#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 538#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 539#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 540#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U 541 542/*Lock circuit configuration settings for lock windowsize*/ 543#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 544#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 545#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 546#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 547#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 548#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U 549 550/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ 551 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ 552#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 553#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 554#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 555#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 556#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 557#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U 558 559/*The integer portion of the feedback divider to the PLL*/ 560#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 561#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 562#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 563#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 564#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 565#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U 566 567/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ 568#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 569#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 570#undef CRF_APB_DPLL_CTRL_DIV2_MASK 571#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 572#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 573#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U 574 575/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 576 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 577#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 578#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 579#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 580#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 581#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 582#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U 583 584/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 585#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 586#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 587#undef CRF_APB_DPLL_CTRL_RESET_MASK 588#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 589#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 590#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U 591 592/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 593#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 594#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 595#undef CRF_APB_DPLL_CTRL_RESET_MASK 596#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 597#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 598#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U 599 600/*DPLL is locked*/ 601#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 602#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 603#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 604#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 605#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 606#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U 607#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 608 609/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 610 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 611#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 612#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 613#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 614#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 615#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 616#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U 617 618/*Divisor value for this clock.*/ 619#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 620#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 621#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 622#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 623#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 624#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U 625 626/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona 627 mode and uses DATA of this register for the fractional portion of the feedback divider.*/ 628#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 629#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 630#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 631#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 632#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 633#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U 634 635/*Fractional value for the Feedback value.*/ 636#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 637#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 638#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK 639#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 640#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 641#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU 642 643/*PLL loop filter resistor control*/ 644#undef CRF_APB_VPLL_CFG_RES_DEFVAL 645#undef CRF_APB_VPLL_CFG_RES_SHIFT 646#undef CRF_APB_VPLL_CFG_RES_MASK 647#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 648#define CRF_APB_VPLL_CFG_RES_SHIFT 0 649#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU 650 651/*PLL charge pump control*/ 652#undef CRF_APB_VPLL_CFG_CP_DEFVAL 653#undef CRF_APB_VPLL_CFG_CP_SHIFT 654#undef CRF_APB_VPLL_CFG_CP_MASK 655#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 656#define CRF_APB_VPLL_CFG_CP_SHIFT 5 657#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U 658 659/*PLL loop filter high frequency capacitor control*/ 660#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 661#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 662#undef CRF_APB_VPLL_CFG_LFHF_MASK 663#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 664#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 665#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U 666 667/*Lock circuit counter setting*/ 668#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 669#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 670#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 671#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 672#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 673#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U 674 675/*Lock circuit configuration settings for lock windowsize*/ 676#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 677#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 678#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 679#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 680#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 681#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U 682 683/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ 684 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ 685#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 686#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 687#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 688#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 689#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 690#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U 691 692/*The integer portion of the feedback divider to the PLL*/ 693#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 694#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 695#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 696#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 697#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 698#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U 699 700/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ 701#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 702#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 703#undef CRF_APB_VPLL_CTRL_DIV2_MASK 704#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 705#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 706#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U 707 708/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 709 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 710#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 711#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 712#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 713#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 714#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 715#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U 716 717/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 718#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 719#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 720#undef CRF_APB_VPLL_CTRL_RESET_MASK 721#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 722#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 723#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U 724 725/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ 726#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 727#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 728#undef CRF_APB_VPLL_CTRL_RESET_MASK 729#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 730#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 731#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U 732 733/*VPLL is locked*/ 734#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 735#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 736#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 737#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 738#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 739#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U 740#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 741 742/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 743 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 744#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 745#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 746#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 747#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 748#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 749#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U 750 751/*Divisor value for this clock.*/ 752#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 753#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 754#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 755#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 756#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 757#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U 758 759/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona 760 mode and uses DATA of this register for the fractional portion of the feedback divider.*/ 761#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 762#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 763#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 764#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 765#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 766#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U 767 768/*Fractional value for the Feedback value.*/ 769#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 770#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 771#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK 772#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 773#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 774#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU 775#undef CRL_APB_GEM0_REF_CTRL_OFFSET 776#define CRL_APB_GEM0_REF_CTRL_OFFSET 0XFF5E0050 777#undef CRL_APB_GEM1_REF_CTRL_OFFSET 778#define CRL_APB_GEM1_REF_CTRL_OFFSET 0XFF5E0054 779#undef CRL_APB_GEM2_REF_CTRL_OFFSET 780#define CRL_APB_GEM2_REF_CTRL_OFFSET 0XFF5E0058 781#undef CRL_APB_GEM3_REF_CTRL_OFFSET 782#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C 783#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 784#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 785#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 786#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 787#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET 788#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET 0XFF5E0064 789#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 790#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C 791#undef CRL_APB_QSPI_REF_CTRL_OFFSET 792#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068 793#undef CRL_APB_SDIO0_REF_CTRL_OFFSET 794#define CRL_APB_SDIO0_REF_CTRL_OFFSET 0XFF5E006C 795#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 796#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070 797#undef CRL_APB_UART0_REF_CTRL_OFFSET 798#define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074 799#undef CRL_APB_UART1_REF_CTRL_OFFSET 800#define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078 801#undef CRL_APB_I2C0_REF_CTRL_OFFSET 802#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120 803#undef CRL_APB_I2C1_REF_CTRL_OFFSET 804#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124 805#undef CRL_APB_SPI0_REF_CTRL_OFFSET 806#define CRL_APB_SPI0_REF_CTRL_OFFSET 0XFF5E007C 807#undef CRL_APB_SPI1_REF_CTRL_OFFSET 808#define CRL_APB_SPI1_REF_CTRL_OFFSET 0XFF5E0080 809#undef CRL_APB_CAN0_REF_CTRL_OFFSET 810#define CRL_APB_CAN0_REF_CTRL_OFFSET 0XFF5E0084 811#undef CRL_APB_CAN1_REF_CTRL_OFFSET 812#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088 813#undef CRL_APB_CPU_R5_CTRL_OFFSET 814#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090 815#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 816#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C 817#undef CRL_APB_CSU_PLL_CTRL_OFFSET 818#define CRL_APB_CSU_PLL_CTRL_OFFSET 0XFF5E00A0 819#undef CRL_APB_PCAP_CTRL_OFFSET 820#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4 821#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 822#define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8 823#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 824#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC 825#undef CRL_APB_DBG_LPD_CTRL_OFFSET 826#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0 827#undef CRL_APB_NAND_REF_CTRL_OFFSET 828#define CRL_APB_NAND_REF_CTRL_OFFSET 0XFF5E00B4 829#undef CRL_APB_ADMA_REF_CTRL_OFFSET 830#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 831#undef CRL_APB_PL0_REF_CTRL_OFFSET 832#define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 833#undef CRL_APB_PL1_REF_CTRL_OFFSET 834#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 835#undef CRL_APB_PL2_REF_CTRL_OFFSET 836#define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8 837#undef CRL_APB_PL3_REF_CTRL_OFFSET 838#define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC 839#undef CRL_APB_AMS_REF_CTRL_OFFSET 840#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 841#undef CRL_APB_DLL_REF_CTRL_OFFSET 842#define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104 843#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 844#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128 845#undef CRF_APB_SATA_REF_CTRL_OFFSET 846#define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0 847#undef CRF_APB_PCIE_REF_CTRL_OFFSET 848#define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4 849#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 850#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070 851#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 852#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074 853#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 854#define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C 855#undef CRF_APB_ACPU_CTRL_OFFSET 856#define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 857#undef CRF_APB_DBG_TRACE_CTRL_OFFSET 858#define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064 859#undef CRF_APB_DBG_FPD_CTRL_OFFSET 860#define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 861#undef CRF_APB_DDR_CTRL_OFFSET 862#define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080 863#undef CRF_APB_GPU_REF_CTRL_OFFSET 864#define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084 865#undef CRF_APB_GDMA_REF_CTRL_OFFSET 866#define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8 867#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 868#define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC 869#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 870#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0 871#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 872#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4 873#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET 874#define CRF_APB_GTGREF0_REF_CTRL_OFFSET 0XFD1A00C8 875#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 876#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8 877#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 878#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380 879#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 880#define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100 881#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 882#define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300 883#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 884#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 885 886/*Clock active for the RX channel*/ 887#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 888#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 889#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 890#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 891#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26 892#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 0x04000000U 893 894/*Clock active signal. Switch to 0 to disable the clock*/ 895#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 896#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 897#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 898#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 0x00002500 899#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25 900#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 0x02000000U 901 902/*6 bit divider*/ 903#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 904#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 905#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 906#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 907#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16 908#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 909 910/*6 bit divider*/ 911#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 912#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 913#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 914#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 915#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8 916#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 917 918/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 919 clock. This is not usually an issue, but designers must be aware.)*/ 920#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 921#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 922#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 923#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 0x00002500 924#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0 925#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 0x00000007U 926 927/*Clock active for the RX channel*/ 928#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 929#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 930#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 931#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 932#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26 933#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 0x04000000U 934 935/*Clock active signal. Switch to 0 to disable the clock*/ 936#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 937#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 938#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 939#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 0x00002500 940#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25 941#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 0x02000000U 942 943/*6 bit divider*/ 944#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 945#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 946#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 947#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 948#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16 949#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 950 951/*6 bit divider*/ 952#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 953#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 954#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 955#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 956#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8 957#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 958 959/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 960 clock. This is not usually an issue, but designers must be aware.)*/ 961#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 962#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 963#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 964#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 0x00002500 965#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0 966#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 0x00000007U 967 968/*Clock active for the RX channel*/ 969#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 970#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 971#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 972#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 973#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26 974#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 0x04000000U 975 976/*Clock active signal. Switch to 0 to disable the clock*/ 977#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 978#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 979#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 980#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 0x00002500 981#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25 982#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 0x02000000U 983 984/*6 bit divider*/ 985#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 986#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 987#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 988#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 989#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16 990#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 0x003F0000U 991 992/*6 bit divider*/ 993#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 994#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 995#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 996#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 997#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8 998#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 0x00003F00U 999 1000/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1001 clock. This is not usually an issue, but designers must be aware.)*/ 1002#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 1003#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 1004#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 1005#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 0x00002500 1006#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0 1007#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 0x00000007U 1008 1009/*Clock active for the RX channel*/ 1010#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 1011#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 1012#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 1013#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 1014#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 1015#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U 1016 1017/*Clock active signal. Switch to 0 to disable the clock*/ 1018#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 1019#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 1020#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 1021#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 1022#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 1023#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U 1024 1025/*6 bit divider*/ 1026#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 1027#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 1028#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 1029#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 1030#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 1031#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1032 1033/*6 bit divider*/ 1034#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 1035#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 1036#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 1037#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 1038#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 1039#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1040 1041/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1042 clock. This is not usually an issue, but designers must be aware.)*/ 1043#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 1044#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 1045#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 1046#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 1047#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 1048#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U 1049 1050/*6 bit divider*/ 1051#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 1052#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 1053#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 1054#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 1055#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 1056#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1057 1058/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1059 clock. This is not usually an issue, but designers must be aware.)*/ 1060#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 1061#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 1062#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 1063#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 1064#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 1065#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U 1066 1067/*6 bit divider*/ 1068#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 1069#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 1070#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 1071#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 1072#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 1073#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1074 1075/*Clock active signal. Switch to 0 to disable the clock*/ 1076#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 1077#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 1078#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 1079#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 1080#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 1081#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U 1082 1083/*Clock active signal. Switch to 0 to disable the clock*/ 1084#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 1085#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 1086#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 1087#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 1088#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 1089#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U 1090 1091/*6 bit divider*/ 1092#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 1093#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 1094#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 1095#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1096#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 1097#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1098 1099/*6 bit divider*/ 1100#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 1101#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 1102#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 1103#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1104#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 1105#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1106 1107/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1108 clock. This is not usually an issue, but designers must be aware.)*/ 1109#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 1110#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 1111#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 1112#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1113#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 1114#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U 1115 1116/*Clock active signal. Switch to 0 to disable the clock*/ 1117#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 1118#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 1119#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 1120#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 1121#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 25 1122#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 0x02000000U 1123 1124/*6 bit divider*/ 1125#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 1126#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 1127#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 1128#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1129#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 16 1130#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1131 1132/*6 bit divider*/ 1133#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 1134#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 1135#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 1136#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1137#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 8 1138#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1139 1140/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1141 clock. This is not usually an issue, but designers must be aware.)*/ 1142#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 1143#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 1144#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 1145#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1146#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 0 1147#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U 1148 1149/*Clock active signal. Switch to 0 to disable the clock*/ 1150#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 1151#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 1152#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 1153#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 1154#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 1155#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U 1156 1157/*6 bit divider*/ 1158#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 1159#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 1160#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 1161#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1162#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 1163#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1164 1165/*6 bit divider*/ 1166#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 1167#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 1168#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 1169#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1170#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 1171#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1172 1173/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1174 clock. This is not usually an issue, but designers must be aware.)*/ 1175#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 1176#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 1177#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 1178#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1179#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 1180#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U 1181 1182/*Clock active signal. Switch to 0 to disable the clock*/ 1183#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 1184#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 1185#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 1186#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 1187#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 1188#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U 1189 1190/*6 bit divider*/ 1191#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 1192#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 1193#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 1194#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 1195#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 1196#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1197 1198/*6 bit divider*/ 1199#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 1200#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 1201#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 1202#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 1203#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 1204#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1205 1206/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1207 clock. This is not usually an issue, but designers must be aware.)*/ 1208#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 1209#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 1210#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 1211#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 1212#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 1213#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U 1214 1215/*Clock active signal. Switch to 0 to disable the clock*/ 1216#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 1217#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 1218#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 1219#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 0x01000F00 1220#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24 1221#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 0x01000000U 1222 1223/*6 bit divider*/ 1224#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 1225#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 1226#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 1227#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 1228#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16 1229#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1230 1231/*6 bit divider*/ 1232#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 1233#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 1234#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 1235#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 1236#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8 1237#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1238 1239/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1240 clock. This is not usually an issue, but designers must be aware.)*/ 1241#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 1242#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 1243#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 1244#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 1245#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0 1246#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 0x00000007U 1247 1248/*Clock active signal. Switch to 0 to disable the clock*/ 1249#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 1250#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 1251#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 1252#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 1253#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 1254#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U 1255 1256/*6 bit divider*/ 1257#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 1258#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 1259#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 1260#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 1261#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 1262#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1263 1264/*6 bit divider*/ 1265#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 1266#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 1267#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 1268#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 1269#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 1270#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1271 1272/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1273 clock. This is not usually an issue, but designers must be aware.)*/ 1274#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 1275#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 1276#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 1277#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 1278#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 1279#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U 1280 1281/*Clock active signal. Switch to 0 to disable the clock*/ 1282#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 1283#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 1284#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 1285#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 1286#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 1287#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U 1288 1289/*6 bit divider*/ 1290#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 1291#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 1292#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 1293#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1294#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 1295#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1296 1297/*6 bit divider*/ 1298#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 1299#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 1300#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 1301#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1302#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 1303#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1304 1305/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1306 clock. This is not usually an issue, but designers must be aware.)*/ 1307#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 1308#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 1309#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 1310#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1311#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 1312#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U 1313 1314/*Clock active signal. Switch to 0 to disable the clock*/ 1315#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 1316#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 1317#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 1318#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 1319#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 1320#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U 1321 1322/*6 bit divider*/ 1323#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 1324#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 1325#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 1326#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1327#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 1328#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1329 1330/*6 bit divider*/ 1331#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 1332#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 1333#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 1334#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1335#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 1336#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1337 1338/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1339 clock. This is not usually an issue, but designers must be aware.)*/ 1340#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 1341#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 1342#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 1343#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1344#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 1345#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U 1346 1347/*Clock active signal. Switch to 0 to disable the clock*/ 1348#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 1349#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 1350#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 1351#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 1352#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 1353#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U 1354 1355/*6 bit divider*/ 1356#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 1357#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 1358#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 1359#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 1360#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 1361#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1362 1363/*6 bit divider*/ 1364#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 1365#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 1366#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 1367#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 1368#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 1369#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1370 1371/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1372 clock. This is not usually an issue, but designers must be aware.)*/ 1373#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 1374#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 1375#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 1376#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 1377#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 1378#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U 1379 1380/*Clock active signal. Switch to 0 to disable the clock*/ 1381#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 1382#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 1383#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 1384#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 1385#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 1386#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U 1387 1388/*6 bit divider*/ 1389#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 1390#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 1391#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 1392#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 1393#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 1394#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1395 1396/*6 bit divider*/ 1397#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 1398#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 1399#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 1400#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 1401#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 1402#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1403 1404/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1405 clock. This is not usually an issue, but designers must be aware.)*/ 1406#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 1407#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 1408#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 1409#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 1410#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 1411#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U 1412 1413/*Clock active signal. Switch to 0 to disable the clock*/ 1414#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 1415#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 1416#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 1417#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 0x01001800 1418#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24 1419#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 0x01000000U 1420 1421/*6 bit divider*/ 1422#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 1423#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 1424#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 1425#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1426#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16 1427#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1428 1429/*6 bit divider*/ 1430#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 1431#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 1432#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 1433#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1434#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8 1435#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1436 1437/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1438 clock. This is not usually an issue, but designers must be aware.)*/ 1439#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 1440#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 1441#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 1442#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1443#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0 1444#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 0x00000007U 1445 1446/*Clock active signal. Switch to 0 to disable the clock*/ 1447#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 1448#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 1449#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 1450#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 0x01001800 1451#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24 1452#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 0x01000000U 1453 1454/*6 bit divider*/ 1455#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 1456#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 1457#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 1458#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1459#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16 1460#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1461 1462/*6 bit divider*/ 1463#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 1464#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 1465#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 1466#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1467#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8 1468#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1469 1470/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1471 clock. This is not usually an issue, but designers must be aware.)*/ 1472#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 1473#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 1474#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 1475#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1476#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0 1477#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 0x00000007U 1478 1479/*Clock active signal. Switch to 0 to disable the clock*/ 1480#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 1481#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 1482#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 1483#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 0x01001800 1484#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24 1485#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 0x01000000U 1486 1487/*6 bit divider*/ 1488#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 1489#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 1490#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 1491#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1492#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16 1493#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1494 1495/*6 bit divider*/ 1496#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 1497#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 1498#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 1499#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1500#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8 1501#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1502 1503/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1504 clock. This is not usually an issue, but designers must be aware.)*/ 1505#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 1506#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 1507#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 1508#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1509#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0 1510#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 0x00000007U 1511 1512/*Clock active signal. Switch to 0 to disable the clock*/ 1513#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 1514#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 1515#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 1516#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 1517#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 1518#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U 1519 1520/*6 bit divider*/ 1521#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 1522#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 1523#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 1524#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1525#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 1526#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1527 1528/*6 bit divider*/ 1529#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 1530#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 1531#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 1532#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1533#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 1534#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1535 1536/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1537 clock. This is not usually an issue, but designers must be aware.)*/ 1538#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 1539#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 1540#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 1541#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1542#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 1543#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U 1544 1545/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou 1546 d lead to system hang*/ 1547#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 1548#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 1549#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 1550#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 1551#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 1552#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U 1553 1554/*6 bit divider*/ 1555#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 1556#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 1557#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 1558#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 1559#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 1560#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U 1561 1562/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1563 clock. This is not usually an issue, but designers must be aware.)*/ 1564#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 1565#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 1566#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 1567#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 1568#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 1569#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U 1570 1571/*Clock active signal. Switch to 0 to disable the clock*/ 1572#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 1573#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 1574#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 1575#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 1576#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 1577#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U 1578 1579/*6 bit divider*/ 1580#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 1581#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 1582#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 1583#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 1584#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 1585#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U 1586 1587/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1588 clock. This is not usually an issue, but designers must be aware.)*/ 1589#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 1590#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 1591#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 1592#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 1593#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 1594#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U 1595 1596/*Clock active signal. Switch to 0 to disable the clock*/ 1597#undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 1598#undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 1599#undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 1600#define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 0x01001500 1601#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 24 1602#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 0x01000000U 1603 1604/*6 bit divider*/ 1605#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 1606#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 1607#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 1608#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 0x01001500 1609#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 8 1610#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 0x00003F00U 1611 1612/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1613 clock. This is not usually an issue, but designers must be aware.)*/ 1614#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 1615#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 1616#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 1617#define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 0x01001500 1618#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 0 1619#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 0x00000007U 1620 1621/*Clock active signal. Switch to 0 to disable the clock*/ 1622#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 1623#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 1624#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 1625#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 1626#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 1627#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U 1628 1629/*6 bit divider*/ 1630#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 1631#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 1632#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 1633#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 1634#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 1635#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U 1636 1637/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1638 clock. This is not usually an issue, but designers must be aware.)*/ 1639#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 1640#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 1641#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 1642#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 1643#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 1644#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U 1645 1646/*Clock active signal. Switch to 0 to disable the clock*/ 1647#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 1648#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 1649#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 1650#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 1651#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 1652#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U 1653 1654/*6 bit divider*/ 1655#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 1656#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 1657#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 1658#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 1659#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 1660#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U 1661 1662/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1663 clock. This is not usually an issue, but designers must be aware.)*/ 1664#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 1665#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 1666#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 1667#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 1668#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 1669#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U 1670 1671/*Clock active signal. Switch to 0 to disable the clock*/ 1672#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 1673#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 1674#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 1675#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 1676#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 1677#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U 1678 1679/*6 bit divider*/ 1680#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 1681#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 1682#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 1683#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 1684#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 1685#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U 1686 1687/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1688 clock. This is not usually an issue, but designers must be aware.)*/ 1689#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 1690#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 1691#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 1692#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 1693#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 1694#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U 1695 1696/*Clock active signal. Switch to 0 to disable the clock*/ 1697#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 1698#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 1699#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 1700#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 1701#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 1702#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U 1703 1704/*6 bit divider*/ 1705#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 1706#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 1707#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 1708#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 1709#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 1710#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U 1711 1712/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1713 clock. This is not usually an issue, but designers must be aware.)*/ 1714#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 1715#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 1716#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 1717#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 1718#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 1719#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U 1720 1721/*Clock active signal. Switch to 0 to disable the clock*/ 1722#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 1723#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 1724#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK 1725#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 0x00052000 1726#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24 1727#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK 0x01000000U 1728 1729/*6 bit divider*/ 1730#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 1731#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 1732#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 1733#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1734#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16 1735#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1736 1737/*6 bit divider*/ 1738#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 1739#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 1740#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 1741#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1742#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8 1743#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1744 1745/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1746 clock. This is not usually an issue, but designers must be aware.)*/ 1747#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 1748#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 1749#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 1750#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1751#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0 1752#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 0x00000007U 1753 1754/*Clock active signal. Switch to 0 to disable the clock*/ 1755#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 1756#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 1757#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 1758#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 1759#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 1760#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U 1761 1762/*6 bit divider*/ 1763#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 1764#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 1765#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 1766#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 1767#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 1768#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1769 1770/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1771 clock. This is not usually an issue, but designers must be aware.)*/ 1772#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 1773#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 1774#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 1775#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 1776#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 1777#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U 1778 1779/*Clock active signal. Switch to 0 to disable the clock*/ 1780#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 1781#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 1782#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 1783#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 1784#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 1785#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U 1786 1787/*6 bit divider*/ 1788#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 1789#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 1790#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 1791#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1792#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 1793#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1794 1795/*6 bit divider*/ 1796#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 1797#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 1798#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 1799#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1800#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 1801#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1802 1803/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1804 clock. This is not usually an issue, but designers must be aware.)*/ 1805#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 1806#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 1807#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 1808#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1809#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 1810#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U 1811 1812/*Clock active signal. Switch to 0 to disable the clock*/ 1813#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 1814#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 1815#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK 1816#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 1817#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 1818#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U 1819 1820/*6 bit divider*/ 1821#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 1822#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 1823#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 1824#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1825#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 1826#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1827 1828/*6 bit divider*/ 1829#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 1830#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 1831#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 1832#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1833#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 1834#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1835 1836/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1837 clock. This is not usually an issue, but designers must be aware.)*/ 1838#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 1839#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 1840#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 1841#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1842#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 1843#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U 1844 1845/*Clock active signal. Switch to 0 to disable the clock*/ 1846#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 1847#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 1848#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK 1849#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000 1850#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 1851#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U 1852 1853/*6 bit divider*/ 1854#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 1855#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 1856#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 1857#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1858#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 1859#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1860 1861/*6 bit divider*/ 1862#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 1863#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 1864#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 1865#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1866#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 1867#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1868 1869/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1870 clock. This is not usually an issue, but designers must be aware.)*/ 1871#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 1872#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 1873#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 1874#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1875#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 1876#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U 1877 1878/*Clock active signal. Switch to 0 to disable the clock*/ 1879#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 1880#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 1881#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK 1882#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000 1883#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 1884#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U 1885 1886/*6 bit divider*/ 1887#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 1888#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 1889#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 1890#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 1891#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 1892#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1893 1894/*6 bit divider*/ 1895#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 1896#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 1897#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 1898#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 1899#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 1900#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1901 1902/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1903 clock. This is not usually an issue, but designers must be aware.)*/ 1904#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 1905#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 1906#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 1907#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000 1908#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 1909#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U 1910 1911/*6 bit divider*/ 1912#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 1913#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 1914#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 1915#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 1916#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 1917#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U 1918 1919/*6 bit divider*/ 1920#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 1921#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 1922#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 1923#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 1924#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 1925#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1926 1927/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 1928 clock. This is not usually an issue, but designers must be aware.)*/ 1929#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 1930#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 1931#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 1932#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 1933#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 1934#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U 1935 1936/*Clock active signal. Switch to 0 to disable the clock*/ 1937#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 1938#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 1939#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 1940#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 1941#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 1942#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U 1943 1944/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 1945 is not usually an issue, but designers must be aware.)*/ 1946#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 1947#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 1948#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 1949#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 1950#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 1951#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U 1952 1953/*6 bit divider*/ 1954#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 1955#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 1956#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 1957#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 1958#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 1959#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U 1960 1961/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 1962 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 1963#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 1964#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 1965#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 1966#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 1967#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 1968#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U 1969 1970/*Clock active signal. Switch to 0 to disable the clock*/ 1971#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 1972#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 1973#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 1974#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 1975#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 1976#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U 1977 1978/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 1979 he new clock. This is not usually an issue, but designers must be aware.)*/ 1980#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 1981#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 1982#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 1983#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 1984#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 1985#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U 1986 1987/*Clock active signal. Switch to 0 to disable the clock*/ 1988#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 1989#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 1990#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 1991#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 1992#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 1993#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U 1994 1995/*6 bit divider*/ 1996#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 1997#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 1998#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 1999#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 2000#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
2001#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2002 2003/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc 2004 es of the new clock. This is not usually an issue, but designers must be aware.)*/ 2005#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 2006#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 2007#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 2008#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 2009#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 2010#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U 2011 2012/*Clock active signal. Switch to 0 to disable the clock*/ 2013#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 2014#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 2015#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 2016#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 2017#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 2018#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U 2019 2020/*6 bit divider*/ 2021#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 2022#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 2023#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 2024#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 2025#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 2026#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2027 2028/*6 bit divider*/ 2029#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 2030#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 2031#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 2032#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 2033#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 2034#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U 2035 2036/*6 bit divider*/ 2037#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 2038#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 2039#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 2040#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 2041#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 2042#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2043 2044/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 2045 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 2046#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 2047#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 2048#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 2049#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 2050#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 2051#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U 2052 2053/*Clock active signal. Switch to 0 to disable the clock*/ 2054#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 2055#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 2056#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 2057#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 2058#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 2059#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U 2060 2061/*6 bit divider*/ 2062#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 2063#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 2064#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 2065#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 2066#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 2067#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U 2068 2069/*6 bit divider*/ 2070#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 2071#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 2072#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 2073#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 2074#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 2075#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2076 2077/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 2078 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ 2079#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 2080#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 2081#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 2082#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 2083#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 2084#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U 2085 2086/*Clock active signal. Switch to 0 to disable the clock*/ 2087#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 2088#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 2089#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 2090#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 2091#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 2092#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U 2093 2094/*6 bit divider*/ 2095#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 2096#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 2097#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 2098#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 2099#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 2100#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U 2101 2102/*6 bit divider*/ 2103#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 2104#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 2105#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 2106#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 2107#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 2108#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2109 2110/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t 2111 e new clock. This is not usually an issue, but designers must be aware.)*/ 2112#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 2113#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 2114#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 2115#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 2116#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 2117#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U 2118 2119/*Clock active signal. Switch to 0 to disable the clock*/ 2120#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 2121#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 2122#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 2123#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 2124#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 2125#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U 2126 2127/*6 bit divider*/ 2128#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 2129#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 2130#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 2131#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 2132#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 2133#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U 2134 2135/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 2136 lock. This is not usually an issue, but designers must be aware.)*/ 2137#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 2138#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 2139#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 2140#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 2141#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 2142#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U 2143 2144/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/ 2145#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 2146#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 2147#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 2148#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 2149#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 2150#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U 2151 2152/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc 2153 to the entire APU*/ 2154#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 2155#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 2156#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 2157#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 2158#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 2159#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U 2160 2161/*6 bit divider*/ 2162#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 2163#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 2164#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 2165#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500 2166#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 2167#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U 2168 2169/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2170 he new clock. This is not usually an issue, but designers must be aware.)*/ 2171#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 2172#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 2173#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 2174#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500 2175#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 2176#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U 2177 2178/*Clock active signal. Switch to 0 to disable the clock*/ 2179#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 2180#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 2181#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 2182#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500 2183#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 2184#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U 2185 2186/*6 bit divider*/ 2187#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 2188#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 2189#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 2190#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 2191#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 2192#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U 2193 2194/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2195 he new clock. This is not usually an issue, but designers must be aware.)*/ 2196#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 2197#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 2198#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 2199#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 2200#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 2201#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U 2202 2203/*Clock active signal. Switch to 0 to disable the clock*/ 2204#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 2205#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 2206#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 2207#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 2208#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 2209#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U 2210 2211/*6 bit divider*/ 2212#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 2213#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 2214#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 2215#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 2216#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 2217#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U 2218 2219/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 2220 s not usually an issue, but designers must be aware.)*/ 2221#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 2222#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 2223#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 2224#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 2225#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 2226#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U 2227 2228/*6 bit divider*/ 2229#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 2230#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 2231#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 2232#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 2233#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 2234#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2235 2236/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2237 he new clock. This is not usually an issue, but designers must be aware.)*/ 2238#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 2239#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 2240#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 2241#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 2242#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 2243#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U 2244 2245/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/ 2246#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 2247#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 2248#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 2249#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 2250#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 2251#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U 2252 2253/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ 2254#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 2255#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 2256#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 2257#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 2258#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 2259#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U 2260 2261/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ 2262#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 2263#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 2264#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 2265#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 2266#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 2267#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U 2268 2269/*6 bit divider*/ 2270#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 2271#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 2272#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 2273#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 2274#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 2275#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2276 2277/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 2278 lock. This is not usually an issue, but designers must be aware.)*/ 2279#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 2280#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 2281#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 2282#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 2283#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 2284#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U 2285 2286/*Clock active signal. Switch to 0 to disable the clock*/ 2287#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 2288#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 2289#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 2290#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 2291#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 2292#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U 2293 2294/*6 bit divider*/ 2295#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 2296#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 2297#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 2298#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 2299#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 2300#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2301 2302/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 2303 lock. This is not usually an issue, but designers must be aware.)*/ 2304#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 2305#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 2306#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 2307#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 2308#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 2309#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U 2310 2311/*Clock active signal. Switch to 0 to disable the clock*/ 2312#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 2313#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 2314#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 2315#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 2316#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 2317#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U 2318 2319/*6 bit divider*/ 2320#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 2321#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 2322#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 2323#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 2324#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 2325#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U 2326 2327/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 2328 lock. This is not usually an issue, but designers must be aware.)*/ 2329#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 2330#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 2331#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 2332#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 2333#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 2334#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U 2335 2336/*Clock active signal. Switch to 0 to disable the clock*/ 2337#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 2338#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 2339#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 2340#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 2341#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 2342#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U 2343 2344/*6 bit divider*/ 2345#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 2346#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 2347#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 2348#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 2349#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 2350#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U 2351 2352/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2353 he new clock. This is not usually an issue, but designers must be aware.)*/ 2354#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 2355#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 2356#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 2357#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 2358#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 2359#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U 2360 2361/*Clock active signal. Switch to 0 to disable the clock*/ 2362#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 2363#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 2364#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 2365#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 2366#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 2367#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U 2368 2369/*6 bit divider*/ 2370#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 2371#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 2372#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 2373#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 0x00000800 2374#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8 2375#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 0x00003F00U 2376 2377/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2378 he new clock. This is not usually an issue, but designers must be aware.)*/ 2379#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 2380#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 2381#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 2382#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 0x00000800 2383#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0 2384#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 0x00000007U 2385 2386/*Clock active signal. Switch to 0 to disable the clock*/ 2387#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 2388#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 2389#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 2390#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 0x00000800 2391#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24 2392#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 0x01000000U 2393 2394/*6 bit divider*/ 2395#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 2396#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 2397#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 2398#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 2399#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 2400#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U 2401 2402/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 2403 he new clock. This is not usually an issue, but designers must be aware.)*/ 2404#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 2405#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 2406#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 2407#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 2408#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 2409#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U 2410 2411/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' 2412 0" = Select the R5 clock for the APB interface of TTC0*/ 2413#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 2414#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 2415#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 2416#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 2417#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 2418#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U 2419 2420/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' 2421 0" = Select the R5 clock for the APB interface of TTC1*/ 2422#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 2423#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2424#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 2425#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 2426#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 2427#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU 2428 2429/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' 2430 0" = Select the R5 clock for the APB interface of TTC2*/ 2431#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 2432#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 2433#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 2434#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 2435#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 2436#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U 2437 2438/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' 2439 0" = Select the R5 clock for the APB interface of TTC3*/ 2440#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 2441#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 2442#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 2443#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 2444#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 2445#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U 2446 2447/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/ 2448#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 2449#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 2450#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 2451#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 2452#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 2453#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U 2454 2455/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 2456 ia MIO*/ 2457#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 2458#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 2459#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 2460#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 2461#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 2462#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U 2463 2464/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/ 2465#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 2466#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 2467#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 2468#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 2469#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 2470#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U 2471#undef CRF_APB_RST_DDR_SS_OFFSET 2472#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 2473#undef DDRC_MSTR_OFFSET 2474#define DDRC_MSTR_OFFSET 0XFD070000 2475#undef DDRC_MRCTRL0_OFFSET 2476#define DDRC_MRCTRL0_OFFSET 0XFD070010 2477#undef DDRC_DERATEEN_OFFSET 2478#define DDRC_DERATEEN_OFFSET 0XFD070020 2479#undef DDRC_DERATEINT_OFFSET 2480#define DDRC_DERATEINT_OFFSET 0XFD070024 2481#undef DDRC_PWRCTL_OFFSET 2482#define DDRC_PWRCTL_OFFSET 0XFD070030 2483#undef DDRC_PWRTMG_OFFSET 2484#define DDRC_PWRTMG_OFFSET 0XFD070034 2485#undef DDRC_RFSHCTL0_OFFSET 2486#define DDRC_RFSHCTL0_OFFSET 0XFD070050 2487#undef DDRC_RFSHCTL3_OFFSET 2488#define DDRC_RFSHCTL3_OFFSET 0XFD070060 2489#undef DDRC_RFSHTMG_OFFSET 2490#define DDRC_RFSHTMG_OFFSET 0XFD070064 2491#undef DDRC_ECCCFG0_OFFSET 2492#define DDRC_ECCCFG0_OFFSET 0XFD070070 2493#undef DDRC_ECCCFG1_OFFSET 2494#define DDRC_ECCCFG1_OFFSET 0XFD070074 2495#undef DDRC_CRCPARCTL1_OFFSET 2496#define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4 2497#undef DDRC_CRCPARCTL2_OFFSET 2498#define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8 2499#undef DDRC_INIT0_OFFSET 2500#define DDRC_INIT0_OFFSET 0XFD0700D0 2501#undef DDRC_INIT1_OFFSET 2502#define DDRC_INIT1_OFFSET 0XFD0700D4 2503#undef DDRC_INIT2_OFFSET 2504#define DDRC_INIT2_OFFSET 0XFD0700D8 2505#undef DDRC_INIT3_OFFSET 2506#define DDRC_INIT3_OFFSET 0XFD0700DC 2507#undef DDRC_INIT4_OFFSET 2508#define DDRC_INIT4_OFFSET 0XFD0700E0 2509#undef DDRC_INIT5_OFFSET 2510#define DDRC_INIT5_OFFSET 0XFD0700E4 2511#undef DDRC_INIT6_OFFSET 2512#define DDRC_INIT6_OFFSET 0XFD0700E8 2513#undef DDRC_INIT7_OFFSET 2514#define DDRC_INIT7_OFFSET 0XFD0700EC 2515#undef DDRC_DIMMCTL_OFFSET 2516#define DDRC_DIMMCTL_OFFSET 0XFD0700F0 2517#undef DDRC_RANKCTL_OFFSET 2518#define DDRC_RANKCTL_OFFSET 0XFD0700F4 2519#undef DDRC_DRAMTMG0_OFFSET 2520#define DDRC_DRAMTMG0_OFFSET 0XFD070100 2521#undef DDRC_DRAMTMG1_OFFSET 2522#define DDRC_DRAMTMG1_OFFSET 0XFD070104 2523#undef DDRC_DRAMTMG2_OFFSET 2524#define DDRC_DRAMTMG2_OFFSET 0XFD070108 2525#undef DDRC_DRAMTMG3_OFFSET 2526#define DDRC_DRAMTMG3_OFFSET 0XFD07010C 2527#undef DDRC_DRAMTMG4_OFFSET 2528#define DDRC_DRAMTMG4_OFFSET 0XFD070110 2529#undef DDRC_DRAMTMG5_OFFSET 2530#define DDRC_DRAMTMG5_OFFSET 0XFD070114 2531#undef DDRC_DRAMTMG6_OFFSET 2532#define DDRC_DRAMTMG6_OFFSET 0XFD070118 2533#undef DDRC_DRAMTMG7_OFFSET 2534#define DDRC_DRAMTMG7_OFFSET 0XFD07011C 2535#undef DDRC_DRAMTMG8_OFFSET 2536#define DDRC_DRAMTMG8_OFFSET 0XFD070120 2537#undef DDRC_DRAMTMG9_OFFSET 2538#define DDRC_DRAMTMG9_OFFSET 0XFD070124 2539#undef DDRC_DRAMTMG11_OFFSET 2540#define DDRC_DRAMTMG11_OFFSET 0XFD07012C 2541#undef DDRC_DRAMTMG12_OFFSET 2542#define DDRC_DRAMTMG12_OFFSET 0XFD070130 2543#undef DDRC_ZQCTL0_OFFSET 2544#define DDRC_ZQCTL0_OFFSET 0XFD070180 2545#undef DDRC_ZQCTL1_OFFSET 2546#define DDRC_ZQCTL1_OFFSET 0XFD070184 2547#undef DDRC_DFITMG0_OFFSET 2548#define DDRC_DFITMG0_OFFSET 0XFD070190 2549#undef DDRC_DFITMG1_OFFSET 2550#define DDRC_DFITMG1_OFFSET 0XFD070194 2551#undef DDRC_DFILPCFG0_OFFSET 2552#define DDRC_DFILPCFG0_OFFSET 0XFD070198 2553#undef DDRC_DFILPCFG1_OFFSET 2554#define DDRC_DFILPCFG1_OFFSET 0XFD07019C 2555#undef DDRC_DFIUPD1_OFFSET 2556#define DDRC_DFIUPD1_OFFSET 0XFD0701A4 2557#undef DDRC_DFIMISC_OFFSET 2558#define DDRC_DFIMISC_OFFSET 0XFD0701B0 2559#undef DDRC_DFITMG2_OFFSET 2560#define DDRC_DFITMG2_OFFSET 0XFD0701B4 2561#undef DDRC_DBICTL_OFFSET 2562#define DDRC_DBICTL_OFFSET 0XFD0701C0 2563#undef DDRC_ADDRMAP0_OFFSET 2564#define DDRC_ADDRMAP0_OFFSET 0XFD070200 2565#undef DDRC_ADDRMAP1_OFFSET 2566#define DDRC_ADDRMAP1_OFFSET 0XFD070204 2567#undef DDRC_ADDRMAP2_OFFSET 2568#define DDRC_ADDRMAP2_OFFSET 0XFD070208 2569#undef DDRC_ADDRMAP3_OFFSET 2570#define DDRC_ADDRMAP3_OFFSET 0XFD07020C 2571#undef DDRC_ADDRMAP4_OFFSET 2572#define DDRC_ADDRMAP4_OFFSET 0XFD070210 2573#undef DDRC_ADDRMAP5_OFFSET 2574#define DDRC_ADDRMAP5_OFFSET 0XFD070214 2575#undef DDRC_ADDRMAP6_OFFSET 2576#define DDRC_ADDRMAP6_OFFSET 0XFD070218 2577#undef DDRC_ADDRMAP7_OFFSET 2578#define DDRC_ADDRMAP7_OFFSET 0XFD07021C 2579#undef DDRC_ADDRMAP8_OFFSET 2580#define DDRC_ADDRMAP8_OFFSET 0XFD070220 2581#undef DDRC_ADDRMAP9_OFFSET 2582#define DDRC_ADDRMAP9_OFFSET 0XFD070224 2583#undef DDRC_ADDRMAP10_OFFSET 2584#define DDRC_ADDRMAP10_OFFSET 0XFD070228 2585#undef DDRC_ADDRMAP11_OFFSET 2586#define DDRC_ADDRMAP11_OFFSET 0XFD07022C 2587#undef DDRC_ODTCFG_OFFSET 2588#define DDRC_ODTCFG_OFFSET 0XFD070240 2589#undef DDRC_ODTMAP_OFFSET 2590#define DDRC_ODTMAP_OFFSET 0XFD070244 2591#undef DDRC_SCHED_OFFSET 2592#define DDRC_SCHED_OFFSET 0XFD070250 2593#undef DDRC_PERFLPR1_OFFSET 2594#define DDRC_PERFLPR1_OFFSET 0XFD070264 2595#undef DDRC_PERFWR1_OFFSET 2596#define DDRC_PERFWR1_OFFSET 0XFD07026C 2597#undef DDRC_DQMAP5_OFFSET 2598#define DDRC_DQMAP5_OFFSET 0XFD070294 2599#undef DDRC_DBG0_OFFSET 2600#define DDRC_DBG0_OFFSET 0XFD070300 2601#undef DDRC_DBGCMD_OFFSET 2602#define DDRC_DBGCMD_OFFSET 0XFD07030C 2603#undef DDRC_SWCTL_OFFSET 2604#define DDRC_SWCTL_OFFSET 0XFD070320 2605#undef DDRC_PCCFG_OFFSET 2606#define DDRC_PCCFG_OFFSET 0XFD070400 2607#undef DDRC_PCFGR_0_OFFSET 2608#define DDRC_PCFGR_0_OFFSET 0XFD070404 2609#undef DDRC_PCFGW_0_OFFSET 2610#define DDRC_PCFGW_0_OFFSET 0XFD070408 2611#undef DDRC_PCTRL_0_OFFSET 2612#define DDRC_PCTRL_0_OFFSET 0XFD070490 2613#undef DDRC_PCFGQOS0_0_OFFSET 2614#define DDRC_PCFGQOS0_0_OFFSET 0XFD070494 2615#undef DDRC_PCFGQOS1_0_OFFSET 2616#define DDRC_PCFGQOS1_0_OFFSET 0XFD070498 2617#undef DDRC_PCFGR_1_OFFSET 2618#define DDRC_PCFGR_1_OFFSET 0XFD0704B4 2619#undef DDRC_PCFGW_1_OFFSET 2620#define DDRC_PCFGW_1_OFFSET 0XFD0704B8 2621#undef DDRC_PCTRL_1_OFFSET 2622#define DDRC_PCTRL_1_OFFSET 0XFD070540 2623#undef DDRC_PCFGQOS0_1_OFFSET 2624#define DDRC_PCFGQOS0_1_OFFSET 0XFD070544 2625#undef DDRC_PCFGQOS1_1_OFFSET 2626#define DDRC_PCFGQOS1_1_OFFSET 0XFD070548 2627#undef DDRC_PCFGR_2_OFFSET 2628#define DDRC_PCFGR_2_OFFSET 0XFD070564 2629#undef DDRC_PCFGW_2_OFFSET 2630#define DDRC_PCFGW_2_OFFSET 0XFD070568 2631#undef DDRC_PCTRL_2_OFFSET 2632#define DDRC_PCTRL_2_OFFSET 0XFD0705F0 2633#undef DDRC_PCFGQOS0_2_OFFSET 2634#define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4 2635#undef DDRC_PCFGQOS1_2_OFFSET 2636#define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8 2637#undef DDRC_PCFGR_3_OFFSET 2638#define DDRC_PCFGR_3_OFFSET 0XFD070614 2639#undef DDRC_PCFGW_3_OFFSET 2640#define DDRC_PCFGW_3_OFFSET 0XFD070618 2641#undef DDRC_PCTRL_3_OFFSET 2642#define DDRC_PCTRL_3_OFFSET 0XFD0706A0 2643#undef DDRC_PCFGQOS0_3_OFFSET 2644#define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4 2645#undef DDRC_PCFGQOS1_3_OFFSET 2646#define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8 2647#undef DDRC_PCFGWQOS0_3_OFFSET 2648#define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC 2649#undef DDRC_PCFGWQOS1_3_OFFSET 2650#define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0 2651#undef DDRC_PCFGR_4_OFFSET 2652#define DDRC_PCFGR_4_OFFSET 0XFD0706C4 2653#undef DDRC_PCFGW_4_OFFSET 2654#define DDRC_PCFGW_4_OFFSET 0XFD0706C8 2655#undef DDRC_PCTRL_4_OFFSET 2656#define DDRC_PCTRL_4_OFFSET 0XFD070750 2657#undef DDRC_PCFGQOS0_4_OFFSET 2658#define DDRC_PCFGQOS0_4_OFFSET 0XFD070754 2659#undef DDRC_PCFGQOS1_4_OFFSET 2660#define DDRC_PCFGQOS1_4_OFFSET 0XFD070758 2661#undef DDRC_PCFGWQOS0_4_OFFSET 2662#define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C 2663#undef DDRC_PCFGWQOS1_4_OFFSET 2664#define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760 2665#undef DDRC_PCFGR_5_OFFSET 2666#define DDRC_PCFGR_5_OFFSET 0XFD070774 2667#undef DDRC_PCFGW_5_OFFSET 2668#define DDRC_PCFGW_5_OFFSET 0XFD070778 2669#undef DDRC_PCTRL_5_OFFSET 2670#define DDRC_PCTRL_5_OFFSET 0XFD070800 2671#undef DDRC_PCFGQOS0_5_OFFSET 2672#define DDRC_PCFGQOS0_5_OFFSET 0XFD070804 2673#undef DDRC_PCFGQOS1_5_OFFSET 2674#define DDRC_PCFGQOS1_5_OFFSET 0XFD070808 2675#undef DDRC_PCFGWQOS0_5_OFFSET 2676#define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C 2677#undef DDRC_PCFGWQOS1_5_OFFSET 2678#define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810 2679#undef DDRC_SARBASE0_OFFSET 2680#define DDRC_SARBASE0_OFFSET 0XFD070F04 2681#undef DDRC_SARSIZE0_OFFSET 2682#define DDRC_SARSIZE0_OFFSET 0XFD070F08 2683#undef DDRC_SARBASE1_OFFSET 2684#define DDRC_SARBASE1_OFFSET 0XFD070F0C 2685#undef DDRC_SARSIZE1_OFFSET 2686#define DDRC_SARSIZE1_OFFSET 0XFD070F10 2687#undef DDRC_DFITMG0_SHADOW_OFFSET 2688#define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190 2689#undef CRF_APB_RST_DDR_SS_OFFSET 2690#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 2691#undef DDR_PHY_PGCR0_OFFSET 2692#define DDR_PHY_PGCR0_OFFSET 0XFD080010 2693#undef DDR_PHY_PGCR2_OFFSET 2694#define DDR_PHY_PGCR2_OFFSET 0XFD080018 2695#undef DDR_PHY_PGCR3_OFFSET 2696#define DDR_PHY_PGCR3_OFFSET 0XFD08001C 2697#undef DDR_PHY_PGCR5_OFFSET 2698#define DDR_PHY_PGCR5_OFFSET 0XFD080024 2699#undef DDR_PHY_PTR0_OFFSET 2700#define DDR_PHY_PTR0_OFFSET 0XFD080040 2701#undef DDR_PHY_PTR1_OFFSET 2702#define DDR_PHY_PTR1_OFFSET 0XFD080044 2703#undef DDR_PHY_DSGCR_OFFSET 2704#define DDR_PHY_DSGCR_OFFSET 0XFD080090 2705#undef DDR_PHY_DCR_OFFSET 2706#define DDR_PHY_DCR_OFFSET 0XFD080100 2707#undef DDR_PHY_DTPR0_OFFSET 2708#define DDR_PHY_DTPR0_OFFSET 0XFD080110 2709#undef DDR_PHY_DTPR1_OFFSET 2710#define DDR_PHY_DTPR1_OFFSET 0XFD080114 2711#undef DDR_PHY_DTPR2_OFFSET 2712#define DDR_PHY_DTPR2_OFFSET 0XFD080118 2713#undef DDR_PHY_DTPR3_OFFSET 2714#define DDR_PHY_DTPR3_OFFSET 0XFD08011C 2715#undef DDR_PHY_DTPR4_OFFSET 2716#define DDR_PHY_DTPR4_OFFSET 0XFD080120 2717#undef DDR_PHY_DTPR5_OFFSET 2718#define DDR_PHY_DTPR5_OFFSET 0XFD080124 2719#undef DDR_PHY_DTPR6_OFFSET 2720#define DDR_PHY_DTPR6_OFFSET 0XFD080128 2721#undef DDR_PHY_RDIMMGCR0_OFFSET 2722#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140 2723#undef DDR_PHY_RDIMMGCR1_OFFSET 2724#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144 2725#undef DDR_PHY_RDIMMCR0_OFFSET 2726#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150 2727#undef DDR_PHY_RDIMMCR1_OFFSET 2728#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154 2729#undef DDR_PHY_MR0_OFFSET 2730#define DDR_PHY_MR0_OFFSET 0XFD080180 2731#undef DDR_PHY_MR1_OFFSET 2732#define DDR_PHY_MR1_OFFSET 0XFD080184 2733#undef DDR_PHY_MR2_OFFSET 2734#define DDR_PHY_MR2_OFFSET 0XFD080188 2735#undef DDR_PHY_MR3_OFFSET 2736#define DDR_PHY_MR3_OFFSET 0XFD08018C 2737#undef DDR_PHY_MR4_OFFSET 2738#define DDR_PHY_MR4_OFFSET 0XFD080190 2739#undef DDR_PHY_MR5_OFFSET 2740#define DDR_PHY_MR5_OFFSET 0XFD080194 2741#undef DDR_PHY_MR6_OFFSET 2742#define DDR_PHY_MR6_OFFSET 0XFD080198 2743#undef DDR_PHY_MR11_OFFSET 2744#define DDR_PHY_MR11_OFFSET 0XFD0801AC 2745#undef DDR_PHY_MR12_OFFSET 2746#define DDR_PHY_MR12_OFFSET 0XFD0801B0 2747#undef DDR_PHY_MR13_OFFSET 2748#define DDR_PHY_MR13_OFFSET 0XFD0801B4 2749#undef DDR_PHY_MR14_OFFSET 2750#define DDR_PHY_MR14_OFFSET 0XFD0801B8 2751#undef DDR_PHY_MR22_OFFSET 2752#define DDR_PHY_MR22_OFFSET 0XFD0801D8 2753#undef DDR_PHY_DTCR0_OFFSET 2754#define DDR_PHY_DTCR0_OFFSET 0XFD080200 2755#undef DDR_PHY_DTCR1_OFFSET 2756#define DDR_PHY_DTCR1_OFFSET 0XFD080204 2757#undef DDR_PHY_CATR0_OFFSET 2758#define DDR_PHY_CATR0_OFFSET 0XFD080240 2759#undef DDR_PHY_RIOCR5_OFFSET 2760#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4 2761#undef DDR_PHY_ACIOCR0_OFFSET 2762#define DDR_PHY_ACIOCR0_OFFSET 0XFD080500 2763#undef DDR_PHY_ACIOCR2_OFFSET 2764#define DDR_PHY_ACIOCR2_OFFSET 0XFD080508 2765#undef DDR_PHY_ACIOCR3_OFFSET 2766#define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C 2767#undef DDR_PHY_ACIOCR4_OFFSET 2768#define DDR_PHY_ACIOCR4_OFFSET 0XFD080510 2769#undef DDR_PHY_IOVCR0_OFFSET 2770#define DDR_PHY_IOVCR0_OFFSET 0XFD080520 2771#undef DDR_PHY_VTCR0_OFFSET 2772#define DDR_PHY_VTCR0_OFFSET 0XFD080528 2773#undef DDR_PHY_VTCR1_OFFSET 2774#define DDR_PHY_VTCR1_OFFSET 0XFD08052C 2775#undef DDR_PHY_ACBDLR1_OFFSET 2776#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544 2777#undef DDR_PHY_ACBDLR2_OFFSET 2778#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548 2779#undef DDR_PHY_ACBDLR6_OFFSET 2780#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558 2781#undef DDR_PHY_ACBDLR7_OFFSET 2782#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C 2783#undef DDR_PHY_ACBDLR8_OFFSET 2784#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560 2785#undef DDR_PHY_ACBDLR9_OFFSET 2786#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564 2787#undef DDR_PHY_ZQCR_OFFSET 2788#define DDR_PHY_ZQCR_OFFSET 0XFD080680 2789#undef DDR_PHY_ZQ0PR0_OFFSET 2790#define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684 2791#undef DDR_PHY_ZQ0OR0_OFFSET 2792#define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694 2793#undef DDR_PHY_ZQ0OR1_OFFSET 2794#define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698 2795#undef DDR_PHY_ZQ1PR0_OFFSET 2796#define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4 2797#undef DDR_PHY_DX0GCR0_OFFSET 2798#define DDR_PHY_DX0GCR0_OFFSET 0XFD080700 2799#undef DDR_PHY_DX0GCR4_OFFSET 2800#define DDR_PHY_DX0GCR4_OFFSET 0XFD080710 2801#undef DDR_PHY_DX0GCR5_OFFSET 2802#define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 2803#undef DDR_PHY_DX0GCR6_OFFSET 2804#define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 2805#undef DDR_PHY_DX0LCDLR2_OFFSET 2806#define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788 2807#undef DDR_PHY_DX0GTR0_OFFSET 2808#define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0 2809#undef DDR_PHY_DX1GCR0_OFFSET 2810#define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 2811#undef DDR_PHY_DX1GCR4_OFFSET 2812#define DDR_PHY_DX1GCR4_OFFSET 0XFD080810 2813#undef DDR_PHY_DX1GCR5_OFFSET 2814#define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 2815#undef DDR_PHY_DX1GCR6_OFFSET 2816#define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 2817#undef DDR_PHY_DX1LCDLR2_OFFSET 2818#define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888 2819#undef DDR_PHY_DX1GTR0_OFFSET 2820#define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0 2821#undef DDR_PHY_DX2GCR0_OFFSET 2822#define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 2823#undef DDR_PHY_DX2GCR1_OFFSET 2824#define DDR_PHY_DX2GCR1_OFFSET 0XFD080904 2825#undef DDR_PHY_DX2GCR4_OFFSET 2826#define DDR_PHY_DX2GCR4_OFFSET 0XFD080910 2827#undef DDR_PHY_DX2GCR5_OFFSET 2828#define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 2829#undef DDR_PHY_DX2GCR6_OFFSET 2830#define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 2831#undef DDR_PHY_DX2LCDLR2_OFFSET 2832#define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988 2833#undef DDR_PHY_DX2GTR0_OFFSET 2834#define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0 2835#undef DDR_PHY_DX3GCR0_OFFSET 2836#define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 2837#undef DDR_PHY_DX3GCR1_OFFSET 2838#define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04 2839#undef DDR_PHY_DX3GCR4_OFFSET 2840#define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10 2841#undef DDR_PHY_DX3GCR5_OFFSET 2842#define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 2843#undef DDR_PHY_DX3GCR6_OFFSET 2844#define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 2845#undef DDR_PHY_DX3LCDLR2_OFFSET 2846#define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88 2847#undef DDR_PHY_DX3GTR0_OFFSET 2848#define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0 2849#undef DDR_PHY_DX4GCR0_OFFSET 2850#define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 2851#undef DDR_PHY_DX4GCR1_OFFSET 2852#define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04 2853#undef DDR_PHY_DX4GCR4_OFFSET 2854#define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10 2855#undef DDR_PHY_DX4GCR5_OFFSET 2856#define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 2857#undef DDR_PHY_DX4GCR6_OFFSET 2858#define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 2859#undef DDR_PHY_DX4LCDLR2_OFFSET 2860#define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88 2861#undef DDR_PHY_DX4GTR0_OFFSET 2862#define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0 2863#undef DDR_PHY_DX5GCR0_OFFSET 2864#define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 2865#undef DDR_PHY_DX5GCR1_OFFSET 2866#define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04 2867#undef DDR_PHY_DX5GCR4_OFFSET 2868#define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10 2869#undef DDR_PHY_DX5GCR5_OFFSET 2870#define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 2871#undef DDR_PHY_DX5GCR6_OFFSET 2872#define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 2873#undef DDR_PHY_DX5LCDLR2_OFFSET 2874#define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88 2875#undef DDR_PHY_DX5GTR0_OFFSET 2876#define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0 2877#undef DDR_PHY_DX6GCR0_OFFSET 2878#define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 2879#undef DDR_PHY_DX6GCR1_OFFSET 2880#define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04 2881#undef DDR_PHY_DX6GCR4_OFFSET 2882#define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10 2883#undef DDR_PHY_DX6GCR5_OFFSET 2884#define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 2885#undef DDR_PHY_DX6GCR6_OFFSET 2886#define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 2887#undef DDR_PHY_DX6LCDLR2_OFFSET 2888#define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88 2889#undef DDR_PHY_DX6GTR0_OFFSET 2890#define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0 2891#undef DDR_PHY_DX7GCR0_OFFSET 2892#define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 2893#undef DDR_PHY_DX7GCR1_OFFSET 2894#define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04 2895#undef DDR_PHY_DX7GCR4_OFFSET 2896#define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10 2897#undef DDR_PHY_DX7GCR5_OFFSET 2898#define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 2899#undef DDR_PHY_DX7GCR6_OFFSET 2900#define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 2901#undef DDR_PHY_DX7LCDLR2_OFFSET 2902#define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88 2903#undef DDR_PHY_DX7GTR0_OFFSET 2904#define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0 2905#undef DDR_PHY_DX8GCR0_OFFSET 2906#define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 2907#undef DDR_PHY_DX8GCR1_OFFSET 2908#define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04 2909#undef DDR_PHY_DX8GCR4_OFFSET 2910#define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10 2911#undef DDR_PHY_DX8GCR5_OFFSET 2912#define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 2913#undef DDR_PHY_DX8GCR6_OFFSET 2914#define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 2915#undef DDR_PHY_DX8LCDLR2_OFFSET 2916#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88 2917#undef DDR_PHY_DX8GTR0_OFFSET 2918#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0 2919#undef DDR_PHY_DX8SL0OSC_OFFSET 2920#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 2921#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 2922#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C 2923#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 2924#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C 2925#undef DDR_PHY_DX8SL0IOCR_OFFSET 2926#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 2927#undef DDR_PHY_DX8SL1OSC_OFFSET 2928#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 2929#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 2930#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C 2931#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 2932#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C 2933#undef DDR_PHY_DX8SL1IOCR_OFFSET 2934#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 2935#undef DDR_PHY_DX8SL2OSC_OFFSET 2936#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 2937#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 2938#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C 2939#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 2940#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC 2941#undef DDR_PHY_DX8SL2IOCR_OFFSET 2942#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 2943#undef DDR_PHY_DX8SL3OSC_OFFSET 2944#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 2945#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 2946#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC 2947#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 2948#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC 2949#undef DDR_PHY_DX8SL3IOCR_OFFSET 2950#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 2951#undef DDR_PHY_DX8SL4OSC_OFFSET 2952#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 2953#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 2954#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C 2955#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 2956#define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C 2957#undef DDR_PHY_DX8SL4IOCR_OFFSET 2958#define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 2959#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 2960#define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC 2961#undef DDR_PHY_PIR_OFFSET 2962#define DDR_PHY_PIR_OFFSET 0XFD080004 2963 2964/*DDR block level reset inside of the DDR Sub System*/ 2965#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 2966#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 2967#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 2968#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F 2969#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 2970#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U 2971 2972/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 2973 evice*/ 2974#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 2975#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 2976#undef DDRC_MSTR_DEVICE_CONFIG_MASK 2977#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 2978#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 2979#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U 2980 2981/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/ 2982#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 2983#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 2984#undef DDRC_MSTR_FREQUENCY_MODE_MASK 2985#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 2986#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 2987#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U 2988 2989/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p 2990 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 2991 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra 2992 ks - 1111 - Four ranks*/ 2993#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 2994#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 2995#undef DDRC_MSTR_ACTIVE_RANKS_MASK 2996#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 2997#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 2998#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U 2999 3000/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
3001 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 3002 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th 3003 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT 3004 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/ 3005#undef DDRC_MSTR_BURST_RDWR_DEFVAL 3006#undef DDRC_MSTR_BURST_RDWR_SHIFT 3007#undef DDRC_MSTR_BURST_RDWR_MASK 3008#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 3009#define DDRC_MSTR_BURST_RDWR_SHIFT 16 3010#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U 3011 3012/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 3013 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d 3014 l_off_mode is not supported, and this bit must be set to '0'.*/ 3015#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 3016#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 3017#undef DDRC_MSTR_DLL_OFF_MODE_MASK 3018#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 3019#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 3020#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U 3021 3022/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD 3023 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w 3024 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co 3025 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/ 3026#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 3027#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 3028#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 3029#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 3030#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 3031#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U 3032 3033/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed 3034 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 3035 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/ 3036#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 3037#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 3038#undef DDRC_MSTR_GEARDOWN_MODE_MASK 3039#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 3040#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 3041#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U 3042 3043/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 3044 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 3045 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti 3046 ing is not supported in DDR4 geardown mode.*/ 3047#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 3048#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 3049#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 3050#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 3051#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 3052#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U 3053 3054/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s 3055 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable 3056 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr 3057 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/ 3058#undef DDRC_MSTR_BURSTCHOP_DEFVAL 3059#undef DDRC_MSTR_BURSTCHOP_SHIFT 3060#undef DDRC_MSTR_BURSTCHOP_MASK 3061#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 3062#define DDRC_MSTR_BURSTCHOP_SHIFT 9 3063#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U 3064 3065/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su 3066 port LPDDR4.*/ 3067#undef DDRC_MSTR_LPDDR4_DEFVAL 3068#undef DDRC_MSTR_LPDDR4_SHIFT 3069#undef DDRC_MSTR_LPDDR4_MASK 3070#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 3071#define DDRC_MSTR_LPDDR4_SHIFT 5 3072#define DDRC_MSTR_LPDDR4_MASK 0x00000020U 3073 3074/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 3075 DR4.*/ 3076#undef DDRC_MSTR_DDR4_DEFVAL 3077#undef DDRC_MSTR_DDR4_SHIFT 3078#undef DDRC_MSTR_DDR4_MASK 3079#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 3080#define DDRC_MSTR_DDR4_SHIFT 4 3081#define DDRC_MSTR_DDR4_MASK 0x00000010U 3082 3083/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su 3084 port LPDDR3.*/ 3085#undef DDRC_MSTR_LPDDR3_DEFVAL 3086#undef DDRC_MSTR_LPDDR3_SHIFT 3087#undef DDRC_MSTR_LPDDR3_MASK 3088#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 3089#define DDRC_MSTR_LPDDR3_SHIFT 3 3090#define DDRC_MSTR_LPDDR3_MASK 0x00000008U 3091 3092/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su 3093 port LPDDR2.*/ 3094#undef DDRC_MSTR_LPDDR2_DEFVAL 3095#undef DDRC_MSTR_LPDDR2_SHIFT 3096#undef DDRC_MSTR_LPDDR2_MASK 3097#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 3098#define DDRC_MSTR_LPDDR2_SHIFT 2 3099#define DDRC_MSTR_LPDDR2_MASK 0x00000004U 3100 3101/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 3102 */ 3103#undef DDRC_MSTR_DDR3_DEFVAL 3104#undef DDRC_MSTR_DDR3_SHIFT 3105#undef DDRC_MSTR_DDR3_MASK 3106#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 3107#define DDRC_MSTR_DDR3_SHIFT 0 3108#define DDRC_MSTR_DDR3_MASK 0x00000001U 3109 3110/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL 3111 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef 3112 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/ 3113#undef DDRC_MRCTRL0_MR_WR_DEFVAL 3114#undef DDRC_MRCTRL0_MR_WR_SHIFT 3115#undef DDRC_MRCTRL0_MR_WR_MASK 3116#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 3117#define DDRC_MRCTRL0_MR_WR_SHIFT 31 3118#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U 3119 3120/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 3121 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD 3122 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a 3123 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 3124 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou 3125 put Inversion of RDIMMs.*/ 3126#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 3127#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 3128#undef DDRC_MRCTRL0_MR_ADDR_MASK 3129#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 3130#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 3131#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U 3132 3133/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 3134 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E 3135 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 3136 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/ 3137#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 3138#undef DDRC_MRCTRL0_MR_RANK_SHIFT 3139#undef DDRC_MRCTRL0_MR_RANK_MASK 3140#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 3141#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 3142#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U 3143 3144/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 3145 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca 3146 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 3147 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi 3148 n is not allowed - 1 - Software intervention is allowed*/ 3149#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 3150#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3151#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 3152#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 3153#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 3154#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U 3155 3156/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/ 3157#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 3158#undef DDRC_MRCTRL0_PDA_EN_SHIFT 3159#undef DDRC_MRCTRL0_PDA_EN_MASK 3160#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 3161#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 3162#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U 3163 3164/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/ 3165#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 3166#undef DDRC_MRCTRL0_MPR_EN_SHIFT 3167#undef DDRC_MRCTRL0_MPR_EN_MASK 3168#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 3169#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 3170#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U 3171 3172/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re 3173 d*/ 3174#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 3175#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 3176#undef DDRC_MRCTRL0_MR_TYPE_MASK 3177#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 3178#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 3179#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U 3180 3181/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 3182 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi 3183 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/ 3184#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 3185#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 3186#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 3187#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 3188#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 3189#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U 3190 3191/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f 3192 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/ 3193#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 3194#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 3195#undef DDRC_DERATEEN_DERATE_BYTE_MASK 3196#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 3197#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 3198#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U 3199 3200/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD 3201 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 3202 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/ 3203#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 3204#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 3205#undef DDRC_DERATEEN_DERATE_VALUE_MASK 3206#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 3207#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 3208#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U 3209 3210/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. 3211 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 3212 mode.*/ 3213#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 3214#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 3215#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 3216#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 3217#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 3218#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U 3219 3220/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP 3221 DR3/LPDDR4. This register must not be set to zero*/ 3222#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 3223#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 3224#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 3225#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 3226#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 3227#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU 3228 3229/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f 3230 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 3231 - Allow transition from Self refresh state*/ 3232#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 3233#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 3234#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 3235#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 3236#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 3237#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U 3238 3239/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP 3240 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft 3241 are Exit from Self Refresh*/ 3242#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 3243#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 3244#undef DDRC_PWRCTL_SELFREF_SW_MASK 3245#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 3246#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 3247#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U 3248 3249/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m 3250 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 3251 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter 3252 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/ 3253#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 3254#undef DDRC_PWRCTL_MPSM_EN_SHIFT 3255#undef DDRC_PWRCTL_MPSM_EN_MASK 3256#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 3257#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 3258#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U 3259 3260/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable 3261 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD 3262 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 3263 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass 3264 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/ 3265#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 3266#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3267#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 3268#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 3269#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 3270#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U 3271 3272/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re 3273 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 3274 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe 3275 should not be set to 1. FOR PERFORMANCE ONLY.*/ 3276#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 3277#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 3278#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 3279#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 3280#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 3281#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U 3282 3283/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P 3284 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/ 3285#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 3286#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 3287#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 3288#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 3289#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 3290#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U 3291 3292/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se 3293 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/ 3294#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 3295#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 3296#undef DDRC_PWRCTL_SELFREF_EN_MASK 3297#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 3298#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 3299#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U 3300 3301/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 3302 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/ 3303#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 3304#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 3305#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 3306#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 3307#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 3308#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U 3309 3310/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed 3311 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul 3312 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/ 3313#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 3314#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 3315#undef DDRC_PWRTMG_T_DPD_X4096_MASK 3316#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 3317#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 3318#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U 3319 3320/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th 3321 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/ 3322#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 3323#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 3324#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 3325#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 3326#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 3327#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU 3328 3329/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu 3330 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 3331 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 3332 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ 3333 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/ 3334#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 3335#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 3336#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 3337#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 3338#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 3339#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U 3340 3341/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst 3342 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres 3343 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF 3344 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe 3345 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is 3346 ued to the uMCTL2. FOR PERFORMANCE ONLY.*/ 3347#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 3348#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 3349#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 3350#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 3351#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 3352#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U 3353 3354/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re 3355 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re 3356 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for 3357 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe 3358 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se 3359 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r 3360 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea 3361 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd 3362 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat 3363 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY 3364 initiated update is complete.*/ 3365#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 3366#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 3367#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 3368#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 3369#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 3370#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U 3371 3372/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n 3373 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to 3374 support LPDDR2/LPDDR3/LPDDR4*/ 3375#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 3376#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 3377#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 3378#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 3379#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 3380#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U 3381 3382/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( 3383 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup 3384 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in 3385 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 3386 uture version of the uMCTL2.*/ 3387#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 3388#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 3389#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 3390#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 3391#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 3392#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U 3393 3394/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 3395 s automatically updated when exiting reset, so it does not need to be toggled initially.*/ 3396#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 3397#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 3398#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 3399#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 3400#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 3401#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U 3402 3403/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u 3404 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis 3405 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry 3406 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 3407 his register field is changeable on the fly.*/ 3408#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 3409#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 3410#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 3411#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 3412#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 3413#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U 3414 3415/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio 3416 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 3417 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 3418 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va 3419 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value 3420 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS 3421 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/ 3422#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 3423#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 3424#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 3425#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C 3426#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 3427#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U 3428 3429/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 3430 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not 3431 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/ 3432#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 3433#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 3434#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 3435#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C 3436#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 3437#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U 3438 3439/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t 3440 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L 3441 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin 3442 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above 3443 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app 3444 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/ 3445#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 3446#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 3447#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 3448#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C 3449#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 3450#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU 3451 3452/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/ 3453#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 3454#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 3455#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 3456#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 3457#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 3458#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U 3459 3460/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur 3461 use*/ 3462#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 3463#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 3464#undef DDRC_ECCCFG0_ECC_MODE_MASK 3465#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 3466#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 3467#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U 3468 3469/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison 3470 ng, if ECCCFG1.data_poison_en=1*/ 3471#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 3472#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 3473#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 3474#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 3475#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 3476#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U 3477 3478/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/ 3479#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 3480#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 3481#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 3482#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 3483#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 3484#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U 3485 3486/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of 3487 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 3488 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC 3489 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ 3490 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo 3491 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/ 3492#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 3493#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 3494#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 3495#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 3496#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 3497#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U 3498 3499/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR 3500 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins 3501 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin 3502 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P 3503 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte 3504 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P 3505 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re 3506 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 3507 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 3508 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 3509 PR Page 1 should be treated as 'Don't care'.*/ 3510#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 3511#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 3512#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 3513#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 3514#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 3515#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U 3516 3517/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o 3518 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o 3519 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/ 3520#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 3521#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 3522#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 3523#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 3524#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 3525#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U 3526 3527/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur 3528 d to support DDR4.*/ 3529#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 3530#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 3531#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 3532#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 3533#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 3534#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U 3535 3536/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th 3537 CRC mode register setting in the DRAM.*/ 3538#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 3539#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 3540#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 3541#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 3542#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 3543#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U 3544 3545/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 3546 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t 3547 is register should be 1.*/ 3548#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 3549#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 3550#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 3551#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 3552#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 3553#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U 3554 3555/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values 3556 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte 3557 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/ 3558#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 3559#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 3560#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 3561#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C 3562#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 3563#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U 3564 3565/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - 3566 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer 3567 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/ 3568#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 3569#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 3570#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 3571#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C 3572#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 3573#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U 3574 3575/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be 3576 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis 3577 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy 3578 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er 3579 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme 3580 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON 3581 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en 3582 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) 3583 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de 3584 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 3585 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set 3586 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- 3587 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D 3588 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM 3589 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C 3590 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo 3591 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte 3592 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP 3593 H-6 Values of 0, 1 and 2 are illegal.*/ 3594#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 3595#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 3596#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 3597#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C 3598#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 3599#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU 3600 3601/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u 3602 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip 3603 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll 3604 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 3605 or LPDDR4 in this version of the uMCTL2.*/ 3606#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 3607#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 3608#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 3609#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E 3610#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 3611#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U 3612 3613/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 3614 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr 3615 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M 3616 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/ 3617#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 3618#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 3619#undef DDRC_INIT0_POST_CKE_X1024_MASK 3620#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E 3621#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 3622#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U 3623 3624/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 3625 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: 3626 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u 3627 to next integer value.*/ 3628#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 3629#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 3630#undef DDRC_INIT0_PRE_CKE_X1024_MASK 3631#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E 3632#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 3633#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU 3634 3635/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or 3636 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/ 3637#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 3638#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 3639#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 3640#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 3641#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 3642#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U 3643 3644/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl 3645 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/ 3646#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 3647#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 3648#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 3649#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 3650#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 3651#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U 3652 3653/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle 3654 . There is no known specific requirement for this; it may be set to zero.*/ 3655#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 3656#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 3657#undef DDRC_INIT1_PRE_OCD_X32_MASK 3658#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 3659#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 3660#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU 3661 3662/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/ 3663#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 3664#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 3665#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 3666#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 3667#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 3668#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U 3669 3670/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc 3671 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/ 3672#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 3673#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 3674#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 3675#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 3676#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 3677#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU 3678 3679/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately 3680 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 3681 register*/ 3682#undef DDRC_INIT3_MR_DEFVAL 3683#undef DDRC_INIT3_MR_SHIFT 3684#undef DDRC_INIT3_MR_MASK 3685#define DDRC_INIT3_MR_DEFVAL 0x00000510 3686#define DDRC_INIT3_MR_SHIFT 16 3687#define DDRC_INIT3_MR_MASK 0xFFFF0000U 3688 3689/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those 3690 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi 3691 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V 3692 lue to write to MR2 register*/ 3693#undef DDRC_INIT3_EMR_DEFVAL 3694#undef DDRC_INIT3_EMR_SHIFT 3695#undef DDRC_INIT3_EMR_MASK 3696#define DDRC_INIT3_EMR_DEFVAL 0x00000510 3697#define DDRC_INIT3_EMR_SHIFT 0 3698#define DDRC_INIT3_EMR_MASK 0x0000FFFFU 3699 3700/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 3701 egister mDDR: Unused*/ 3702#undef DDRC_INIT4_EMR2_DEFVAL 3703#undef DDRC_INIT4_EMR2_SHIFT 3704#undef DDRC_INIT4_EMR2_MASK 3705#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 3706#define DDRC_INIT4_EMR2_SHIFT 16 3707#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U 3708 3709/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 3710 rite to MR13 register*/ 3711#undef DDRC_INIT4_EMR3_DEFVAL 3712#undef DDRC_INIT4_EMR3_SHIFT 3713#undef DDRC_INIT4_EMR3_MASK 3714#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 3715#define DDRC_INIT4_EMR3_SHIFT 0 3716#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU 3717 3718/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 3719 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/ 3720#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 3721#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 3722#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 3723#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 3724#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 3725#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U 3726 3727/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD 3728 3 typically requires 10 us.*/ 3729#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 3730#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 3731#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 3732#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 3733#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 3734#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU 3735 3736/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/ 3737#undef DDRC_INIT6_MR4_DEFVAL 3738#undef DDRC_INIT6_MR4_SHIFT 3739#undef DDRC_INIT6_MR4_MASK 3740#define DDRC_INIT6_MR4_DEFVAL 0x00000000 3741#define DDRC_INIT6_MR4_SHIFT 16 3742#define DDRC_INIT6_MR4_MASK 0xFFFF0000U 3743 3744/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/ 3745#undef DDRC_INIT6_MR5_DEFVAL 3746#undef DDRC_INIT6_MR5_SHIFT 3747#undef DDRC_INIT6_MR5_MASK 3748#define DDRC_INIT6_MR5_DEFVAL 0x00000000 3749#define DDRC_INIT6_MR5_SHIFT 0 3750#define DDRC_INIT6_MR5_MASK 0x0000FFFFU 3751 3752/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/ 3753#undef DDRC_INIT7_MR6_DEFVAL 3754#undef DDRC_INIT7_MR6_SHIFT 3755#undef DDRC_INIT7_MR6_MASK 3756#define DDRC_INIT7_MR6_DEFVAL 3757#define DDRC_INIT7_MR6_SHIFT 0 3758#define DDRC_INIT7_MR6_MASK 0x0000FFFFU 3759 3760/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab 3761 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i 3762 address mirroring is enabled.*/ 3763#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 3764#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 3765#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 3766#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 3767#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 3768#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U 3769 3770/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus 3771 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 3772 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no 3773 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena 3774 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/ 3775#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 3776#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 3777#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 3778#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 3779#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 3780#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U 3781 3782/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus 3783 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 3784 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 3785 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/ 3786#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 3787#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3788#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 3789#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 3790#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 3791#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U 3792 3793/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, 3794 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 3795 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi 3796 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 3797 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi 3798 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out 3799 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/ 3800#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 3801#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 3802#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 3803#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 3804#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 3805#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U 3806 3807/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD 3808 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 3809 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t 3810 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe 3811 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar 3812 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr 3813 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 3814 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, 3815 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d 3816 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do 3817 not implement address mirroring*/ 3818#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 3819#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 3820#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 3821#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 3822#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 3823#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U 3824 3825/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD 3826 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M 3827 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t 3828 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/ 3829#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 3830#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 3831#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 3832#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 3833#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 3834#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U 3835 3836/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti 3837 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c 3838 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs 3839 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa 3840 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 3841 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi 3842 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement 3843 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u 3844 to the next integer.*/ 3845#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 3846#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 3847#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 3848#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F 3849#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 3850#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U 3851 3852/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti 3853 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co 3854 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg 3855 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl 3856 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing 3857 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r 3858 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 3859 ound it up to the next integer.*/ 3860#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 3861#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 3862#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 3863#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F 3864#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 3865#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U 3866 3867/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ 3868 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content 3869 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl 3870 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran 3871 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f 3872 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv 3873 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 3874 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair 3875 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 3876 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x 3877 . FOR PERFORMANCE ONLY.*/ 3878#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 3879#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 3880#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 3881#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F 3882#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 3883#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU 3884 3885/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 3886 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th 3887 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = 3888 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 3889 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations 3890 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/ 3891#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 3892#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 3893#undef DDRC_DRAMTMG0_WR2PRE_MASK 3894#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F 3895#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 3896#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U 3897 3898/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated 3899 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 3900 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/ 3901#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 3902#undef DDRC_DRAMTMG0_T_FAW_SHIFT 3903#undef DDRC_DRAMTMG0_T_FAW_MASK 3904#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F 3905#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 3906#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U 3907 3908/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi 3909 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 3910 No rounding up. Unit: Multiples of 1024 clocks.*/ 3911#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 3912#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 3913#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 3914#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F 3915#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 3916#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U 3917 3918/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 3919 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t 3920 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/ 3921#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 3922#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 3923#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 3924#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F 3925#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 3926#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU 3927 3928/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi 3929 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 3930 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/ 3931#undef DDRC_DRAMTMG1_T_XP_DEFVAL 3932#undef DDRC_DRAMTMG1_T_XP_SHIFT 3933#undef DDRC_DRAMTMG1_T_XP_MASK 3934#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 3935#define DDRC_DRAMTMG1_T_XP_SHIFT 16 3936#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U 3937 3938/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D 3939 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 3940 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL 3941 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf 3942 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val 3943 e. Unit: Clocks.*/ 3944#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 3945#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 3946#undef DDRC_DRAMTMG1_RD2PRE_MASK 3947#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 3948#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 3949#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U 3950 3951/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun 3952 up to next integer value. Unit: Clocks.*/ 3953#undef DDRC_DRAMTMG1_T_RC_DEFVAL 3954#undef DDRC_DRAMTMG1_T_RC_SHIFT 3955#undef DDRC_DRAMTMG1_T_RC_MASK 3956#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 3957#define DDRC_DRAMTMG1_T_RC_SHIFT 0 3958#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU 3959 3960/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s 3961 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e 3962 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above 3963 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ 3964 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ 3965#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 3966#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 3967#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 3968#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D 3969#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 3970#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U 3971 3972/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if 3973 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 3974 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte 3975 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci 3976 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ 3977#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 3978#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 3979#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 3980#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D 3981#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 3982#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U 3983 3984/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 3985 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B 3986 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include 3987 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 3988 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l 3989 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L 3990 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf 3991 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ 3992#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 3993#undef DDRC_DRAMTMG2_RD2WR_SHIFT 3994#undef DDRC_DRAMTMG2_RD2WR_MASK 3995#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D 3996#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 3997#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U 3998 3999/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba 4000 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
4001 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs 4002 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re 4003 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman 4004 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu 4005 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ 4006#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 4007#undef DDRC_DRAMTMG2_WR2RD_SHIFT 4008#undef DDRC_DRAMTMG2_WR2RD_MASK 4009#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D 4010#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 4011#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU 4012 4013/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o 4014 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 4015 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i 4016 used for the time from a MRW/MRR to a MRW/MRR.*/ 4017#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 4018#undef DDRC_DRAMTMG3_T_MRW_SHIFT 4019#undef DDRC_DRAMTMG3_T_MRW_MASK 4020#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C 4021#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 4022#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U 4023 4024/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 4025 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c 4026 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD 4027 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/ 4028#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 4029#undef DDRC_DRAMTMG3_T_MRD_SHIFT 4030#undef DDRC_DRAMTMG3_T_MRD_MASK 4031#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C 4032#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 4033#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U 4034 4035/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari 4036 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer 4037 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO 4038 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/ 4039#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 4040#undef DDRC_DRAMTMG3_T_MOD_SHIFT 4041#undef DDRC_DRAMTMG3_T_MOD_MASK 4042#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C 4043#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 4044#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU 4045 4046/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog 4047 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im 4048 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/ 4049#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 4050#undef DDRC_DRAMTMG4_T_RCD_SHIFT 4051#undef DDRC_DRAMTMG4_T_RCD_MASK 4052#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 4053#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 4054#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U 4055 4056/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum 4057 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou 4058 d it up to the next integer value. Unit: clocks.*/ 4059#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 4060#undef DDRC_DRAMTMG4_T_CCD_SHIFT 4061#undef DDRC_DRAMTMG4_T_CCD_MASK 4062#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 4063#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 4064#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U 4065 4066/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee 4067 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round 4068 it up to the next integer value. Unit: Clocks.*/ 4069#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 4070#undef DDRC_DRAMTMG4_T_RRD_SHIFT 4071#undef DDRC_DRAMTMG4_T_RRD_MASK 4072#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 4073#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 4074#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U 4075 4076/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU 4077 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO 4078 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/ 4079#undef DDRC_DRAMTMG4_T_RP_DEFVAL 4080#undef DDRC_DRAMTMG4_T_RP_SHIFT 4081#undef DDRC_DRAMTMG4_T_RP_MASK 4082#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 4083#define DDRC_DRAMTMG4_T_RP_SHIFT 0 4084#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU 4085 4086/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab 4087 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: 4088 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in 4089 eger.*/ 4090#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 4091#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 4092#undef DDRC_DRAMTMG5_T_CKSRX_MASK 4093#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 4094#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 4095#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U 4096 4097/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte 4098 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 4099 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up 4100 to next integer.*/ 4101#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 4102#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 4103#undef DDRC_DRAMTMG5_T_CKSRE_MASK 4104#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 4105#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 4106#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U 4107 4108/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se 4109 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 4110 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege 4111 .*/ 4112#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 4113#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 4114#undef DDRC_DRAMTMG5_T_CKESR_MASK 4115#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 4116#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 4117#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U 4118 4119/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 4120 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 4121 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th 4122 next integer value. Unit: Clocks.*/ 4123#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 4124#undef DDRC_DRAMTMG5_T_CKE_SHIFT 4125#undef DDRC_DRAMTMG5_T_CKE_MASK 4126#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 4127#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 4128#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU 4129 4130/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 4131 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom 4132 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 4133 devices.*/ 4134#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 4135#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 4136#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 4137#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 4138#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 4139#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U 4140 4141/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 4142 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr 4143 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD 4144 R or LPDDR2 devices.*/ 4145#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 4146#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 4147#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 4148#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 4149#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 4150#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U 4151 4152/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 4153 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 4154 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 4155 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4156#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 4157#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 4158#undef DDRC_DRAMTMG6_T_CKCSX_MASK 4159#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 4160#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 4161#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU 4162 4163/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 4164 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t 4165 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L 4166 DDR2/LPDDR3/LPDDR4 devices.*/ 4167#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 4168#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 4169#undef DDRC_DRAMTMG7_T_CKPDE_MASK 4170#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 4171#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 4172#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U 4173 4174/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable 4175 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= 4176 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti 4177 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4178#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 4179#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 4180#undef DDRC_DRAMTMG7_T_CKPDX_MASK 4181#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 4182#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 4183#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU 4184 4185/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT 4186 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi 4187 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/ 4188#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 4189#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 4190#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 4191#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 4192#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 4193#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U 4194 4195/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ 4196 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 4197 nsure this is less than or equal to t_xs_x32.*/ 4198#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 4199#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 4200#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 4201#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 4202#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 4203#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U 4204 4205/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 4206 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 4207 DR4 SDRAMs.*/ 4208#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 4209#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 4210#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 4211#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 4212#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 4213#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U 4214 4215/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 4216 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 4217 DDR4 SDRAMs.*/ 4218#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 4219#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 4220#undef DDRC_DRAMTMG8_T_XS_X32_MASK 4221#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 4222#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 4223#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU 4224 4225/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/ 4226#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 4227#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 4228#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 4229#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D 4230#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 4231#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U 4232 4233/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 4234 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro 4235 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/ 4236#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 4237#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 4238#undef DDRC_DRAMTMG9_T_CCD_S_MASK 4239#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D 4240#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 4241#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U 4242 4243/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ 4244 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D 4245 R4. Unit: Clocks.*/ 4246#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 4247#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 4248#undef DDRC_DRAMTMG9_T_RRD_S_MASK 4249#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D 4250#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 4251#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U 4252 4253/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn 4254 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 4255 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm 4256 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T 4257 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 4258 he above equation by 2, and round it up to next integer.*/ 4259#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 4260#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 4261#undef DDRC_DRAMTMG9_WR2RD_S_MASK 4262#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D 4263#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 4264#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU 4265 4266/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program 4267 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult 4268 ples of 32 clocks.*/ 4269#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 4270#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 4271#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 4272#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C 4273#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 4274#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U 4275 4276/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t 4277 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/ 4278#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 4279#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 4280#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 4281#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C 4282#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 4283#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U 4284 4285/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it 4286 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/ 4287#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 4288#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 4289#undef DDRC_DRAMTMG11_T_MPX_S_MASK 4290#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C 4291#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 4292#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U 4293 4294/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F 4295 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i 4296 teger.*/ 4297#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 4298#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 4299#undef DDRC_DRAMTMG11_T_CKMPE_MASK 4300#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C 4301#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 4302#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU 4303 4304/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ 4305 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/ 4306#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 4307#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 4308#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 4309#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 4310#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 4311#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U 4312 4313/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM 4314 /2) and round it up to next integer value.*/ 4315#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 4316#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 4317#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 4318#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 4319#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 4320#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U 4321 4322/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th 4323 s to (tMRD_PDA/2) and round it up to next integer value.*/ 4324#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 4325#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 4326#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 4327#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 4328#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 4329#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU 4330 4331/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is 4332 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s 4333 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4334#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 4335#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 4336#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 4337#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 4338#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 4339#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U 4340 4341/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 4342 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power 4343 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo 4344 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4345#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 4346#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 4347#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 4348#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 4349#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 4350#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U 4351 4352/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r 4353 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov 4354 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4355#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 4356#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 4357#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 4358#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 4359#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 4360#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U 4361 4362/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 4363 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des 4364 gns supporting DDR4 devices.*/ 4365#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 4366#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 4367#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 4368#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 4369#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 4370#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U 4371 4372/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat 4373 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo 4374 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va 4375 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 4376 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4377#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 4378#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 4379#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 4380#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 4381#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 4382#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U 4383 4384/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC 4385 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t 4386 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic 4387 s.*/ 4388#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 4389#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 4390#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 4391#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 4392#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 4393#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU 4394 4395/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati 4396 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 4397 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/ 4398#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 4399#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 4400#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 4401#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 4402#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 4403#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U 4404 4405/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ 4406 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 4407 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ 4408#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 4409#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 4410#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 4411#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 4412#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 4413#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU 4414 4415/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa 4416 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne 4417 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen 4418 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ 4419#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 4420#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 4421#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 4422#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 4423#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 4424#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U 4425 4426/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM 4427 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R 4428 fer to PHY specification for correct value.*/ 4429#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 4430#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 4431#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 4432#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 4433#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 4434#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U 4435 4436/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe 4437 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM 4438 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o 4439 latency through the RDIMM. Unit: Clocks*/ 4440#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 4441#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 4442#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 4443#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 4444#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 4445#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U 4446 4447/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG 4448 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or 4449 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val 4450 e.*/ 4451#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 4452#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 4453#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 4454#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 4455#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 4456#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U 4457 4458/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th 4459 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N 4460 te, max supported value is 8. Unit: Clocks*/ 4461#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 4462#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 4463#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 4464#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 4465#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 4466#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U 4467 4468/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin 4469 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b 4470 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t 4471 rough the RDIMM.*/ 4472#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 4473#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 4474#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 4475#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 4476#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 4477#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU 4478 4479/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 4480 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If 4481 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/ 4482#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 4483#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 4484#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 4485#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 4486#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 4487#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U 4488 4489/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa 4490 is driven.*/ 4491#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 4492#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 4493#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 4494#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 4495#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 4496#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U 4497 4498/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr 4499 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo 4500 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 4501 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ 4502 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni 4503 : Clocks*/ 4504#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 4505#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 4506#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 4507#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 4508#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 4509#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U 4510 4511/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 4512 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 4513 ligned, this timing parameter should be rounded up to the next integer value.*/ 4514#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 4515#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 4516#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 4517#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 4518#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 4519#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U 4520 4521/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 4522 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are 4523 not phase aligned, this timing parameter should be rounded up to the next integer value.*/ 4524#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 4525#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 4526#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 4527#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 4528#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 4529#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU 4530 4531/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi 4532 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/ 4533#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 4534#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 4535#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 4536#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 4537#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 4538#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U 4539 4540/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 4541 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 4542 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 4543 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device 4544 .*/ 4545#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 4546#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 4547#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 4548#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 4549#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 4550#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U 4551 4552/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres 4553 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/ 4554#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 4555#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 4556#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 4557#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 4558#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 4559#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U 4560 4561/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy 4562 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 4563 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 4564 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ 4565#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 4566#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 4567#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 4568#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 4569#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 4570#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U 4571 4572/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/ 4573#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 4574#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 4575#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 4576#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 4577#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 4578#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U 4579 4580/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl 4581 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 4582 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 4583 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ 4584#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 4585#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4586#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 4587#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 4588#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 4589#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U 4590 4591/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/ 4592#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 4593#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 4594#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 4595#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 4596#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 4597#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U 4598 4599/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 4600 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 4601 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 4602 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/ 4603#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 4604#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4605#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 4606#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 4607#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 4608#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U 4609 4610/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is 4611 only present for designs supporting DDR4 devices.*/ 4612#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 4613#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 4614#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 4615#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 4616#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 4617#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U 4618 4619/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl 4620 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir 4621 t read request when the uMCTL2 is idle. Unit: 1024 clocks*/ 4622#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 4623#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 4624#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 4625#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 4626#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 4627#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U 4628 4629/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 4630 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this 4631 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca 4632 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. 4633 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x 4634 024. Unit: 1024 clocks*/ 4635#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 4636#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 4637#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 4638#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 4639#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 4640#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU 4641 4642/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/ 4643#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 4644#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 4645#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 4646#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 4647#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 4648#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U 4649 4650/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only 4651 in designs configured to support DDR4 and LPDDR4.*/ 4652#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 4653#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 4654#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 4655#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 4656#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 4657#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U 4658 4659/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa 4660 ion*/ 4661#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 4662#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 4663#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 4664#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 4665#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 4666#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U 4667 4668/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign 4669 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/ 4670#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 4671#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 4672#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 4673#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 4674#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 4675#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U 4676 4677/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign 4678 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/ 4679#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 4680#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 4681#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 4682#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 4683#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 4684#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU 4685 4686/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value 4687 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/ 4688#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 4689#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 4690#undef DDRC_DBICTL_RD_DBI_EN_MASK 4691#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 4692#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 4693#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U 4694 4695/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va 4696 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/ 4697#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 4698#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 4699#undef DDRC_DBICTL_WR_DBI_EN_MASK 4700#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 4701#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 4702#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U 4703 4704/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's 4705 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR 4706 : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/ 4707#undef DDRC_DBICTL_DM_EN_DEFVAL 4708#undef DDRC_DBICTL_DM_EN_SHIFT 4709#undef DDRC_DBICTL_DM_EN_MASK 4710#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 4711#define DDRC_DBICTL_DM_EN_SHIFT 0 4712#define DDRC_DBICTL_DM_EN_MASK 0x00000001U 4713 4714/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres 4715 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/ 4716#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 4717#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 4718#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 4719#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 4720#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 4721#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU 4722 4723/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address 4724 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/ 4725#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 4726#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 4727#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 4728#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 4729#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 4730#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U 4731 4732/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f 4733 r each of the bank address bits is determined by adding the internal base to the value of this field.*/ 4734#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 4735#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 4736#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 4737#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 4738#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 4739#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U 4740 4741/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f 4742 r each of the bank address bits is determined by adding the internal base to the value of this field.*/ 4743#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 4744#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 4745#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 4746#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 4747#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 4748#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU 4749 4750/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre 4751 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali 4752 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o 4753 this field. If set to 15, this column address bit is set to 0.*/ 4754#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 4755#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 4756#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 4757#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 4758#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 4759#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U 4760 4761/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre 4762 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid 4763 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of 4764 this field. If set to 15, this column address bit is set to 0.*/ 4765#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 4766#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 4767#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 4768#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 4769#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 4770#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U 4771 4772/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre 4773 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid 4774 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi 4775 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i 4776 this case.*/ 4777#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 4778#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 4779#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 4780#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 4781#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 4782#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U 4783 4784/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre 4785 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid 4786 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi 4787 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/ 4788#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 4789#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 4790#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 4791#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 4792#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 4793#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU 4794 4795/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre 4796 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as 4797 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i 4798 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 4799 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr 4800 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an 4801 hence column bit 10 is used.*/ 4802#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 4803#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 4804#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 4805#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 4806#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 4807#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U 4808 4809/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre 4810 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i 4811 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i 4812 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif 4813 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col 4814 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use 4815 .*/ 4816#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 4817#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 4818#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 4819#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 4820#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 4821#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U 4822 4823/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre 4824 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid 4825 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of 4826 this field. If set to 15, this column address bit is set to 0.*/ 4827#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 4828#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 4829#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 4830#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 4831#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 4832#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U 4833 4834/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre 4835 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid 4836 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of 4837 this field. If set to 15, this column address bit is set to 0.*/ 4838#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 4839#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 4840#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 4841#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 4842#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 4843#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU 4844 4845/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width 4846 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 4847 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern 4848 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati 4849 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a 4850 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/ 4851#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 4852#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 4853#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 4854#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 4855#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 4856#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U 4857 4858/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width 4859 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. 4860 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d 4861 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per 4862 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address 4863 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h 4864 nce column bit 10 is used.*/ 4865#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 4866#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 4867#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 4868#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 4869#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 4870#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU 4871 4872/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre 4873 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/ 4874#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 4875#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 4876#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 4877#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 4878#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 4879#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U 4880 4881/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address 4882 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 4883 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 4884 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/ 4885#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 4886#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 4887#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 4888#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 4889#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 4890#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U 4891 4892/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo 4893 each of the row address bits is determined by adding the internal base to the value of this field.*/ 4894#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 4895#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 4896#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 4897#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 4898#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 4899#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U 4900 4901/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo 4902 each of the row address bits is determined by adding the internal base to the value of this field.*/ 4903#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 4904#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 4905#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 4906#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 4907#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 4908#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU 4909 4910/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address 4911 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on 4912 y in designs configured to support LPDDR3.*/ 4913#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 4914#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 4915#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 4916#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 4917#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 4918#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U 4919 4920/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre 4921 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/ 4922#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 4923#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 4924#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 4925#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 4926#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 4927#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U 4928 4929/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre 4930 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/ 4931#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 4932#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 4933#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 4934#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 4935#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 4936#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U 4937 4938/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre 4939 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/ 4940#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 4941#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 4942#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 4943#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 4944#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 4945#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U 4946 4947/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre 4948 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/ 4949#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 4950#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 4951#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 4952#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 4953#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 4954#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU 4955 4956/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre 4957 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/ 4958#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 4959#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 4960#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 4961#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 4962#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 4963#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U 4964 4965/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre 4966 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/ 4967#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 4968#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 4969#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 4970#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 4971#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 4972#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU 4973 4974/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF 4975 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 4976 et to 31, bank group address bit 1 is set to 0.*/ 4977#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 4978#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 4979#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 4980#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 4981#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 4982#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U 4983 4984/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address 4985 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/ 4986#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 4987#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 4988#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 4989#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 4990#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 4991#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU 4992 4993/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f 4994 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 4995 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 4996#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 4997#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 4998#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 4999#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 5000#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24
5001#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U 5002 5003/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f 5004 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 5005 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5006#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 5007#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 5008#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 5009#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 5010#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 5011#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U 5012 5013/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo 5014 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us 5015 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5016#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 5017#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 5018#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 5019#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 5020#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 5021#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U 5022 5023/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo 5024 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us 5025 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5026#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 5027#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 5028#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 5029#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 5030#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 5031#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU 5032 5033/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f 5034 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 5035 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5036#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 5037#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 5038#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 5039#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 5040#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 5041#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U 5042 5043/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f 5044 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 5045 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5046#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 5047#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 5048#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 5049#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 5050#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 5051#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U 5052 5053/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f 5054 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 5055 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5056#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 5057#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 5058#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 5059#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 5060#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 5061#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U 5062 5063/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f 5064 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u 5065 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5066#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 5067#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 5068#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 5069#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 5070#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 5071#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU 5072 5073/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 5074 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 5075 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ 5076#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 5077#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 5078#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 5079#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 5080#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 5081#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU 5082 5083/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ 5084 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 5085 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 5086 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/ 5087#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 5088#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 5089#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 5090#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 5091#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 5092#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U 5093 5094/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must 5095 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ 5096 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation 5097 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/ 5098#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 5099#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 5100#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 5101#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 5102#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 5103#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U 5104 5105/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) 5106 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( 5107 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC 5108 )*/ 5109#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 5110#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 5111#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 5112#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 5113#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 5114#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U 5115 5116/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 5117 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), 5118 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C 5119 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK 5120 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, 5121 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/ 5122#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 5123#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 5124#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 5125#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 5126#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 5127#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU 5128 5129/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 5130 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB 5131 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ 5132#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 5133#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 5134#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 5135#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 5136#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 5137#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U 5138 5139/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b 5140 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, 5141 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ 5142#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 5143#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 5144#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 5145#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 5146#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 5147#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U 5148 5149/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 5150 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB 5151 etc. For each rank, set its bit to 1 to enable its ODT.*/ 5152#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 5153#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 5154#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 5155#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 5156#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 5157#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U 5158 5159/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b 5160 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, 5161 etc. For each rank, set its bit to 1 to enable its ODT.*/ 5162#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 5163#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 5164#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 5165#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 5166#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 5167#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U 5168 5169/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is 5170 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t 5171 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 5172 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 5173 OR PERFORMANCE ONLY*/ 5174#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 5175#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 5176#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 5177#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 5178#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 5179#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U 5180 5181/*UNUSED*/ 5182#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 5183#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 5184#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 5185#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 5186#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 5187#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U 5188 5189/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i 5190 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries 5191 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high 5192 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les 5193 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar 5194 sing out of single bit error correction RMW operation.*/ 5195#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 5196#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 5197#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 5198#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 5199#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 5200#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U 5201 5202/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri 5203 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 5204 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca 5205 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 5206 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n 5207 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 5208 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea 5209 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/ 5210#undef DDRC_SCHED_PAGECLOSE_DEFVAL 5211#undef DDRC_SCHED_PAGECLOSE_SHIFT 5212#undef DDRC_SCHED_PAGECLOSE_MASK 5213#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 5214#define DDRC_SCHED_PAGECLOSE_SHIFT 2 5215#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U 5216 5217/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/ 5218#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 5219#undef DDRC_SCHED_PREFER_WRITE_SHIFT 5220#undef DDRC_SCHED_PREFER_WRITE_MASK 5221#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 5222#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 5223#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U 5224 5225/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio 5226 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si 5227 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t 5228 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/ 5229#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 5230#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 5231#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 5232#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 5233#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 5234#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U 5235 5236/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o 5237 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ 5238#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 5239#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 5240#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 5241#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F 5242#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 5243#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U 5244 5245/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis 5246 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 5247 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ 5248#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 5249#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 5250#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 5251#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F 5252#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 5253#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU 5254 5255/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of 5256 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ 5257#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 5258#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 5259#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 5260#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F 5261#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 5262#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U 5263 5264/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist 5265 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 5266 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ 5267#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 5268#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 5269#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 5270#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F 5271#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 5272#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU 5273 5274/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for 5275 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 5276 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su 5277 port DDR4.*/ 5278#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 5279#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 5280#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 5281#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 5282#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 5283#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U 5284 5285/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo 5286 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d 5287 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/ 5288#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 5289#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 5290#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 5291#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 5292#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 5293#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U 5294 5295/*When 1, disable write combine. FOR DEBUG ONLY*/ 5296#undef DDRC_DBG0_DIS_WC_DEFVAL 5297#undef DDRC_DBG0_DIS_WC_SHIFT 5298#undef DDRC_DBG0_DIS_WC_MASK 5299#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 5300#define DDRC_DBG0_DIS_WC_SHIFT 0 5301#define DDRC_DBG0_DIS_WC_MASK 0x00000001U 5302 5303/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, 5304 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this 5305 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank 5306 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static 5307 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/ 5308#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 5309#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 5310#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 5311#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 5312#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 5313#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U 5314 5315/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 5316 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/ 5317#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 5318#undef DDRC_DBGCMD_CTRLUPD_SHIFT 5319#undef DDRC_DBGCMD_CTRLUPD_MASK 5320#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 5321#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 5322#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U 5323 5324/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 5325 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w 5326 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor 5327 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M 5328 de.*/ 5329#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 5330#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 5331#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 5332#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 5333#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 5334#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U 5335 5336/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 5337 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can 5338 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d 5339 wn operating modes or Maximum Power Saving Mode.*/ 5340#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 5341#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 5342#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 5343#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 5344#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 5345#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U 5346 5347/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 5348 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can 5349 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d 5350 wn operating modes or Maximum Power Saving Mode.*/ 5351#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 5352#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 5353#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 5354#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 5355#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 5356#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U 5357 5358/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 5359 egister to 1 once programming is done.*/ 5360#undef DDRC_SWCTL_SW_DONE_DEFVAL 5361#undef DDRC_SWCTL_SW_DONE_SHIFT 5362#undef DDRC_SWCTL_SW_DONE_MASK 5363#define DDRC_SWCTL_SW_DONE_DEFVAL 5364#define DDRC_SWCTL_SW_DONE_SHIFT 0 5365#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U 5366 5367/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t 5368 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo 5369 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par 5370 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc 5371 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ 5372 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP 5373 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 5374 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share 5375 -AC is enabled*/ 5376#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 5377#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 5378#undef DDRC_PCCFG_BL_EXP_MODE_MASK 5379#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 5380#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 5381#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U 5382 5383/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P 5384 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p 5385 ge DDRC transactions.*/ 5386#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 5387#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 5388#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 5389#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 5390#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 5391#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U 5392 5393/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 5394 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica 5395 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/ 5396#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 5397#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 5398#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 5399#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 5400#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 5401#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U 5402 5403/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5404 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5405 imit register.*/ 5406#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 5407#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 5408#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 5409#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 5410#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 5411#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 5412 5413/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 5414 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 5415 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 5416 ess handshaking (it is not associated with any particular command).*/ 5417#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 5418#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 5419#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 5420#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 5421#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 5422#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U 5423 5424/*If set to 1, enables aging function for the read channel of the port.*/ 5425#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 5426#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 5427#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 5428#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 5429#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 5430#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U 5431 5432/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 5433 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5434 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 5435 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 5436 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 5437 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 5438 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 5439 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 5440 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 5441 he two LSBs of this register field are tied internally to 2'b00.*/ 5442#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 5443#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 5444#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 5445#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 5446#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 5447#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU 5448 5449/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5450 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5451 imit register.*/ 5452#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 5453#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 5454#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 5455#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 5456#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 5457#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 5458 5459/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 5460 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 5461 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 5462 not associated with any particular command).*/ 5463#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 5464#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 5465#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 5466#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 5467#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 5468#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U 5469 5470/*If set to 1, enables aging function for the write channel of the port.*/ 5471#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 5472#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 5473#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 5474#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 5475#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 5476#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U 5477 5478/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 5479 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5480 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 5481 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 5482 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 5483 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 5484 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 5485 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 5486#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 5487#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 5488#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 5489#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 5490#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 5491#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU 5492 5493/*Enables port n.*/ 5494#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 5495#undef DDRC_PCTRL_0_PORT_EN_SHIFT 5496#undef DDRC_PCTRL_0_PORT_EN_MASK 5497#define DDRC_PCTRL_0_PORT_EN_DEFVAL 5498#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 5499#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U 5500 5501/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 5502 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 5503 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5504#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 5505#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 5506#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 5507#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 5508#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 5509#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U 5510 5511/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 5512 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 5513 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5514#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 5515#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 5516#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 5517#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 5518#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 5519#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U 5520 5521/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 5522 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 5523 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc 5524 values.*/ 5525#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 5526#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 5527#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 5528#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 5529#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 5530#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU 5531 5532/*Specifies the timeout value for transactions mapped to the red address queue.*/ 5533#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 5534#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 5535#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 5536#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 5537#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 5538#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 5539 5540/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 5541#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 5542#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 5543#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 5544#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 5545#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 5546#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 5547 5548/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5549 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5550 imit register.*/ 5551#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 5552#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 5553#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 5554#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 5555#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 5556#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 5557 5558/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 5559 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 5560 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 5561 ess handshaking (it is not associated with any particular command).*/ 5562#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 5563#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 5564#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 5565#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 5566#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 5567#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U 5568 5569/*If set to 1, enables aging function for the read channel of the port.*/ 5570#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 5571#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 5572#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 5573#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 5574#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 5575#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U 5576 5577/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 5578 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5579 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 5580 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 5581 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 5582 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 5583 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 5584 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 5585 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 5586 he two LSBs of this register field are tied internally to 2'b00.*/ 5587#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 5588#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 5589#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 5590#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 5591#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 5592#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU 5593 5594/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5595 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5596 imit register.*/ 5597#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 5598#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 5599#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 5600#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 5601#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 5602#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 5603 5604/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 5605 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 5606 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 5607 not associated with any particular command).*/ 5608#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 5609#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 5610#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 5611#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 5612#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 5613#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U 5614 5615/*If set to 1, enables aging function for the write channel of the port.*/ 5616#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 5617#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 5618#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 5619#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 5620#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 5621#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U 5622 5623/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 5624 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5625 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 5626 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 5627 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 5628 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 5629 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 5630 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 5631#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 5632#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 5633#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 5634#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 5635#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 5636#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU 5637 5638/*Enables port n.*/ 5639#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 5640#undef DDRC_PCTRL_1_PORT_EN_SHIFT 5641#undef DDRC_PCTRL_1_PORT_EN_MASK 5642#define DDRC_PCTRL_1_PORT_EN_DEFVAL 5643#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 5644#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U 5645 5646/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 5647 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 5648 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5649#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 5650#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 5651#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 5652#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 5653#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 5654#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U 5655 5656/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 5657 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 5658 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5659#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 5660#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 5661#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 5662#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 5663#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 5664#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U 5665 5666/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 5667 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 5668 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5669#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 5670#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 5671#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 5672#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 5673#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 5674#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U 5675 5676/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le 5677 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used 5678 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 5679 ust be set to distinct values.*/ 5680#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 5681#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 5682#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 5683#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 5684#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 5685#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U 5686 5687/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 5688 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 5689 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc 5690 values.*/ 5691#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 5692#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 5693#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 5694#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 5695#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 5696#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU 5697 5698/*Specifies the timeout value for transactions mapped to the red address queue.*/ 5699#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 5700#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 5701#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 5702#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 5703#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 5704#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 5705 5706/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 5707#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 5708#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 5709#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 5710#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 5711#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 5712#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 5713 5714/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5715 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5716 imit register.*/ 5717#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 5718#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 5719#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 5720#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 5721#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 5722#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 5723 5724/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 5725 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 5726 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 5727 ess handshaking (it is not associated with any particular command).*/ 5728#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 5729#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 5730#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 5731#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 5732#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 5733#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U 5734 5735/*If set to 1, enables aging function for the read channel of the port.*/ 5736#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 5737#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 5738#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 5739#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 5740#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 5741#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U 5742 5743/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 5744 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5745 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 5746 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 5747 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 5748 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 5749 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 5750 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 5751 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 5752 he two LSBs of this register field are tied internally to 2'b00.*/ 5753#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 5754#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 5755#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 5756#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 5757#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 5758#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU 5759 5760/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5761 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5762 imit register.*/ 5763#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 5764#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 5765#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 5766#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 5767#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 5768#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 5769 5770/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 5771 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 5772 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 5773 not associated with any particular command).*/ 5774#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 5775#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 5776#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 5777#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 5778#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 5779#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U 5780 5781/*If set to 1, enables aging function for the write channel of the port.*/ 5782#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 5783#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 5784#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 5785#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 5786#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 5787#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U 5788 5789/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 5790 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5791 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 5792 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 5793 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 5794 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 5795 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 5796 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 5797#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 5798#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 5799#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 5800#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 5801#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 5802#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU 5803 5804/*Enables port n.*/ 5805#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 5806#undef DDRC_PCTRL_2_PORT_EN_SHIFT 5807#undef DDRC_PCTRL_2_PORT_EN_MASK 5808#define DDRC_PCTRL_2_PORT_EN_DEFVAL 5809#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 5810#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U 5811 5812/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 5813 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 5814 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5815#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 5816#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 5817#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 5818#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 5819#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 5820#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U 5821 5822/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 5823 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 5824 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5825#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 5826#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 5827#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 5828#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 5829#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 5830#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U 5831 5832/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 5833 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 5834 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5835#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 5836#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 5837#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 5838#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 5839#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 5840#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U 5841 5842/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le 5843 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used 5844 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 5845 ust be set to distinct values.*/ 5846#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 5847#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 5848#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 5849#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 5850#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 5851#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U 5852 5853/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 5854 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 5855 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc 5856 values.*/ 5857#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 5858#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 5859#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 5860#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 5861#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 5862#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU 5863 5864/*Specifies the timeout value for transactions mapped to the red address queue.*/ 5865#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 5866#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 5867#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 5868#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 5869#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 5870#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 5871 5872/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 5873#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 5874#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 5875#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 5876#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 5877#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 5878#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 5879 5880/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5881 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5882 imit register.*/ 5883#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 5884#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 5885#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 5886#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 5887#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 5888#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 5889 5890/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 5891 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 5892 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 5893 ess handshaking (it is not associated with any particular command).*/ 5894#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 5895#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 5896#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 5897#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 5898#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 5899#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U 5900 5901/*If set to 1, enables aging function for the read channel of the port.*/ 5902#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 5903#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 5904#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 5905#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 5906#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 5907#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U 5908 5909/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 5910 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5911 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 5912 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 5913 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 5914 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 5915 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 5916 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 5917 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 5918 he two LSBs of this register field are tied internally to 2'b00.*/ 5919#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 5920#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 5921#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 5922#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 5923#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 5924#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU 5925 5926/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 5927 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 5928 imit register.*/ 5929#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 5930#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 5931#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 5932#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 5933#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 5934#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 5935 5936/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 5937 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 5938 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 5939 not associated with any particular command).*/ 5940#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 5941#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 5942#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 5943#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 5944#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 5945#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U 5946 5947/*If set to 1, enables aging function for the write channel of the port.*/ 5948#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 5949#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 5950#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 5951#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 5952#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 5953#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U 5954 5955/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 5956 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 5957 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 5958 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 5959 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 5960 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 5961 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 5962 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 5963#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 5964#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 5965#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 5966#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 5967#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 5968#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU 5969 5970/*Enables port n.*/ 5971#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 5972#undef DDRC_PCTRL_3_PORT_EN_SHIFT 5973#undef DDRC_PCTRL_3_PORT_EN_MASK 5974#define DDRC_PCTRL_3_PORT_EN_DEFVAL 5975#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 5976#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U 5977 5978/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 5979 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 5980 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5981#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 5982#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 5983#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 5984#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 5985#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 5986#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U 5987 5988/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 5989 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 5990 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 5991#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 5992#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 5993#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 5994#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 5995#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 5996#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U 5997 5998/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 5999 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 6000 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
6001 values.*/ 6002#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 6003#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 6004#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 6005#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 6006#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 6007#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU 6008 6009/*Specifies the timeout value for transactions mapped to the red address queue.*/ 6010#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 6011#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 6012#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 6013#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 6014#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 6015#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 6016 6017/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 6018#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 6019#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 6020#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 6021#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 6022#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 6023#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 6024 6025/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6026 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ 6027#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 6028#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 6029#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 6030#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 6031#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 6032#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U 6033 6034/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6035 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ 6036#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 6037#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 6038#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 6039#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 6040#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 6041#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U 6042 6043/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c 6044 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon 6045 s to higher port priority.*/ 6046#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 6047#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 6048#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 6049#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 6050#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 6051#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU 6052 6053/*Specifies the timeout value for write transactions.*/ 6054#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 6055#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 6056#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 6057#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 6058#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 6059#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU 6060 6061/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 6062 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 6063 imit register.*/ 6064#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 6065#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 6066#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 6067#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 6068#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 6069#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 6070 6071/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 6072 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 6073 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 6074 ess handshaking (it is not associated with any particular command).*/ 6075#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 6076#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 6077#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 6078#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 6079#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 6080#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U 6081 6082/*If set to 1, enables aging function for the read channel of the port.*/ 6083#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 6084#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 6085#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 6086#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 6087#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 6088#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U 6089 6090/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 6091 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 6092 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 6093 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 6094 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 6095 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 6096 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 6097 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 6098 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 6099 he two LSBs of this register field are tied internally to 2'b00.*/ 6100#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 6101#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 6102#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 6103#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 6104#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 6105#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU 6106 6107/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 6108 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 6109 imit register.*/ 6110#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 6111#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 6112#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 6113#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 6114#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 6115#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 6116 6117/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 6118 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 6119 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 6120 not associated with any particular command).*/ 6121#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 6122#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 6123#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 6124#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 6125#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 6126#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U 6127 6128/*If set to 1, enables aging function for the write channel of the port.*/ 6129#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 6130#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 6131#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 6132#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 6133#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 6134#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U 6135 6136/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 6137 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 6138 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 6139 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 6140 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 6141 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 6142 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 6143 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 6144#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 6145#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 6146#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 6147#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 6148#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 6149#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU 6150 6151/*Enables port n.*/ 6152#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 6153#undef DDRC_PCTRL_4_PORT_EN_SHIFT 6154#undef DDRC_PCTRL_4_PORT_EN_MASK 6155#define DDRC_PCTRL_4_PORT_EN_DEFVAL 6156#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 6157#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U 6158 6159/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 6160 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 6161 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 6162#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 6163#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 6164#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 6165#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 6166#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 6167#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U 6168 6169/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 6170 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 6171 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 6172#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 6173#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 6174#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 6175#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 6176#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 6177#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U 6178 6179/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 6180 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 6181 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc 6182 values.*/ 6183#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 6184#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 6185#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 6186#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 6187#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 6188#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU 6189 6190/*Specifies the timeout value for transactions mapped to the red address queue.*/ 6191#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 6192#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 6193#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 6194#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 6195#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 6196#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 6197 6198/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 6199#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 6200#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 6201#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 6202#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 6203#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 6204#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 6205 6206/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6207 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ 6208#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 6209#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 6210#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 6211#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 6212#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 6213#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U 6214 6215/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6216 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ 6217#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 6218#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 6219#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 6220#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 6221#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 6222#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U 6223 6224/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c 6225 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon 6226 s to higher port priority.*/ 6227#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 6228#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 6229#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 6230#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 6231#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 6232#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU 6233 6234/*Specifies the timeout value for write transactions.*/ 6235#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 6236#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 6237#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 6238#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 6239#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 6240#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU 6241 6242/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 6243 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 6244 imit register.*/ 6245#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 6246#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 6247#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 6248#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 6249#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 6250#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U 6251 6252/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por 6253 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. 6254 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add 6255 ess handshaking (it is not associated with any particular command).*/ 6256#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 6257#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 6258#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 6259#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 6260#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 6261#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U 6262 6263/*If set to 1, enables aging function for the read channel of the port.*/ 6264#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 6265#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 6266#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 6267#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 6268#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 6269#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U 6270 6271/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g 6272 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 6273 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority 6274 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre 6275 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the 6276 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st 6277 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w 6278 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D 6279 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 6280 he two LSBs of this register field are tied internally to 2'b00.*/ 6281#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 6282#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 6283#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 6284#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 6285#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 6286#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU 6287 6288/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant 6289 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ 6290 imit register.*/ 6291#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 6292#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 6293#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 6294#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 6295#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 6296#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U 6297 6298/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por 6299 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register 6300 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is 6301 not associated with any particular command).*/ 6302#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 6303#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 6304#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 6305#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 6306#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 6307#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U 6308 6309/*If set to 1, enables aging function for the write channel of the port.*/ 6310#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 6311#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 6312#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 6313#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 6314#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 6315#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U 6316 6317/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 6318 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 6319 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port 6320 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 6321 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno 6322 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 6323 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch 6324 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ 6325#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 6326#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 6327#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 6328#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 6329#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 6330#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU 6331 6332/*Enables port n.*/ 6333#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 6334#undef DDRC_PCTRL_5_PORT_EN_SHIFT 6335#undef DDRC_PCTRL_5_PORT_EN_MASK 6336#define DDRC_PCTRL_5_PORT_EN_DEFVAL 6337#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 6338#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U 6339 6340/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf 6341 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is 6342 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 6343#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 6344#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 6345#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 6346#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 6347#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 6348#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U 6349 6350/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi 6351 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i 6352 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ 6353#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 6354#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 6355#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 6356#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 6357#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 6358#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U 6359 6360/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d 6361 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio 6362 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc 6363 values.*/ 6364#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 6365#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 6366#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 6367#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 6368#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 6369#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU 6370 6371/*Specifies the timeout value for transactions mapped to the red address queue.*/ 6372#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 6373#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 6374#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 6375#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 6376#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 6377#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U 6378 6379/*Specifies the timeout value for transactions mapped to the blue address queue.*/ 6380#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 6381#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 6382#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 6383#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 6384#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 6385#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU 6386 6387/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6388 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ 6389#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 6390#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 6391#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 6392#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 6393#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 6394#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U 6395 6396/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 6397 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ 6398#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 6399#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 6400#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 6401#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 6402#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 6403#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U 6404 6405/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c 6406 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon 6407 s to higher port priority.*/ 6408#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 6409#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 6410#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 6411#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 6412#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 6413#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU 6414 6415/*Specifies the timeout value for write transactions.*/ 6416#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 6417#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 6418#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 6419#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 6420#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 6421#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU 6422 6423/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine 6424 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ 6425#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 6426#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 6427#undef DDRC_SARBASE0_BASE_ADDR_MASK 6428#define DDRC_SARBASE0_BASE_ADDR_DEFVAL 6429#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 6430#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU 6431 6432/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si 6433 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 6434 or example, if register is programmed to 0, region will have 1 block.*/ 6435#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 6436#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 6437#undef DDRC_SARSIZE0_NBLOCKS_MASK 6438#define DDRC_SARSIZE0_NBLOCKS_DEFVAL 6439#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 6440#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU 6441 6442/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine 6443 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ 6444#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 6445#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 6446#undef DDRC_SARBASE1_BASE_ADDR_MASK 6447#define DDRC_SARBASE1_BASE_ADDR_DEFVAL 6448#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 6449#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU 6450 6451/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si 6452 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 6453 or example, if register is programmed to 0, region will have 1 block.*/ 6454#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 6455#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 6456#undef DDRC_SARSIZE1_NBLOCKS_MASK 6457#define DDRC_SARSIZE1_NBLOCKS_DEFVAL 6458#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 6459#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU 6460 6461/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa 6462 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne 6463 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen 6464 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ 6465#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 6466#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 6467#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 6468#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 6469#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 6470#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U 6471 6472/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM 6473 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R 6474 fer to PHY specification for correct value.*/ 6475#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 6476#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 6477#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 6478#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 6479#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 6480#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U 6481 6482/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe 6483 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM 6484 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o 6485 latency through the RDIMM. Unit: Clocks*/ 6486#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 6487#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 6488#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 6489#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 6490#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 6491#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U 6492 6493/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG 6494 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or 6495 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val 6496 e.*/ 6497#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 6498#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 6499#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 6500#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 6501#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 6502#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U 6503 6504/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th 6505 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N 6506 te, max supported value is 8. Unit: Clocks*/ 6507#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 6508#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 6509#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 6510#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 6511#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 6512#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U 6513 6514/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin 6515 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b 6516 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t 6517 rough the RDIMM.*/ 6518#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 6519#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 6520#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 6521#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 6522#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 6523#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU 6524 6525/*DDR block level reset inside of the DDR Sub System*/ 6526#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 6527#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 6528#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 6529#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F 6530#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 6531#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U 6532 6533/*Address Copy*/ 6534#undef DDR_PHY_PGCR0_ADCP_DEFVAL 6535#undef DDR_PHY_PGCR0_ADCP_SHIFT 6536#undef DDR_PHY_PGCR0_ADCP_MASK 6537#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 6538#define DDR_PHY_PGCR0_ADCP_SHIFT 31 6539#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U 6540 6541/*Reserved. Returns zeroes on reads.*/ 6542#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 6543#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 6544#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 6545#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 6546#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 6547#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U 6548 6549/*PHY FIFO Reset*/ 6550#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 6551#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 6552#undef DDR_PHY_PGCR0_PHYFRST_MASK 6553#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 6554#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 6555#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U 6556 6557/*Oscillator Mode Address/Command Delay Line Select*/ 6558#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 6559#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 6560#undef DDR_PHY_PGCR0_OSCACDL_MASK 6561#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 6562#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 6563#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U 6564 6565/*Reserved. Returns zeroes on reads.*/ 6566#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 6567#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 6568#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 6569#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 6570#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 6571#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U 6572 6573/*Digital Test Output Select*/ 6574#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 6575#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 6576#undef DDR_PHY_PGCR0_DTOSEL_MASK 6577#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 6578#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 6579#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U 6580 6581/*Reserved. Returns zeroes on reads.*/ 6582#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 6583#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 6584#undef DDR_PHY_PGCR0_RESERVED_13_MASK 6585#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 6586#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 6587#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U 6588 6589/*Oscillator Mode Division*/ 6590#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 6591#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 6592#undef DDR_PHY_PGCR0_OSCDIV_MASK 6593#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 6594#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 6595#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U 6596 6597/*Oscillator Enable*/ 6598#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 6599#undef DDR_PHY_PGCR0_OSCEN_SHIFT 6600#undef DDR_PHY_PGCR0_OSCEN_MASK 6601#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 6602#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 6603#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U 6604 6605/*Reserved. Returns zeroes on reads.*/ 6606#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 6607#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 6608#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 6609#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 6610#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 6611#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU 6612 6613/*Clear Training Status Registers*/ 6614#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 6615#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 6616#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 6617#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 6618#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 6619#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U 6620 6621/*Clear Impedance Calibration*/ 6622#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 6623#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 6624#undef DDR_PHY_PGCR2_CLRZCAL_MASK 6625#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 6626#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 6627#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U 6628 6629/*Clear Parity Error*/ 6630#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 6631#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 6632#undef DDR_PHY_PGCR2_CLRPERR_MASK 6633#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 6634#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 6635#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U 6636 6637/*Initialization Complete Pin Configuration*/ 6638#undef DDR_PHY_PGCR2_ICPC_DEFVAL 6639#undef DDR_PHY_PGCR2_ICPC_SHIFT 6640#undef DDR_PHY_PGCR2_ICPC_MASK 6641#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 6642#define DDR_PHY_PGCR2_ICPC_SHIFT 28 6643#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U 6644 6645/*Data Training PUB Mode Exit Timer*/ 6646#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 6647#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 6648#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 6649#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 6650#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 6651#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U 6652 6653/*Initialization Bypass*/ 6654#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 6655#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 6656#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 6657#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 6658#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 6659#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U 6660 6661/*PLL FSM Bypass*/ 6662#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 6663#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 6664#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 6665#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 6666#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 6667#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U 6668 6669/*Refresh Period*/ 6670#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 6671#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 6672#undef DDR_PHY_PGCR2_TREFPRD_MASK 6673#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 6674#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 6675#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU 6676 6677/*CKN Enable*/ 6678#undef DDR_PHY_PGCR3_CKNEN_DEFVAL 6679#undef DDR_PHY_PGCR3_CKNEN_SHIFT 6680#undef DDR_PHY_PGCR3_CKNEN_MASK 6681#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 6682#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 6683#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U 6684 6685/*CK Enable*/ 6686#undef DDR_PHY_PGCR3_CKEN_DEFVAL 6687#undef DDR_PHY_PGCR3_CKEN_SHIFT 6688#undef DDR_PHY_PGCR3_CKEN_MASK 6689#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 6690#define DDR_PHY_PGCR3_CKEN_SHIFT 16 6691#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U 6692 6693/*Reserved. Return zeroes on reads.*/ 6694#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL 6695#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT 6696#undef DDR_PHY_PGCR3_RESERVED_15_MASK 6697#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 6698#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 6699#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U 6700 6701/*Enable Clock Gating for AC [0] ctl_rd_clk*/ 6702#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 6703#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 6704#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK 6705#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 6706#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 6707#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U 6708 6709/*Enable Clock Gating for AC [0] ddr_clk*/ 6710#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 6711#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 6712#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK 6713#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 6714#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 6715#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U 6716 6717/*Enable Clock Gating for AC [0] ctl_clk*/ 6718#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 6719#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 6720#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK 6721#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 6722#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 6723#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U 6724 6725/*Reserved. Return zeroes on reads.*/ 6726#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL 6727#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT 6728#undef DDR_PHY_PGCR3_RESERVED_8_MASK 6729#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 6730#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 6731#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U 6732 6733/*Controls DDL Bypass Modes*/ 6734#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 6735#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6736#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK 6737#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 6738#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 6739#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U 6740 6741/*IO Loop-Back Select*/ 6742#undef DDR_PHY_PGCR3_IOLB_DEFVAL 6743#undef DDR_PHY_PGCR3_IOLB_SHIFT 6744#undef DDR_PHY_PGCR3_IOLB_MASK 6745#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 6746#define DDR_PHY_PGCR3_IOLB_SHIFT 5 6747#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U 6748 6749/*AC Receive FIFO Read Mode*/ 6750#undef DDR_PHY_PGCR3_RDMODE_DEFVAL 6751#undef DDR_PHY_PGCR3_RDMODE_SHIFT 6752#undef DDR_PHY_PGCR3_RDMODE_MASK 6753#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 6754#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 6755#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U 6756 6757/*Read FIFO Reset Disable*/ 6758#undef DDR_PHY_PGCR3_DISRST_DEFVAL 6759#undef DDR_PHY_PGCR3_DISRST_SHIFT 6760#undef DDR_PHY_PGCR3_DISRST_MASK 6761#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 6762#define DDR_PHY_PGCR3_DISRST_SHIFT 2 6763#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U 6764 6765/*Clock Level when Clock Gating*/ 6766#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 6767#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT 6768#undef DDR_PHY_PGCR3_CLKLEVEL_MASK 6769#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 6770#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 6771#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U 6772 6773/*Frequency B Ratio Term*/ 6774#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 6775#undef DDR_PHY_PGCR5_FRQBT_SHIFT 6776#undef DDR_PHY_PGCR5_FRQBT_MASK 6777#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 6778#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 6779#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U 6780 6781/*Frequency A Ratio Term*/ 6782#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 6783#undef DDR_PHY_PGCR5_FRQAT_SHIFT 6784#undef DDR_PHY_PGCR5_FRQAT_MASK 6785#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 6786#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 6787#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U 6788 6789/*DFI Disconnect Time Period*/ 6790#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 6791#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 6792#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 6793#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 6794#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 6795#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U 6796 6797/*Receiver bias core side control*/ 6798#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 6799#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 6800#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 6801#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 6802#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 6803#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U 6804 6805/*Reserved. Return zeroes on reads.*/ 6806#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 6807#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 6808#undef DDR_PHY_PGCR5_RESERVED_3_MASK 6809#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 6810#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 6811#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U 6812 6813/*Internal VREF generator REFSEL ragne select*/ 6814#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 6815#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 6816#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 6817#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 6818#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 6819#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U 6820 6821/*DDL Page Read Write select*/ 6822#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 6823#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 6824#undef DDR_PHY_PGCR5_DDLPGACT_MASK 6825#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 6826#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 6827#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U 6828 6829/*DDL Page Read Write select*/ 6830#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 6831#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 6832#undef DDR_PHY_PGCR5_DDLPGRW_MASK 6833#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 6834#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 6835#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U 6836 6837/*PLL Power-Down Time*/ 6838#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 6839#undef DDR_PHY_PTR0_TPLLPD_SHIFT 6840#undef DDR_PHY_PTR0_TPLLPD_MASK 6841#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 6842#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 6843#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U 6844 6845/*PLL Gear Shift Time*/ 6846#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 6847#undef DDR_PHY_PTR0_TPLLGS_SHIFT 6848#undef DDR_PHY_PTR0_TPLLGS_MASK 6849#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 6850#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 6851#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U 6852 6853/*PHY Reset Time*/ 6854#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 6855#undef DDR_PHY_PTR0_TPHYRST_SHIFT 6856#undef DDR_PHY_PTR0_TPHYRST_MASK 6857#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 6858#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 6859#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU 6860 6861/*PLL Lock Time*/ 6862#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 6863#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 6864#undef DDR_PHY_PTR1_TPLLLOCK_MASK 6865#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 6866#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 6867#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U 6868 6869/*Reserved. Returns zeroes on reads.*/ 6870#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 6871#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 6872#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 6873#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 6874#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 6875#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U 6876 6877/*PLL Reset Time*/ 6878#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 6879#undef DDR_PHY_PTR1_TPLLRST_SHIFT 6880#undef DDR_PHY_PTR1_TPLLRST_MASK 6881#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 6882#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 6883#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU 6884 6885/*Reserved. Return zeroes on reads.*/ 6886#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 6887#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 6888#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 6889#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 6890#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 6891#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U 6892 6893/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d 6894 fault calculation.*/ 6895#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 6896#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 6897#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 6898#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 6899#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 6900#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U 6901 6902/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/ 6903#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 6904#undef DDR_PHY_DSGCR_RDBICL_SHIFT 6905#undef DDR_PHY_DSGCR_RDBICL_MASK 6906#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 6907#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 6908#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U 6909 6910/*PHY Impedance Update Enable*/ 6911#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 6912#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 6913#undef DDR_PHY_DSGCR_PHYZUEN_MASK 6914#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 6915#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 6916#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U 6917 6918/*Reserved. Return zeroes on reads.*/ 6919#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 6920#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 6921#undef DDR_PHY_DSGCR_RESERVED_22_MASK 6922#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 6923#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 6924#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U 6925 6926/*SDRAM Reset Output Enable*/ 6927#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 6928#undef DDR_PHY_DSGCR_RSTOE_SHIFT 6929#undef DDR_PHY_DSGCR_RSTOE_MASK 6930#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 6931#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 6932#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U 6933 6934/*Single Data Rate Mode*/ 6935#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 6936#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 6937#undef DDR_PHY_DSGCR_SDRMODE_MASK 6938#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 6939#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 6940#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U 6941 6942/*Reserved. Return zeroes on reads.*/ 6943#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 6944#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 6945#undef DDR_PHY_DSGCR_RESERVED_18_MASK 6946#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 6947#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 6948#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U 6949 6950/*ATO Analog Test Enable*/ 6951#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 6952#undef DDR_PHY_DSGCR_ATOAE_SHIFT 6953#undef DDR_PHY_DSGCR_ATOAE_MASK 6954#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 6955#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 6956#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U 6957 6958/*DTO Output Enable*/ 6959#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 6960#undef DDR_PHY_DSGCR_DTOOE_SHIFT 6961#undef DDR_PHY_DSGCR_DTOOE_MASK 6962#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 6963#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 6964#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U 6965 6966/*DTO I/O Mode*/ 6967#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 6968#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 6969#undef DDR_PHY_DSGCR_DTOIOM_MASK 6970#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 6971#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 6972#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U 6973 6974/*DTO Power Down Receiver*/ 6975#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 6976#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 6977#undef DDR_PHY_DSGCR_DTOPDR_MASK 6978#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 6979#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 6980#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U 6981 6982/*Reserved. Return zeroes on reads*/ 6983#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 6984#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 6985#undef DDR_PHY_DSGCR_RESERVED_13_MASK 6986#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 6987#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 6988#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U 6989 6990/*DTO On-Die Termination*/ 6991#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 6992#undef DDR_PHY_DSGCR_DTOODT_SHIFT 6993#undef DDR_PHY_DSGCR_DTOODT_MASK 6994#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 6995#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 6996#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U 6997 6998/*PHY Update Acknowledge Delay*/ 6999#undef DDR_PHY_DSGCR_PUAD_DEFVAL 7000#undef DDR_PHY_DSGCR_PUAD_SHIFT
7001#undef DDR_PHY_DSGCR_PUAD_MASK 7002#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 7003#define DDR_PHY_DSGCR_PUAD_SHIFT 6 7004#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U 7005 7006/*Controller Update Acknowledge Enable*/ 7007#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 7008#undef DDR_PHY_DSGCR_CUAEN_SHIFT 7009#undef DDR_PHY_DSGCR_CUAEN_MASK 7010#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 7011#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 7012#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U 7013 7014/*Reserved. Return zeroes on reads*/ 7015#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 7016#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 7017#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 7018#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 7019#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 7020#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U 7021 7022/*Controller Impedance Update Enable*/ 7023#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 7024#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 7025#undef DDR_PHY_DSGCR_CTLZUEN_MASK 7026#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 7027#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 7028#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U 7029 7030/*Reserved. Return zeroes on reads*/ 7031#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 7032#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 7033#undef DDR_PHY_DSGCR_RESERVED_1_MASK 7034#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 7035#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 7036#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U 7037 7038/*PHY Update Request Enable*/ 7039#undef DDR_PHY_DSGCR_PUREN_DEFVAL 7040#undef DDR_PHY_DSGCR_PUREN_SHIFT 7041#undef DDR_PHY_DSGCR_PUREN_MASK 7042#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 7043#define DDR_PHY_DSGCR_PUREN_SHIFT 0 7044#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U 7045 7046/*DDR4 Gear Down Timing.*/ 7047#undef DDR_PHY_DCR_GEARDN_DEFVAL 7048#undef DDR_PHY_DCR_GEARDN_SHIFT 7049#undef DDR_PHY_DCR_GEARDN_MASK 7050#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D 7051#define DDR_PHY_DCR_GEARDN_SHIFT 31 7052#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U 7053 7054/*Un-used Bank Group*/ 7055#undef DDR_PHY_DCR_UBG_DEFVAL 7056#undef DDR_PHY_DCR_UBG_SHIFT 7057#undef DDR_PHY_DCR_UBG_MASK 7058#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D 7059#define DDR_PHY_DCR_UBG_SHIFT 30 7060#define DDR_PHY_DCR_UBG_MASK 0x40000000U 7061 7062/*Un-buffered DIMM Address Mirroring*/ 7063#undef DDR_PHY_DCR_UDIMM_DEFVAL 7064#undef DDR_PHY_DCR_UDIMM_SHIFT 7065#undef DDR_PHY_DCR_UDIMM_MASK 7066#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D 7067#define DDR_PHY_DCR_UDIMM_SHIFT 29 7068#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U 7069 7070/*DDR 2T Timing*/ 7071#undef DDR_PHY_DCR_DDR2T_DEFVAL 7072#undef DDR_PHY_DCR_DDR2T_SHIFT 7073#undef DDR_PHY_DCR_DDR2T_MASK 7074#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D 7075#define DDR_PHY_DCR_DDR2T_SHIFT 28 7076#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U 7077 7078/*No Simultaneous Rank Access*/ 7079#undef DDR_PHY_DCR_NOSRA_DEFVAL 7080#undef DDR_PHY_DCR_NOSRA_SHIFT 7081#undef DDR_PHY_DCR_NOSRA_MASK 7082#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D 7083#define DDR_PHY_DCR_NOSRA_SHIFT 27 7084#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U 7085 7086/*Reserved. Return zeroes on reads.*/ 7087#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 7088#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 7089#undef DDR_PHY_DCR_RESERVED_26_18_MASK 7090#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D 7091#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 7092#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U 7093 7094/*Byte Mask*/ 7095#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 7096#undef DDR_PHY_DCR_BYTEMASK_SHIFT 7097#undef DDR_PHY_DCR_BYTEMASK_MASK 7098#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D 7099#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 7100#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U 7101 7102/*DDR Type*/ 7103#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 7104#undef DDR_PHY_DCR_DDRTYPE_SHIFT 7105#undef DDR_PHY_DCR_DDRTYPE_MASK 7106#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D 7107#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 7108#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U 7109 7110/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/ 7111#undef DDR_PHY_DCR_MPRDQ_DEFVAL 7112#undef DDR_PHY_DCR_MPRDQ_SHIFT 7113#undef DDR_PHY_DCR_MPRDQ_MASK 7114#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D 7115#define DDR_PHY_DCR_MPRDQ_SHIFT 7 7116#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U 7117 7118/*Primary DQ (DDR3 Only)*/ 7119#undef DDR_PHY_DCR_PDQ_DEFVAL 7120#undef DDR_PHY_DCR_PDQ_SHIFT 7121#undef DDR_PHY_DCR_PDQ_MASK 7122#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D 7123#define DDR_PHY_DCR_PDQ_SHIFT 4 7124#define DDR_PHY_DCR_PDQ_MASK 0x00000070U 7125 7126/*DDR 8-Bank*/ 7127#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 7128#undef DDR_PHY_DCR_DDR8BNK_SHIFT 7129#undef DDR_PHY_DCR_DDR8BNK_MASK 7130#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D 7131#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 7132#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U 7133 7134/*DDR Mode*/ 7135#undef DDR_PHY_DCR_DDRMD_DEFVAL 7136#undef DDR_PHY_DCR_DDRMD_SHIFT 7137#undef DDR_PHY_DCR_DDRMD_MASK 7138#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D 7139#define DDR_PHY_DCR_DDRMD_SHIFT 0 7140#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U 7141 7142/*Reserved. Return zeroes on reads.*/ 7143#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 7144#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 7145#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 7146#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 7147#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 7148#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U 7149 7150/*Activate to activate command delay (different banks)*/ 7151#undef DDR_PHY_DTPR0_TRRD_DEFVAL 7152#undef DDR_PHY_DTPR0_TRRD_SHIFT 7153#undef DDR_PHY_DTPR0_TRRD_MASK 7154#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 7155#define DDR_PHY_DTPR0_TRRD_SHIFT 24 7156#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U 7157 7158/*Reserved. Return zeroes on reads.*/ 7159#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 7160#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 7161#undef DDR_PHY_DTPR0_RESERVED_23_MASK 7162#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 7163#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 7164#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U 7165 7166/*Activate to precharge command delay*/ 7167#undef DDR_PHY_DTPR0_TRAS_DEFVAL 7168#undef DDR_PHY_DTPR0_TRAS_SHIFT 7169#undef DDR_PHY_DTPR0_TRAS_MASK 7170#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 7171#define DDR_PHY_DTPR0_TRAS_SHIFT 16 7172#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U 7173 7174/*Reserved. Return zeroes on reads.*/ 7175#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 7176#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 7177#undef DDR_PHY_DTPR0_RESERVED_15_MASK 7178#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 7179#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 7180#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U 7181 7182/*Precharge command period*/ 7183#undef DDR_PHY_DTPR0_TRP_DEFVAL 7184#undef DDR_PHY_DTPR0_TRP_SHIFT 7185#undef DDR_PHY_DTPR0_TRP_MASK 7186#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 7187#define DDR_PHY_DTPR0_TRP_SHIFT 8 7188#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U 7189 7190/*Reserved. Return zeroes on reads.*/ 7191#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 7192#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 7193#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 7194#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 7195#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 7196#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U 7197 7198/*Internal read to precharge command delay*/ 7199#undef DDR_PHY_DTPR0_TRTP_DEFVAL 7200#undef DDR_PHY_DTPR0_TRTP_SHIFT 7201#undef DDR_PHY_DTPR0_TRTP_MASK 7202#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 7203#define DDR_PHY_DTPR0_TRTP_SHIFT 0 7204#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU 7205 7206/*Reserved. Return zeroes on reads.*/ 7207#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 7208#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 7209#undef DDR_PHY_DTPR1_RESERVED_31_MASK 7210#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E 7211#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 7212#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U 7213 7214/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/ 7215#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 7216#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 7217#undef DDR_PHY_DTPR1_TWLMRD_MASK 7218#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E 7219#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 7220#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U 7221 7222/*Reserved. Return zeroes on reads.*/ 7223#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 7224#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 7225#undef DDR_PHY_DTPR1_RESERVED_23_MASK 7226#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E 7227#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 7228#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U 7229 7230/*4-bank activate period*/ 7231#undef DDR_PHY_DTPR1_TFAW_DEFVAL 7232#undef DDR_PHY_DTPR1_TFAW_SHIFT 7233#undef DDR_PHY_DTPR1_TFAW_MASK 7234#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E 7235#define DDR_PHY_DTPR1_TFAW_SHIFT 16 7236#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U 7237 7238/*Reserved. Return zeroes on reads.*/ 7239#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 7240#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 7241#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 7242#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E 7243#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 7244#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U 7245 7246/*Load mode update delay (DDR4 and DDR3 only)*/ 7247#undef DDR_PHY_DTPR1_TMOD_DEFVAL 7248#undef DDR_PHY_DTPR1_TMOD_SHIFT 7249#undef DDR_PHY_DTPR1_TMOD_MASK 7250#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E 7251#define DDR_PHY_DTPR1_TMOD_SHIFT 8 7252#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U 7253 7254/*Reserved. Return zeroes on reads.*/ 7255#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 7256#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 7257#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 7258#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E 7259#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 7260#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U 7261 7262/*Load mode cycle time*/ 7263#undef DDR_PHY_DTPR1_TMRD_DEFVAL 7264#undef DDR_PHY_DTPR1_TMRD_SHIFT 7265#undef DDR_PHY_DTPR1_TMRD_MASK 7266#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E 7267#define DDR_PHY_DTPR1_TMRD_SHIFT 0 7268#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU 7269 7270/*Reserved. Return zeroes on reads.*/ 7271#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 7272#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 7273#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 7274#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 7275#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 7276#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U 7277 7278/*Read to Write command delay. Valid values are*/ 7279#undef DDR_PHY_DTPR2_TRTW_DEFVAL 7280#undef DDR_PHY_DTPR2_TRTW_SHIFT 7281#undef DDR_PHY_DTPR2_TRTW_MASK 7282#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 7283#define DDR_PHY_DTPR2_TRTW_SHIFT 28 7284#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U 7285 7286/*Reserved. Return zeroes on reads.*/ 7287#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 7288#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 7289#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 7290#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 7291#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 7292#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U 7293 7294/*Read to ODT delay (DDR3 only)*/ 7295#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 7296#undef DDR_PHY_DTPR2_TRTODT_SHIFT 7297#undef DDR_PHY_DTPR2_TRTODT_MASK 7298#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 7299#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 7300#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U 7301 7302/*Reserved. Return zeroes on reads.*/ 7303#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 7304#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 7305#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 7306#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 7307#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 7308#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U 7309 7310/*CKE minimum pulse width*/ 7311#undef DDR_PHY_DTPR2_TCKE_DEFVAL 7312#undef DDR_PHY_DTPR2_TCKE_SHIFT 7313#undef DDR_PHY_DTPR2_TCKE_MASK 7314#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 7315#define DDR_PHY_DTPR2_TCKE_SHIFT 16 7316#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U 7317 7318/*Reserved. Return zeroes on reads.*/ 7319#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 7320#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 7321#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 7322#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 7323#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 7324#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U 7325 7326/*Self refresh exit delay*/ 7327#undef DDR_PHY_DTPR2_TXS_DEFVAL 7328#undef DDR_PHY_DTPR2_TXS_SHIFT 7329#undef DDR_PHY_DTPR2_TXS_MASK 7330#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 7331#define DDR_PHY_DTPR2_TXS_SHIFT 0 7332#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU 7333 7334/*ODT turn-off delay extension*/ 7335#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 7336#undef DDR_PHY_DTPR3_TOFDX_SHIFT 7337#undef DDR_PHY_DTPR3_TOFDX_MASK 7338#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 7339#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 7340#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U 7341 7342/*Read to read and write to write command delay*/ 7343#undef DDR_PHY_DTPR3_TCCD_DEFVAL 7344#undef DDR_PHY_DTPR3_TCCD_SHIFT 7345#undef DDR_PHY_DTPR3_TCCD_MASK 7346#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 7347#define DDR_PHY_DTPR3_TCCD_SHIFT 26 7348#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U 7349 7350/*DLL locking time*/ 7351#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 7352#undef DDR_PHY_DTPR3_TDLLK_SHIFT 7353#undef DDR_PHY_DTPR3_TDLLK_MASK 7354#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 7355#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 7356#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U 7357 7358/*Reserved. Return zeroes on reads.*/ 7359#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 7360#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 7361#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 7362#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 7363#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 7364#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U 7365 7366/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/ 7367#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 7368#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 7369#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 7370#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 7371#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 7372#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U 7373 7374/*Reserved. Return zeroes on reads.*/ 7375#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 7376#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 7377#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 7378#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 7379#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 7380#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U 7381 7382/*DQS output access time from CK/CK# (LPDDR2/3 only)*/ 7383#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 7384#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 7385#undef DDR_PHY_DTPR3_TDQSCK_MASK 7386#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 7387#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 7388#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U 7389 7390/*Reserved. Return zeroes on reads.*/ 7391#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 7392#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 7393#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 7394#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 7395#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 7396#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U 7397 7398/*ODT turn-on/turn-off delays (DDR2 only)*/ 7399#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 7400#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 7401#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 7402#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 7403#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 7404#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U 7405 7406/*Reserved. Return zeroes on reads.*/ 7407#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 7408#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 7409#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 7410#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 7411#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 7412#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U 7413 7414/*Refresh-to-Refresh*/ 7415#undef DDR_PHY_DTPR4_TRFC_DEFVAL 7416#undef DDR_PHY_DTPR4_TRFC_SHIFT 7417#undef DDR_PHY_DTPR4_TRFC_MASK 7418#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 7419#define DDR_PHY_DTPR4_TRFC_SHIFT 16 7420#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U 7421 7422/*Reserved. Return zeroes on reads.*/ 7423#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 7424#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 7425#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 7426#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 7427#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 7428#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U 7429 7430/*Write leveling output delay*/ 7431#undef DDR_PHY_DTPR4_TWLO_DEFVAL 7432#undef DDR_PHY_DTPR4_TWLO_SHIFT 7433#undef DDR_PHY_DTPR4_TWLO_MASK 7434#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 7435#define DDR_PHY_DTPR4_TWLO_SHIFT 8 7436#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U 7437 7438/*Reserved. Return zeroes on reads.*/ 7439#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 7440#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 7441#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 7442#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 7443#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 7444#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U 7445 7446/*Power down exit delay*/ 7447#undef DDR_PHY_DTPR4_TXP_DEFVAL 7448#undef DDR_PHY_DTPR4_TXP_SHIFT 7449#undef DDR_PHY_DTPR4_TXP_MASK 7450#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 7451#define DDR_PHY_DTPR4_TXP_SHIFT 0 7452#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU 7453 7454/*Reserved. Return zeroes on reads.*/ 7455#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 7456#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 7457#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 7458#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 7459#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 7460#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U 7461 7462/*Activate to activate command delay (same bank)*/ 7463#undef DDR_PHY_DTPR5_TRC_DEFVAL 7464#undef DDR_PHY_DTPR5_TRC_SHIFT 7465#undef DDR_PHY_DTPR5_TRC_MASK 7466#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 7467#define DDR_PHY_DTPR5_TRC_SHIFT 16 7468#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U 7469 7470/*Reserved. Return zeroes on reads.*/ 7471#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 7472#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 7473#undef DDR_PHY_DTPR5_RESERVED_15_MASK 7474#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 7475#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 7476#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U 7477 7478/*Activate to read or write delay*/ 7479#undef DDR_PHY_DTPR5_TRCD_DEFVAL 7480#undef DDR_PHY_DTPR5_TRCD_SHIFT 7481#undef DDR_PHY_DTPR5_TRCD_MASK 7482#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 7483#define DDR_PHY_DTPR5_TRCD_SHIFT 8 7484#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U 7485 7486/*Reserved. Return zeroes on reads.*/ 7487#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 7488#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 7489#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 7490#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 7491#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 7492#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U 7493 7494/*Internal write to read command delay*/ 7495#undef DDR_PHY_DTPR5_TWTR_DEFVAL 7496#undef DDR_PHY_DTPR5_TWTR_SHIFT 7497#undef DDR_PHY_DTPR5_TWTR_MASK 7498#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 7499#define DDR_PHY_DTPR5_TWTR_SHIFT 0 7500#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU 7501 7502/*PUB Write Latency Enable*/ 7503#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 7504#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 7505#undef DDR_PHY_DTPR6_PUBWLEN_MASK 7506#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 7507#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 7508#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U 7509 7510/*PUB Read Latency Enable*/ 7511#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 7512#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 7513#undef DDR_PHY_DTPR6_PUBRLEN_MASK 7514#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 7515#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 7516#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U 7517 7518/*Reserved. Return zeroes on reads.*/ 7519#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 7520#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 7521#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 7522#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 7523#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 7524#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U 7525 7526/*Write Latency*/ 7527#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 7528#undef DDR_PHY_DTPR6_PUBWL_SHIFT 7529#undef DDR_PHY_DTPR6_PUBWL_MASK 7530#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 7531#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 7532#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U 7533 7534/*Reserved. Return zeroes on reads.*/ 7535#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 7536#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 7537#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 7538#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 7539#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 7540#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U 7541 7542/*Read Latency*/ 7543#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 7544#undef DDR_PHY_DTPR6_PUBRL_SHIFT 7545#undef DDR_PHY_DTPR6_PUBRL_MASK 7546#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 7547#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 7548#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU 7549 7550/*Reserved. Return zeroes on reads.*/ 7551#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 7552#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 7553#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 7554#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 7555#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 7556#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U 7557 7558/*RDMIMM Quad CS Enable*/ 7559#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 7560#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 7561#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 7562#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 7563#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 7564#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U 7565 7566/*Reserved. Return zeroes on reads.*/ 7567#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 7568#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 7569#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 7570#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 7571#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 7572#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U 7573 7574/*RDIMM Outputs I/O Mode*/ 7575#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 7576#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 7577#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 7578#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 7579#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 7580#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U 7581 7582/*Reserved. Return zeroes on reads.*/ 7583#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 7584#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 7585#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 7586#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 7587#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 7588#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U 7589 7590/*ERROUT# Output Enable*/ 7591#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 7592#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 7593#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 7594#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 7595#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 7596#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U 7597 7598/*ERROUT# I/O Mode*/ 7599#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 7600#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 7601#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 7602#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 7603#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 7604#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U 7605 7606/*ERROUT# Power Down Receiver*/ 7607#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 7608#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 7609#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 7610#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 7611#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 7612#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U 7613 7614/*Reserved. Return zeroes on reads.*/ 7615#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 7616#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 7617#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 7618#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 7619#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 7620#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U 7621 7622/*ERROUT# On-Die Termination*/ 7623#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 7624#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 7625#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 7626#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 7627#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 7628#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U 7629 7630/*Load Reduced DIMM*/ 7631#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 7632#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 7633#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 7634#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 7635#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 7636#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U 7637 7638/*PAR_IN I/O Mode*/ 7639#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 7640#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 7641#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 7642#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 7643#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 7644#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U 7645 7646/*Reserved. Return zeroes on reads.*/ 7647#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 7648#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 7649#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 7650#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 7651#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 7652#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U 7653 7654/*Reserved. Return zeroes on reads.*/ 7655#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 7656#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 7657#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 7658#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 7659#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 7660#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U 7661 7662/*Rank Mirror Enable.*/ 7663#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 7664#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 7665#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 7666#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 7667#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 7668#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U 7669 7670/*Reserved. Return zeroes on reads.*/ 7671#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 7672#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 7673#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 7674#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 7675#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 7676#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U 7677 7678/*Stop on Parity Error*/ 7679#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 7680#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 7681#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 7682#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 7683#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 7684#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U 7685 7686/*Parity Error No Registering*/ 7687#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 7688#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 7689#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 7690#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 7691#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 7692#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U 7693 7694/*Registered DIMM*/ 7695#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 7696#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 7697#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 7698#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 7699#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 7700#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U 7701 7702/*Reserved. Return zeroes on reads.*/ 7703#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 7704#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 7705#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 7706#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 7707#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 7708#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U 7709 7710/*Address [17] B-side Inversion Disable*/ 7711#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 7712#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 7713#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 7714#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 7715#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 7716#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U 7717 7718/*Reserved. Return zeroes on reads.*/ 7719#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 7720#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 7721#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 7722#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 7723#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 7724#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U 7725 7726/*Command word to command word programming delay*/ 7727#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 7728#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 7729#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 7730#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 7731#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 7732#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U 7733 7734/*Reserved. Return zeroes on reads.*/ 7735#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 7736#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 7737#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 7738#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 7739#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 7740#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U 7741 7742/*Command word to command word programming delay*/ 7743#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 7744#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 7745#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 7746#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 7747#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 7748#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U 7749 7750/*Reserved. Return zeroes on reads.*/ 7751#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 7752#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 7753#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 7754#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 7755#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 7756#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U 7757 7758/*Command word to command word programming delay*/ 7759#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 7760#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 7761#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 7762#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 7763#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 7764#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U 7765 7766/*Reserved. Return zeroes on reads.*/ 7767#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 7768#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 7769#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 7770#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 7771#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 7772#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U 7773 7774/*Stabilization time*/ 7775#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 7776#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 7777#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 7778#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 7779#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 7780#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU 7781 7782/*DDR4/DDR3 Control Word 7*/ 7783#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL 7784#undef DDR_PHY_RDIMMCR0_RC7_SHIFT 7785#undef DDR_PHY_RDIMMCR0_RC7_MASK 7786#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 7787#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 7788#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U 7789 7790/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/ 7791#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL 7792#undef DDR_PHY_RDIMMCR0_RC6_SHIFT 7793#undef DDR_PHY_RDIMMCR0_RC6_MASK 7794#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 7795#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 7796#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U 7797 7798/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/ 7799#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL 7800#undef DDR_PHY_RDIMMCR0_RC5_SHIFT 7801#undef DDR_PHY_RDIMMCR0_RC5_MASK 7802#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 7803#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 7804#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U 7805 7806/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C 7807 aracteristics Control Word)*/ 7808#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL 7809#undef DDR_PHY_RDIMMCR0_RC4_SHIFT 7810#undef DDR_PHY_RDIMMCR0_RC4_MASK 7811#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 7812#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 7813#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U 7814 7815/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr 7816 ver Characteristrics Control Word)*/ 7817#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL 7818#undef DDR_PHY_RDIMMCR0_RC3_SHIFT 7819#undef DDR_PHY_RDIMMCR0_RC3_MASK 7820#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 7821#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 7822#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U 7823 7824/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/ 7825#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL 7826#undef DDR_PHY_RDIMMCR0_RC2_SHIFT 7827#undef DDR_PHY_RDIMMCR0_RC2_MASK 7828#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 7829#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 7830#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U 7831 7832/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/ 7833#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL 7834#undef DDR_PHY_RDIMMCR0_RC1_SHIFT 7835#undef DDR_PHY_RDIMMCR0_RC1_MASK 7836#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 7837#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 7838#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U 7839 7840/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/ 7841#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL 7842#undef DDR_PHY_RDIMMCR0_RC0_SHIFT 7843#undef DDR_PHY_RDIMMCR0_RC0_MASK 7844#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 7845#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 7846#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU 7847 7848/*Control Word 15*/ 7849#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 7850#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 7851#undef DDR_PHY_RDIMMCR1_RC15_MASK 7852#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 7853#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 7854#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U 7855 7856/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/ 7857#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 7858#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 7859#undef DDR_PHY_RDIMMCR1_RC14_MASK 7860#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 7861#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 7862#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U 7863 7864/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/ 7865#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 7866#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 7867#undef DDR_PHY_RDIMMCR1_RC13_MASK 7868#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 7869#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 7870#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U 7871 7872/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/ 7873#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 7874#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 7875#undef DDR_PHY_RDIMMCR1_RC12_MASK 7876#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 7877#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 7878#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U 7879 7880/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con 7881 rol Word)*/ 7882#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 7883#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 7884#undef DDR_PHY_RDIMMCR1_RC11_MASK 7885#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 7886#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 7887#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U 7888 7889/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/ 7890#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 7891#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 7892#undef DDR_PHY_RDIMMCR1_RC10_MASK 7893#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 7894#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 7895#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U 7896 7897/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/ 7898#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 7899#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 7900#undef DDR_PHY_RDIMMCR1_RC9_MASK 7901#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 7902#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 7903#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U 7904 7905/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting 7906 Control Word)*/ 7907#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 7908#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 7909#undef DDR_PHY_RDIMMCR1_RC8_MASK 7910#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 7911#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 7912#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU 7913 7914/*Reserved. Return zeroes on reads.*/ 7915#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 7916#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 7917#undef DDR_PHY_MR0_RESERVED_31_8_MASK 7918#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 7919#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 7920#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U 7921 7922/*CA Terminating Rank*/ 7923#undef DDR_PHY_MR0_CATR_DEFVAL 7924#undef DDR_PHY_MR0_CATR_SHIFT 7925#undef DDR_PHY_MR0_CATR_MASK 7926#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 7927#define DDR_PHY_MR0_CATR_SHIFT 7 7928#define DDR_PHY_MR0_CATR_MASK 0x00000080U 7929 7930/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 7931#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 7932#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 7933#undef DDR_PHY_MR0_RSVD_6_5_MASK 7934#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 7935#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 7936#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U 7937 7938/*Built-in Self-Test for RZQ*/ 7939#undef DDR_PHY_MR0_RZQI_DEFVAL 7940#undef DDR_PHY_MR0_RZQI_SHIFT 7941#undef DDR_PHY_MR0_RZQI_MASK 7942#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 7943#define DDR_PHY_MR0_RZQI_SHIFT 3 7944#define DDR_PHY_MR0_RZQI_MASK 0x00000018U 7945 7946/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 7947#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 7948#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 7949#undef DDR_PHY_MR0_RSVD_2_0_MASK 7950#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 7951#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 7952#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U 7953 7954/*Reserved. Return zeroes on reads.*/ 7955#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 7956#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 7957#undef DDR_PHY_MR1_RESERVED_31_8_MASK 7958#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 7959#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 7960#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U 7961 7962/*Read Postamble Length*/ 7963#undef DDR_PHY_MR1_RDPST_DEFVAL 7964#undef DDR_PHY_MR1_RDPST_SHIFT 7965#undef DDR_PHY_MR1_RDPST_MASK 7966#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 7967#define DDR_PHY_MR1_RDPST_SHIFT 7 7968#define DDR_PHY_MR1_RDPST_MASK 0x00000080U 7969 7970/*Write-recovery for auto-precharge command*/ 7971#undef DDR_PHY_MR1_NWR_DEFVAL 7972#undef DDR_PHY_MR1_NWR_SHIFT 7973#undef DDR_PHY_MR1_NWR_MASK 7974#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 7975#define DDR_PHY_MR1_NWR_SHIFT 4 7976#define DDR_PHY_MR1_NWR_MASK 0x00000070U 7977 7978/*Read Preamble Length*/ 7979#undef DDR_PHY_MR1_RDPRE_DEFVAL 7980#undef DDR_PHY_MR1_RDPRE_SHIFT 7981#undef DDR_PHY_MR1_RDPRE_MASK 7982#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 7983#define DDR_PHY_MR1_RDPRE_SHIFT 3 7984#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U 7985 7986/*Write Preamble Length*/ 7987#undef DDR_PHY_MR1_WRPRE_DEFVAL 7988#undef DDR_PHY_MR1_WRPRE_SHIFT 7989#undef DDR_PHY_MR1_WRPRE_MASK 7990#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 7991#define DDR_PHY_MR1_WRPRE_SHIFT 2 7992#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U 7993 7994/*Burst Length*/ 7995#undef DDR_PHY_MR1_BL_DEFVAL 7996#undef DDR_PHY_MR1_BL_SHIFT 7997#undef DDR_PHY_MR1_BL_MASK 7998#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 7999#define DDR_PHY_MR1_BL_SHIFT 0 8000#define DDR_PHY_MR1_BL_MASK 0x00000003U
8001 8002/*Reserved. Return zeroes on reads.*/ 8003#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 8004#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 8005#undef DDR_PHY_MR2_RESERVED_31_8_MASK 8006#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 8007#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 8008#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U 8009 8010/*Write Leveling*/ 8011#undef DDR_PHY_MR2_WRL_DEFVAL 8012#undef DDR_PHY_MR2_WRL_SHIFT 8013#undef DDR_PHY_MR2_WRL_MASK 8014#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 8015#define DDR_PHY_MR2_WRL_SHIFT 7 8016#define DDR_PHY_MR2_WRL_MASK 0x00000080U 8017 8018/*Write Latency Set*/ 8019#undef DDR_PHY_MR2_WLS_DEFVAL 8020#undef DDR_PHY_MR2_WLS_SHIFT 8021#undef DDR_PHY_MR2_WLS_MASK 8022#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 8023#define DDR_PHY_MR2_WLS_SHIFT 6 8024#define DDR_PHY_MR2_WLS_MASK 0x00000040U 8025 8026/*Write Latency*/ 8027#undef DDR_PHY_MR2_WL_DEFVAL 8028#undef DDR_PHY_MR2_WL_SHIFT 8029#undef DDR_PHY_MR2_WL_MASK 8030#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 8031#define DDR_PHY_MR2_WL_SHIFT 3 8032#define DDR_PHY_MR2_WL_MASK 0x00000038U 8033 8034/*Read Latency*/ 8035#undef DDR_PHY_MR2_RL_DEFVAL 8036#undef DDR_PHY_MR2_RL_SHIFT 8037#undef DDR_PHY_MR2_RL_MASK 8038#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 8039#define DDR_PHY_MR2_RL_SHIFT 0 8040#define DDR_PHY_MR2_RL_MASK 0x00000007U 8041 8042/*Reserved. Return zeroes on reads.*/ 8043#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 8044#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 8045#undef DDR_PHY_MR3_RESERVED_31_8_MASK 8046#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 8047#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 8048#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U 8049 8050/*DBI-Write Enable*/ 8051#undef DDR_PHY_MR3_DBIWR_DEFVAL 8052#undef DDR_PHY_MR3_DBIWR_SHIFT 8053#undef DDR_PHY_MR3_DBIWR_MASK 8054#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 8055#define DDR_PHY_MR3_DBIWR_SHIFT 7 8056#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U 8057 8058/*DBI-Read Enable*/ 8059#undef DDR_PHY_MR3_DBIRD_DEFVAL 8060#undef DDR_PHY_MR3_DBIRD_SHIFT 8061#undef DDR_PHY_MR3_DBIRD_MASK 8062#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 8063#define DDR_PHY_MR3_DBIRD_SHIFT 6 8064#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U 8065 8066/*Pull-down Drive Strength*/ 8067#undef DDR_PHY_MR3_PDDS_DEFVAL 8068#undef DDR_PHY_MR3_PDDS_SHIFT 8069#undef DDR_PHY_MR3_PDDS_MASK 8070#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 8071#define DDR_PHY_MR3_PDDS_SHIFT 3 8072#define DDR_PHY_MR3_PDDS_MASK 0x00000038U 8073 8074/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8075#undef DDR_PHY_MR3_RSVD_DEFVAL 8076#undef DDR_PHY_MR3_RSVD_SHIFT 8077#undef DDR_PHY_MR3_RSVD_MASK 8078#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 8079#define DDR_PHY_MR3_RSVD_SHIFT 2 8080#define DDR_PHY_MR3_RSVD_MASK 0x00000004U 8081 8082/*Write Postamble Length*/ 8083#undef DDR_PHY_MR3_WRPST_DEFVAL 8084#undef DDR_PHY_MR3_WRPST_SHIFT 8085#undef DDR_PHY_MR3_WRPST_MASK 8086#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 8087#define DDR_PHY_MR3_WRPST_SHIFT 1 8088#define DDR_PHY_MR3_WRPST_MASK 0x00000002U 8089 8090/*Pull-up Calibration Point*/ 8091#undef DDR_PHY_MR3_PUCAL_DEFVAL 8092#undef DDR_PHY_MR3_PUCAL_SHIFT 8093#undef DDR_PHY_MR3_PUCAL_MASK 8094#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 8095#define DDR_PHY_MR3_PUCAL_SHIFT 0 8096#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U 8097 8098/*Reserved. Return zeroes on reads.*/ 8099#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 8100#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 8101#undef DDR_PHY_MR4_RESERVED_31_16_MASK 8102#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 8103#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 8104#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U 8105 8106/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8107#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 8108#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 8109#undef DDR_PHY_MR4_RSVD_15_13_MASK 8110#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 8111#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 8112#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U 8113 8114/*Write Preamble*/ 8115#undef DDR_PHY_MR4_WRP_DEFVAL 8116#undef DDR_PHY_MR4_WRP_SHIFT 8117#undef DDR_PHY_MR4_WRP_MASK 8118#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 8119#define DDR_PHY_MR4_WRP_SHIFT 12 8120#define DDR_PHY_MR4_WRP_MASK 0x00001000U 8121 8122/*Read Preamble*/ 8123#undef DDR_PHY_MR4_RDP_DEFVAL 8124#undef DDR_PHY_MR4_RDP_SHIFT 8125#undef DDR_PHY_MR4_RDP_MASK 8126#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 8127#define DDR_PHY_MR4_RDP_SHIFT 11 8128#define DDR_PHY_MR4_RDP_MASK 0x00000800U 8129 8130/*Read Preamble Training Mode*/ 8131#undef DDR_PHY_MR4_RPTM_DEFVAL 8132#undef DDR_PHY_MR4_RPTM_SHIFT 8133#undef DDR_PHY_MR4_RPTM_MASK 8134#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 8135#define DDR_PHY_MR4_RPTM_SHIFT 10 8136#define DDR_PHY_MR4_RPTM_MASK 0x00000400U 8137 8138/*Self Refresh Abort*/ 8139#undef DDR_PHY_MR4_SRA_DEFVAL 8140#undef DDR_PHY_MR4_SRA_SHIFT 8141#undef DDR_PHY_MR4_SRA_MASK 8142#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 8143#define DDR_PHY_MR4_SRA_SHIFT 9 8144#define DDR_PHY_MR4_SRA_MASK 0x00000200U 8145 8146/*CS to Command Latency Mode*/ 8147#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 8148#undef DDR_PHY_MR4_CS2CMDL_SHIFT 8149#undef DDR_PHY_MR4_CS2CMDL_MASK 8150#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 8151#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 8152#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U 8153 8154/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8155#undef DDR_PHY_MR4_RSVD1_DEFVAL 8156#undef DDR_PHY_MR4_RSVD1_SHIFT 8157#undef DDR_PHY_MR4_RSVD1_MASK 8158#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 8159#define DDR_PHY_MR4_RSVD1_SHIFT 5 8160#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U 8161 8162/*Internal VREF Monitor*/ 8163#undef DDR_PHY_MR4_IVM_DEFVAL 8164#undef DDR_PHY_MR4_IVM_SHIFT 8165#undef DDR_PHY_MR4_IVM_MASK 8166#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 8167#define DDR_PHY_MR4_IVM_SHIFT 4 8168#define DDR_PHY_MR4_IVM_MASK 0x00000010U 8169 8170/*Temperature Controlled Refresh Mode*/ 8171#undef DDR_PHY_MR4_TCRM_DEFVAL 8172#undef DDR_PHY_MR4_TCRM_SHIFT 8173#undef DDR_PHY_MR4_TCRM_MASK 8174#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 8175#define DDR_PHY_MR4_TCRM_SHIFT 3 8176#define DDR_PHY_MR4_TCRM_MASK 0x00000008U 8177 8178/*Temperature Controlled Refresh Range*/ 8179#undef DDR_PHY_MR4_TCRR_DEFVAL 8180#undef DDR_PHY_MR4_TCRR_SHIFT 8181#undef DDR_PHY_MR4_TCRR_MASK 8182#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 8183#define DDR_PHY_MR4_TCRR_SHIFT 2 8184#define DDR_PHY_MR4_TCRR_MASK 0x00000004U 8185 8186/*Maximum Power Down Mode*/ 8187#undef DDR_PHY_MR4_MPDM_DEFVAL 8188#undef DDR_PHY_MR4_MPDM_SHIFT 8189#undef DDR_PHY_MR4_MPDM_MASK 8190#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 8191#define DDR_PHY_MR4_MPDM_SHIFT 1 8192#define DDR_PHY_MR4_MPDM_MASK 0x00000002U 8193 8194/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/ 8195#undef DDR_PHY_MR4_RSVD_0_DEFVAL 8196#undef DDR_PHY_MR4_RSVD_0_SHIFT 8197#undef DDR_PHY_MR4_RSVD_0_MASK 8198#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 8199#define DDR_PHY_MR4_RSVD_0_SHIFT 0 8200#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U 8201 8202/*Reserved. Return zeroes on reads.*/ 8203#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 8204#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 8205#undef DDR_PHY_MR5_RESERVED_31_16_MASK 8206#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 8207#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 8208#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U 8209 8210/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8211#undef DDR_PHY_MR5_RSVD_DEFVAL 8212#undef DDR_PHY_MR5_RSVD_SHIFT 8213#undef DDR_PHY_MR5_RSVD_MASK 8214#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 8215#define DDR_PHY_MR5_RSVD_SHIFT 13 8216#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U 8217 8218/*Read DBI*/ 8219#undef DDR_PHY_MR5_RDBI_DEFVAL 8220#undef DDR_PHY_MR5_RDBI_SHIFT 8221#undef DDR_PHY_MR5_RDBI_MASK 8222#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 8223#define DDR_PHY_MR5_RDBI_SHIFT 12 8224#define DDR_PHY_MR5_RDBI_MASK 0x00001000U 8225 8226/*Write DBI*/ 8227#undef DDR_PHY_MR5_WDBI_DEFVAL 8228#undef DDR_PHY_MR5_WDBI_SHIFT 8229#undef DDR_PHY_MR5_WDBI_MASK 8230#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 8231#define DDR_PHY_MR5_WDBI_SHIFT 11 8232#define DDR_PHY_MR5_WDBI_MASK 0x00000800U 8233 8234/*Data Mask*/ 8235#undef DDR_PHY_MR5_DM_DEFVAL 8236#undef DDR_PHY_MR5_DM_SHIFT 8237#undef DDR_PHY_MR5_DM_MASK 8238#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 8239#define DDR_PHY_MR5_DM_SHIFT 10 8240#define DDR_PHY_MR5_DM_MASK 0x00000400U 8241 8242/*CA Parity Persistent Error*/ 8243#undef DDR_PHY_MR5_CAPPE_DEFVAL 8244#undef DDR_PHY_MR5_CAPPE_SHIFT 8245#undef DDR_PHY_MR5_CAPPE_MASK 8246#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 8247#define DDR_PHY_MR5_CAPPE_SHIFT 9 8248#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U 8249 8250/*RTT_PARK*/ 8251#undef DDR_PHY_MR5_RTTPARK_DEFVAL 8252#undef DDR_PHY_MR5_RTTPARK_SHIFT 8253#undef DDR_PHY_MR5_RTTPARK_MASK 8254#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 8255#define DDR_PHY_MR5_RTTPARK_SHIFT 6 8256#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U 8257 8258/*ODT Input Buffer during Power Down mode*/ 8259#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 8260#undef DDR_PHY_MR5_ODTIBPD_SHIFT 8261#undef DDR_PHY_MR5_ODTIBPD_MASK 8262#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 8263#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 8264#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U 8265 8266/*C/A Parity Error Status*/ 8267#undef DDR_PHY_MR5_CAPES_DEFVAL 8268#undef DDR_PHY_MR5_CAPES_SHIFT 8269#undef DDR_PHY_MR5_CAPES_MASK 8270#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 8271#define DDR_PHY_MR5_CAPES_SHIFT 4 8272#define DDR_PHY_MR5_CAPES_MASK 0x00000010U 8273 8274/*CRC Error Clear*/ 8275#undef DDR_PHY_MR5_CRCEC_DEFVAL 8276#undef DDR_PHY_MR5_CRCEC_SHIFT 8277#undef DDR_PHY_MR5_CRCEC_MASK 8278#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 8279#define DDR_PHY_MR5_CRCEC_SHIFT 3 8280#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U 8281 8282/*C/A Parity Latency Mode*/ 8283#undef DDR_PHY_MR5_CAPM_DEFVAL 8284#undef DDR_PHY_MR5_CAPM_SHIFT 8285#undef DDR_PHY_MR5_CAPM_MASK 8286#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 8287#define DDR_PHY_MR5_CAPM_SHIFT 0 8288#define DDR_PHY_MR5_CAPM_MASK 0x00000007U 8289 8290/*Reserved. Return zeroes on reads.*/ 8291#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 8292#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 8293#undef DDR_PHY_MR6_RESERVED_31_16_MASK 8294#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 8295#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 8296#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U 8297 8298/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8299#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 8300#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 8301#undef DDR_PHY_MR6_RSVD_15_13_MASK 8302#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 8303#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 8304#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U 8305 8306/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/ 8307#undef DDR_PHY_MR6_TCCDL_DEFVAL 8308#undef DDR_PHY_MR6_TCCDL_SHIFT 8309#undef DDR_PHY_MR6_TCCDL_MASK 8310#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 8311#define DDR_PHY_MR6_TCCDL_SHIFT 10 8312#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U 8313 8314/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8315#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 8316#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 8317#undef DDR_PHY_MR6_RSVD_9_8_MASK 8318#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 8319#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 8320#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U 8321 8322/*VrefDQ Training Enable*/ 8323#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 8324#undef DDR_PHY_MR6_VDDQTEN_SHIFT 8325#undef DDR_PHY_MR6_VDDQTEN_MASK 8326#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 8327#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 8328#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U 8329 8330/*VrefDQ Training Range*/ 8331#undef DDR_PHY_MR6_VDQTRG_DEFVAL 8332#undef DDR_PHY_MR6_VDQTRG_SHIFT 8333#undef DDR_PHY_MR6_VDQTRG_MASK 8334#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 8335#define DDR_PHY_MR6_VDQTRG_SHIFT 6 8336#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U 8337 8338/*VrefDQ Training Values*/ 8339#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 8340#undef DDR_PHY_MR6_VDQTVAL_SHIFT 8341#undef DDR_PHY_MR6_VDQTVAL_MASK 8342#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 8343#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 8344#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU 8345 8346/*Reserved. Return zeroes on reads.*/ 8347#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 8348#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 8349#undef DDR_PHY_MR11_RESERVED_31_8_MASK 8350#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 8351#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 8352#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U 8353 8354/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8355#undef DDR_PHY_MR11_RSVD_DEFVAL 8356#undef DDR_PHY_MR11_RSVD_SHIFT 8357#undef DDR_PHY_MR11_RSVD_MASK 8358#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 8359#define DDR_PHY_MR11_RSVD_SHIFT 3 8360#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U 8361 8362/*Power Down Control*/ 8363#undef DDR_PHY_MR11_PDCTL_DEFVAL 8364#undef DDR_PHY_MR11_PDCTL_SHIFT 8365#undef DDR_PHY_MR11_PDCTL_MASK 8366#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 8367#define DDR_PHY_MR11_PDCTL_SHIFT 2 8368#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U 8369 8370/*DQ Bus Receiver On-Die-Termination*/ 8371#undef DDR_PHY_MR11_DQODT_DEFVAL 8372#undef DDR_PHY_MR11_DQODT_SHIFT 8373#undef DDR_PHY_MR11_DQODT_MASK 8374#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 8375#define DDR_PHY_MR11_DQODT_SHIFT 0 8376#define DDR_PHY_MR11_DQODT_MASK 0x00000003U 8377 8378/*Reserved. Return zeroes on reads.*/ 8379#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 8380#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 8381#undef DDR_PHY_MR12_RESERVED_31_8_MASK 8382#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D 8383#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 8384#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U 8385 8386/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8387#undef DDR_PHY_MR12_RSVD_DEFVAL 8388#undef DDR_PHY_MR12_RSVD_SHIFT 8389#undef DDR_PHY_MR12_RSVD_MASK 8390#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D 8391#define DDR_PHY_MR12_RSVD_SHIFT 7 8392#define DDR_PHY_MR12_RSVD_MASK 0x00000080U 8393 8394/*VREF_CA Range Select.*/ 8395#undef DDR_PHY_MR12_VR_CA_DEFVAL 8396#undef DDR_PHY_MR12_VR_CA_SHIFT 8397#undef DDR_PHY_MR12_VR_CA_MASK 8398#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D 8399#define DDR_PHY_MR12_VR_CA_SHIFT 6 8400#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U 8401 8402/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/ 8403#undef DDR_PHY_MR12_VREF_CA_DEFVAL 8404#undef DDR_PHY_MR12_VREF_CA_SHIFT 8405#undef DDR_PHY_MR12_VREF_CA_MASK 8406#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D 8407#define DDR_PHY_MR12_VREF_CA_SHIFT 0 8408#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU 8409 8410/*Reserved. Return zeroes on reads.*/ 8411#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 8412#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 8413#undef DDR_PHY_MR13_RESERVED_31_8_MASK 8414#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 8415#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 8416#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U 8417 8418/*Frequency Set Point Operation Mode*/ 8419#undef DDR_PHY_MR13_FSPOP_DEFVAL 8420#undef DDR_PHY_MR13_FSPOP_SHIFT 8421#undef DDR_PHY_MR13_FSPOP_MASK 8422#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 8423#define DDR_PHY_MR13_FSPOP_SHIFT 7 8424#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U 8425 8426/*Frequency Set Point Write Enable*/ 8427#undef DDR_PHY_MR13_FSPWR_DEFVAL 8428#undef DDR_PHY_MR13_FSPWR_SHIFT 8429#undef DDR_PHY_MR13_FSPWR_MASK 8430#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 8431#define DDR_PHY_MR13_FSPWR_SHIFT 6 8432#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U 8433 8434/*Data Mask Enable*/ 8435#undef DDR_PHY_MR13_DMD_DEFVAL 8436#undef DDR_PHY_MR13_DMD_SHIFT 8437#undef DDR_PHY_MR13_DMD_MASK 8438#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 8439#define DDR_PHY_MR13_DMD_SHIFT 5 8440#define DDR_PHY_MR13_DMD_MASK 0x00000020U 8441 8442/*Refresh Rate Option*/ 8443#undef DDR_PHY_MR13_RRO_DEFVAL 8444#undef DDR_PHY_MR13_RRO_SHIFT 8445#undef DDR_PHY_MR13_RRO_MASK 8446#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 8447#define DDR_PHY_MR13_RRO_SHIFT 4 8448#define DDR_PHY_MR13_RRO_MASK 0x00000010U 8449 8450/*VREF Current Generator*/ 8451#undef DDR_PHY_MR13_VRCG_DEFVAL 8452#undef DDR_PHY_MR13_VRCG_SHIFT 8453#undef DDR_PHY_MR13_VRCG_MASK 8454#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 8455#define DDR_PHY_MR13_VRCG_SHIFT 3 8456#define DDR_PHY_MR13_VRCG_MASK 0x00000008U 8457 8458/*VREF Output*/ 8459#undef DDR_PHY_MR13_VRO_DEFVAL 8460#undef DDR_PHY_MR13_VRO_SHIFT 8461#undef DDR_PHY_MR13_VRO_MASK 8462#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 8463#define DDR_PHY_MR13_VRO_SHIFT 2 8464#define DDR_PHY_MR13_VRO_MASK 0x00000004U 8465 8466/*Read Preamble Training Mode*/ 8467#undef DDR_PHY_MR13_RPT_DEFVAL 8468#undef DDR_PHY_MR13_RPT_SHIFT 8469#undef DDR_PHY_MR13_RPT_MASK 8470#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 8471#define DDR_PHY_MR13_RPT_SHIFT 1 8472#define DDR_PHY_MR13_RPT_MASK 0x00000002U 8473 8474/*Command Bus Training*/ 8475#undef DDR_PHY_MR13_CBT_DEFVAL 8476#undef DDR_PHY_MR13_CBT_SHIFT 8477#undef DDR_PHY_MR13_CBT_MASK 8478#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 8479#define DDR_PHY_MR13_CBT_SHIFT 0 8480#define DDR_PHY_MR13_CBT_MASK 0x00000001U 8481 8482/*Reserved. Return zeroes on reads.*/ 8483#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 8484#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 8485#undef DDR_PHY_MR14_RESERVED_31_8_MASK 8486#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D 8487#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 8488#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U 8489 8490/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8491#undef DDR_PHY_MR14_RSVD_DEFVAL 8492#undef DDR_PHY_MR14_RSVD_SHIFT 8493#undef DDR_PHY_MR14_RSVD_MASK 8494#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D 8495#define DDR_PHY_MR14_RSVD_SHIFT 7 8496#define DDR_PHY_MR14_RSVD_MASK 0x00000080U 8497 8498/*VREFDQ Range Selects.*/ 8499#undef DDR_PHY_MR14_VR_DQ_DEFVAL 8500#undef DDR_PHY_MR14_VR_DQ_SHIFT 8501#undef DDR_PHY_MR14_VR_DQ_MASK 8502#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D 8503#define DDR_PHY_MR14_VR_DQ_SHIFT 6 8504#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U 8505 8506/*Reserved. Return zeroes on reads.*/ 8507#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 8508#undef DDR_PHY_MR14_VREF_DQ_SHIFT 8509#undef DDR_PHY_MR14_VREF_DQ_MASK 8510#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D 8511#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 8512#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU 8513 8514/*Reserved. Return zeroes on reads.*/ 8515#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 8516#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 8517#undef DDR_PHY_MR22_RESERVED_31_8_MASK 8518#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 8519#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 8520#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U 8521 8522/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ 8523#undef DDR_PHY_MR22_RSVD_DEFVAL 8524#undef DDR_PHY_MR22_RSVD_SHIFT 8525#undef DDR_PHY_MR22_RSVD_MASK 8526#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 8527#define DDR_PHY_MR22_RSVD_SHIFT 6 8528#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U 8529 8530/*CA ODT termination disable.*/ 8531#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 8532#undef DDR_PHY_MR22_ODTD_CA_SHIFT 8533#undef DDR_PHY_MR22_ODTD_CA_MASK 8534#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 8535#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 8536#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U 8537 8538/*ODT CS override.*/ 8539#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 8540#undef DDR_PHY_MR22_ODTE_CS_SHIFT 8541#undef DDR_PHY_MR22_ODTE_CS_MASK 8542#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 8543#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 8544#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U 8545 8546/*ODT CK override.*/ 8547#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 8548#undef DDR_PHY_MR22_ODTE_CK_SHIFT 8549#undef DDR_PHY_MR22_ODTE_CK_MASK 8550#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 8551#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 8552#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U 8553 8554/*Controller ODT value for VOH calibration.*/ 8555#undef DDR_PHY_MR22_CODT_DEFVAL 8556#undef DDR_PHY_MR22_CODT_SHIFT 8557#undef DDR_PHY_MR22_CODT_MASK 8558#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 8559#define DDR_PHY_MR22_CODT_SHIFT 0 8560#define DDR_PHY_MR22_CODT_MASK 0x00000007U 8561 8562/*Refresh During Training*/ 8563#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 8564#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 8565#undef DDR_PHY_DTCR0_RFSHDT_MASK 8566#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 8567#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 8568#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U 8569 8570/*Reserved. Return zeroes on reads.*/ 8571#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 8572#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 8573#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 8574#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 8575#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 8576#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U 8577 8578/*Data Training Debug Rank Select*/ 8579#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 8580#undef DDR_PHY_DTCR0_DTDRS_SHIFT 8581#undef DDR_PHY_DTCR0_DTDRS_MASK 8582#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 8583#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 8584#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U 8585 8586/*Data Training with Early/Extended Gate*/ 8587#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 8588#undef DDR_PHY_DTCR0_DTEXG_SHIFT 8589#undef DDR_PHY_DTCR0_DTEXG_MASK 8590#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 8591#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 8592#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U 8593 8594/*Data Training Extended Write DQS*/ 8595#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 8596#undef DDR_PHY_DTCR0_DTEXD_SHIFT 8597#undef DDR_PHY_DTCR0_DTEXD_MASK 8598#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 8599#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 8600#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U 8601 8602/*Data Training Debug Step*/ 8603#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 8604#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 8605#undef DDR_PHY_DTCR0_DTDSTP_MASK 8606#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 8607#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 8608#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U 8609 8610/*Data Training Debug Enable*/ 8611#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 8612#undef DDR_PHY_DTCR0_DTDEN_SHIFT 8613#undef DDR_PHY_DTCR0_DTDEN_MASK 8614#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 8615#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 8616#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U 8617 8618/*Data Training Debug Byte Select*/ 8619#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 8620#undef DDR_PHY_DTCR0_DTDBS_SHIFT 8621#undef DDR_PHY_DTCR0_DTDBS_MASK 8622#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 8623#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 8624#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U 8625 8626/*Data Training read DBI deskewing configuration*/ 8627#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 8628#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 8629#undef DDR_PHY_DTCR0_DTRDBITR_MASK 8630#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 8631#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 8632#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U 8633 8634/*Reserved. Return zeroes on reads.*/ 8635#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 8636#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 8637#undef DDR_PHY_DTCR0_RESERVED_13_MASK 8638#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 8639#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 8640#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U 8641 8642/*Data Training Write Bit Deskew Data Mask*/ 8643#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 8644#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 8645#undef DDR_PHY_DTCR0_DTWBDDM_MASK 8646#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 8647#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 8648#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U 8649 8650/*Refreshes Issued During Entry to Training*/ 8651#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 8652#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 8653#undef DDR_PHY_DTCR0_RFSHEN_MASK 8654#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 8655#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 8656#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U 8657 8658/*Data Training Compare Data*/ 8659#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 8660#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 8661#undef DDR_PHY_DTCR0_DTCMPD_MASK 8662#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 8663#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 8664#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U 8665 8666/*Data Training Using MPR*/ 8667#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 8668#undef DDR_PHY_DTCR0_DTMPR_SHIFT 8669#undef DDR_PHY_DTCR0_DTMPR_MASK 8670#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 8671#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 8672#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U 8673 8674/*Reserved. Return zeroes on reads.*/ 8675#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 8676#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 8677#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 8678#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 8679#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 8680#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U 8681 8682/*Data Training Repeat Number*/ 8683#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 8684#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 8685#undef DDR_PHY_DTCR0_DTRPTN_MASK 8686#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 8687#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 8688#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU 8689 8690/*Rank Enable.*/ 8691#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 8692#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 8693#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 8694#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 8695#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 8696#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U 8697 8698/*Rank Enable.*/ 8699#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 8700#undef DDR_PHY_DTCR1_RANKEN_SHIFT 8701#undef DDR_PHY_DTCR1_RANKEN_MASK 8702#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 8703#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 8704#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U 8705 8706/*Reserved. Return zeroes on reads.*/ 8707#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 8708#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 8709#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 8710#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 8711#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 8712#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U 8713 8714/*Data Training Rank*/ 8715#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 8716#undef DDR_PHY_DTCR1_DTRANK_SHIFT 8717#undef DDR_PHY_DTCR1_DTRANK_MASK 8718#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 8719#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 8720#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U 8721 8722/*Reserved. Return zeroes on reads.*/ 8723#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 8724#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 8725#undef DDR_PHY_DTCR1_RESERVED_11_MASK 8726#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 8727#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 8728#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U 8729 8730/*Read Leveling Gate Sampling Difference*/ 8731#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 8732#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8733#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 8734#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 8735#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 8736#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U 8737 8738/*Reserved. Return zeroes on reads.*/ 8739#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 8740#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 8741#undef DDR_PHY_DTCR1_RESERVED_7_MASK 8742#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 8743#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 8744#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U 8745 8746/*Read Leveling Gate Shift*/ 8747#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 8748#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 8749#undef DDR_PHY_DTCR1_RDLVLGS_MASK 8750#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 8751#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 8752#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U 8753 8754/*Reserved. Return zeroes on reads.*/ 8755#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 8756#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 8757#undef DDR_PHY_DTCR1_RESERVED_3_MASK 8758#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 8759#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 8760#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U 8761 8762/*Read Preamble Training enable*/ 8763#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 8764#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 8765#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 8766#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 8767#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 8768#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U 8769 8770/*Read Leveling Enable*/ 8771#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 8772#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 8773#undef DDR_PHY_DTCR1_RDLVLEN_MASK 8774#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 8775#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 8776#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U 8777 8778/*Basic Gate Training Enable*/ 8779#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 8780#undef DDR_PHY_DTCR1_BSTEN_SHIFT 8781#undef DDR_PHY_DTCR1_BSTEN_MASK 8782#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 8783#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 8784#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U 8785 8786/*Reserved. Return zeroes on reads.*/ 8787#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 8788#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 8789#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 8790#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 8791#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 8792#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U 8793 8794/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/ 8795#undef DDR_PHY_CATR0_CACD_DEFVAL 8796#undef DDR_PHY_CATR0_CACD_SHIFT 8797#undef DDR_PHY_CATR0_CACD_MASK 8798#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 8799#define DDR_PHY_CATR0_CACD_SHIFT 16 8800#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U 8801 8802/*Reserved. Return zeroes on reads.*/ 8803#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 8804#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 8805#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 8806#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 8807#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 8808#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U 8809 8810/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha 8811 been sent to the memory*/ 8812#undef DDR_PHY_CATR0_CAADR_DEFVAL 8813#undef DDR_PHY_CATR0_CAADR_SHIFT 8814#undef DDR_PHY_CATR0_CAADR_MASK 8815#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 8816#define DDR_PHY_CATR0_CAADR_SHIFT 8 8817#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U 8818 8819/*CA_1 Response Byte Lane 1*/ 8820#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 8821#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 8822#undef DDR_PHY_CATR0_CA1BYTE1_MASK 8823#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 8824#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 8825#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U 8826 8827/*CA_1 Response Byte Lane 0*/ 8828#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 8829#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 8830#undef DDR_PHY_CATR0_CA1BYTE0_MASK 8831#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 8832#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 8833#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU 8834 8835/*Reserved. Return zeroes on reads.*/ 8836#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 8837#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 8838#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 8839#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 8840#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 8841#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U 8842 8843/*Reserved. Return zeros on reads.*/ 8844#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 8845#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 8846#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 8847#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 8848#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 8849#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U 8850 8851/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/ 8852#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 8853#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 8854#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 8855#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 8856#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 8857#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU 8858 8859/*Address/Command Slew Rate (D3F I/O Only)*/ 8860#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 8861#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 8862#undef DDR_PHY_ACIOCR0_ACSR_MASK 8863#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 8864#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 8865#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U 8866 8867/*SDRAM Reset I/O Mode*/ 8868#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 8869#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 8870#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 8871#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 8872#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 8873#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U 8874 8875/*SDRAM Reset Power Down Receiver*/ 8876#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 8877#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 8878#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 8879#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 8880#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 8881#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U 8882 8883/*Reserved. Return zeroes on reads.*/ 8884#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 8885#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 8886#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 8887#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 8888#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 8889#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U 8890 8891/*SDRAM Reset On-Die Termination*/ 8892#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 8893#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 8894#undef DDR_PHY_ACIOCR0_RSTODT_MASK 8895#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 8896#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 8897#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U 8898 8899/*Reserved. Return zeroes on reads.*/ 8900#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 8901#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 8902#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 8903#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 8904#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 8905#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U 8906 8907/*CK Duty Cycle Correction*/ 8908#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 8909#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 8910#undef DDR_PHY_ACIOCR0_CKDCC_MASK 8911#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 8912#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 8913#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U 8914 8915/*AC Power Down Receiver Mode*/ 8916#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 8917#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 8918#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 8919#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 8920#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 8921#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U 8922 8923/*AC On-die Termination Mode*/ 8924#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 8925#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 8926#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 8927#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 8928#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 8929#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU 8930 8931/*Reserved. Return zeroes on reads.*/ 8932#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 8933#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 8934#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 8935#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 8936#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 8937#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U 8938 8939/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/ 8940#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 8941#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 8942#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 8943#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 8944#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 8945#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U 8946 8947/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/ 8948#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 8949#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 8950#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 8951#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 8952#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 8953#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U 8954 8955/*Clock gating for Output Enable D slices [0]*/ 8956#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 8957#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 8958#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 8959#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 8960#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 8961#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U 8962 8963/*Clock gating for Power Down Receiver D slices [0]*/ 8964#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 8965#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 8966#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 8967#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 8968#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 8969#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U 8970 8971/*Clock gating for Termination Enable D slices [0]*/ 8972#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 8973#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 8974#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 8975#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 8976#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 8977#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U 8978 8979/*Clock gating for CK# D slices [1:0]*/ 8980#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 8981#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 8982#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 8983#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 8984#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 8985#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U 8986 8987/*Clock gating for CK D slices [1:0]*/ 8988#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 8989#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 8990#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 8991#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 8992#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 8993#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U 8994 8995/*Clock gating for AC D slices [23:0]*/ 8996#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 8997#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 8998#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 8999#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 9000#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0
9001#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU 9002 9003/*SDRAM Parity Output Enable (OE) Mode Selection*/ 9004#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 9005#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 9006#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 9007#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 9008#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 9009#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U 9010 9011/*SDRAM Bank Group Output Enable (OE) Mode Selection*/ 9012#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 9013#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 9014#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 9015#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 9016#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 9017#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U 9018 9019/*SDRAM Bank Address Output Enable (OE) Mode Selection*/ 9020#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 9021#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 9022#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 9023#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 9024#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 9025#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U 9026 9027/*SDRAM A[17] Output Enable (OE) Mode Selection*/ 9028#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 9029#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 9030#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 9031#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 9032#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 9033#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U 9034 9035/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/ 9036#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 9037#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 9038#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 9039#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 9040#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 9041#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U 9042 9043/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/ 9044#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 9045#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 9046#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 9047#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 9048#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 9049#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U 9050 9051/*Reserved. Return zeroes on reads.*/ 9052#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 9053#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 9054#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 9055#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 9056#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 9057#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U 9058 9059/*Reserved. Return zeros on reads.*/ 9060#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 9061#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 9062#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 9063#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 9064#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 9065#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U 9066 9067/*SDRAM CK Output Enable (OE) Mode Selection.*/ 9068#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 9069#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 9070#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 9071#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 9072#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 9073#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU 9074 9075/*Clock gating for AC LB slices and loopback read valid slices*/ 9076#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 9077#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 9078#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 9079#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 9080#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 9081#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U 9082 9083/*Clock gating for Output Enable D slices [1]*/ 9084#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 9085#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 9086#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 9087#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 9088#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 9089#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U 9090 9091/*Clock gating for Power Down Receiver D slices [1]*/ 9092#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 9093#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 9094#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 9095#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 9096#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 9097#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U 9098 9099/*Clock gating for Termination Enable D slices [1]*/ 9100#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 9101#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 9102#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 9103#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 9104#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 9105#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U 9106 9107/*Clock gating for CK# D slices [3:2]*/ 9108#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 9109#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 9110#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 9111#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 9112#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 9113#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U 9114 9115/*Clock gating for CK D slices [3:2]*/ 9116#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 9117#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 9118#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 9119#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 9120#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 9121#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U 9122 9123/*Clock gating for AC D slices [47:24]*/ 9124#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 9125#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 9126#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 9127#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 9128#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 9129#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU 9130 9131/*Reserved. Return zeroes on reads.*/ 9132#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 9133#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 9134#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 9135#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 9136#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 9137#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U 9138 9139/*Address/command lane VREF Pad Enable*/ 9140#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 9141#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 9142#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 9143#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 9144#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 9145#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U 9146 9147/*Address/command lane Internal VREF Enable*/ 9148#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 9149#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 9150#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 9151#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 9152#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 9153#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U 9154 9155/*Address/command lane Single-End VREF Enable*/ 9156#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 9157#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 9158#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 9159#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 9160#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 9161#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U 9162 9163/*Address/command lane Internal VREF Enable*/ 9164#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 9165#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 9166#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 9167#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 9168#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 9169#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U 9170 9171/*External VREF generato REFSEL range select*/ 9172#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 9173#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 9174#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 9175#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 9176#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 9177#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U 9178 9179/*Address/command lane External VREF Select*/ 9180#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 9181#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 9182#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 9183#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 9184#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 9185#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U 9186 9187/*Single ended VREF generator REFSEL range select*/ 9188#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 9189#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 9190#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 9191#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 9192#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 9193#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U 9194 9195/*Address/command lane Single-End VREF Select*/ 9196#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 9197#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 9198#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 9199#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 9200#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 9201#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U 9202 9203/*Internal VREF generator REFSEL ragne select*/ 9204#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 9205#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 9206#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 9207#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 9208#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 9209#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U 9210 9211/*REFSEL Control for internal AC IOs*/ 9212#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 9213#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 9214#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 9215#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 9216#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 9217#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU 9218 9219/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/ 9220#undef DDR_PHY_VTCR0_TVREF_DEFVAL 9221#undef DDR_PHY_VTCR0_TVREF_SHIFT 9222#undef DDR_PHY_VTCR0_TVREF_MASK 9223#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 9224#define DDR_PHY_VTCR0_TVREF_SHIFT 29 9225#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U 9226 9227/*DRM DQ VREF training Enable*/ 9228#undef DDR_PHY_VTCR0_DVEN_DEFVAL 9229#undef DDR_PHY_VTCR0_DVEN_SHIFT 9230#undef DDR_PHY_VTCR0_DVEN_MASK 9231#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 9232#define DDR_PHY_VTCR0_DVEN_SHIFT 28 9233#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U 9234 9235/*Per Device Addressability Enable*/ 9236#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 9237#undef DDR_PHY_VTCR0_PDAEN_SHIFT 9238#undef DDR_PHY_VTCR0_PDAEN_MASK 9239#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 9240#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 9241#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U 9242 9243/*Reserved. Returns zeroes on reads.*/ 9244#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 9245#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 9246#undef DDR_PHY_VTCR0_RESERVED_26_MASK 9247#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 9248#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 9249#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U 9250 9251/*VREF Word Count*/ 9252#undef DDR_PHY_VTCR0_VWCR_DEFVAL 9253#undef DDR_PHY_VTCR0_VWCR_SHIFT 9254#undef DDR_PHY_VTCR0_VWCR_MASK 9255#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 9256#define DDR_PHY_VTCR0_VWCR_SHIFT 22 9257#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U 9258 9259/*DRAM DQ VREF step size used during DRAM VREF training*/ 9260#undef DDR_PHY_VTCR0_DVSS_DEFVAL 9261#undef DDR_PHY_VTCR0_DVSS_SHIFT 9262#undef DDR_PHY_VTCR0_DVSS_MASK 9263#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 9264#define DDR_PHY_VTCR0_DVSS_SHIFT 18 9265#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U 9266 9267/*Maximum VREF limit value used during DRAM VREF training*/ 9268#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 9269#undef DDR_PHY_VTCR0_DVMAX_SHIFT 9270#undef DDR_PHY_VTCR0_DVMAX_MASK 9271#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 9272#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 9273#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U 9274 9275/*Minimum VREF limit value used during DRAM VREF training*/ 9276#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 9277#undef DDR_PHY_VTCR0_DVMIN_SHIFT 9278#undef DDR_PHY_VTCR0_DVMIN_MASK 9279#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 9280#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 9281#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U 9282 9283/*Initial DRAM DQ VREF value used during DRAM VREF training*/ 9284#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 9285#undef DDR_PHY_VTCR0_DVINIT_SHIFT 9286#undef DDR_PHY_VTCR0_DVINIT_MASK 9287#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 9288#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 9289#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU 9290 9291/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/ 9292#undef DDR_PHY_VTCR1_HVSS_DEFVAL 9293#undef DDR_PHY_VTCR1_HVSS_SHIFT 9294#undef DDR_PHY_VTCR1_HVSS_MASK 9295#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 9296#define DDR_PHY_VTCR1_HVSS_SHIFT 28 9297#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U 9298 9299/*Reserved. Returns zeroes on reads.*/ 9300#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 9301#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 9302#undef DDR_PHY_VTCR1_RESERVED_27_MASK 9303#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 9304#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 9305#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U 9306 9307/*Maximum VREF limit value used during DRAM VREF training.*/ 9308#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 9309#undef DDR_PHY_VTCR1_HVMAX_SHIFT 9310#undef DDR_PHY_VTCR1_HVMAX_MASK 9311#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 9312#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 9313#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U 9314 9315/*Reserved. Returns zeroes on reads.*/ 9316#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 9317#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 9318#undef DDR_PHY_VTCR1_RESERVED_19_MASK 9319#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 9320#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 9321#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U 9322 9323/*Minimum VREF limit value used during DRAM VREF training.*/ 9324#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 9325#undef DDR_PHY_VTCR1_HVMIN_SHIFT 9326#undef DDR_PHY_VTCR1_HVMIN_MASK 9327#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 9328#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 9329#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U 9330 9331/*Reserved. Returns zeroes on reads.*/ 9332#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 9333#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 9334#undef DDR_PHY_VTCR1_RESERVED_11_MASK 9335#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 9336#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 9337#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U 9338 9339/*Static Host Vref Rank Value*/ 9340#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 9341#undef DDR_PHY_VTCR1_SHRNK_SHIFT 9342#undef DDR_PHY_VTCR1_SHRNK_MASK 9343#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 9344#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 9345#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U 9346 9347/*Static Host Vref Rank Enable*/ 9348#undef DDR_PHY_VTCR1_SHREN_DEFVAL 9349#undef DDR_PHY_VTCR1_SHREN_SHIFT 9350#undef DDR_PHY_VTCR1_SHREN_MASK 9351#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 9352#define DDR_PHY_VTCR1_SHREN_SHIFT 8 9353#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U 9354 9355/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/ 9356#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 9357#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 9358#undef DDR_PHY_VTCR1_TVREFIO_MASK 9359#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 9360#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 9361#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U 9362 9363/*Eye LCDL Offset value for VREF training*/ 9364#undef DDR_PHY_VTCR1_EOFF_DEFVAL 9365#undef DDR_PHY_VTCR1_EOFF_SHIFT 9366#undef DDR_PHY_VTCR1_EOFF_MASK 9367#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 9368#define DDR_PHY_VTCR1_EOFF_SHIFT 3 9369#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U 9370 9371/*Number of LCDL Eye points for which VREF training is repeated*/ 9372#undef DDR_PHY_VTCR1_ENUM_DEFVAL 9373#undef DDR_PHY_VTCR1_ENUM_SHIFT 9374#undef DDR_PHY_VTCR1_ENUM_MASK 9375#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 9376#define DDR_PHY_VTCR1_ENUM_SHIFT 2 9377#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U 9378 9379/*HOST (IO) internal VREF training Enable*/ 9380#undef DDR_PHY_VTCR1_HVEN_DEFVAL 9381#undef DDR_PHY_VTCR1_HVEN_SHIFT 9382#undef DDR_PHY_VTCR1_HVEN_MASK 9383#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 9384#define DDR_PHY_VTCR1_HVEN_SHIFT 1 9385#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U 9386 9387/*Host IO Type Control*/ 9388#undef DDR_PHY_VTCR1_HVIO_DEFVAL 9389#undef DDR_PHY_VTCR1_HVIO_SHIFT 9390#undef DDR_PHY_VTCR1_HVIO_MASK 9391#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 9392#define DDR_PHY_VTCR1_HVIO_SHIFT 0 9393#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U 9394 9395/*Reserved. Return zeroes on reads.*/ 9396#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 9397#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 9398#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 9399#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 9400#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 9401#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U 9402 9403/*Delay select for the BDL on Parity.*/ 9404#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL 9405#undef DDR_PHY_ACBDLR1_PARBD_SHIFT 9406#undef DDR_PHY_ACBDLR1_PARBD_MASK 9407#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 9408#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 9409#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U 9410 9411/*Reserved. Return zeroes on reads.*/ 9412#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 9413#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 9414#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 9415#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 9416#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 9417#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U 9418 9419/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/ 9420#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL 9421#undef DDR_PHY_ACBDLR1_A16BD_SHIFT 9422#undef DDR_PHY_ACBDLR1_A16BD_MASK 9423#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 9424#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 9425#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U 9426 9427/*Reserved. Return zeroes on reads.*/ 9428#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 9429#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 9430#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 9431#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 9432#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 9433#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U 9434 9435/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/ 9436#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL 9437#undef DDR_PHY_ACBDLR1_A17BD_SHIFT 9438#undef DDR_PHY_ACBDLR1_A17BD_MASK 9439#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 9440#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 9441#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U 9442 9443/*Reserved. Return zeroes on reads.*/ 9444#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 9445#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 9446#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 9447#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 9448#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 9449#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U 9450 9451/*Delay select for the BDL on ACTN.*/ 9452#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL 9453#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT 9454#undef DDR_PHY_ACBDLR1_ACTBD_MASK 9455#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 9456#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 9457#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU 9458 9459/*Reserved. Return zeroes on reads.*/ 9460#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 9461#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 9462#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 9463#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 9464#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 9465#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U 9466 9467/*Delay select for the BDL on BG[1].*/ 9468#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL 9469#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT 9470#undef DDR_PHY_ACBDLR2_BG1BD_MASK 9471#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 9472#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 9473#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U 9474 9475/*Reserved. Return zeroes on reads.*/ 9476#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 9477#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 9478#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 9479#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 9480#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 9481#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U 9482 9483/*Delay select for the BDL on BG[0].*/ 9484#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL 9485#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT 9486#undef DDR_PHY_ACBDLR2_BG0BD_MASK 9487#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 9488#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 9489#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U 9490 9491/*Reser.ved Return zeroes on reads.*/ 9492#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 9493#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 9494#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 9495#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 9496#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 9497#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U 9498 9499/*Delay select for the BDL on BA[1].*/ 9500#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL 9501#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT 9502#undef DDR_PHY_ACBDLR2_BA1BD_MASK 9503#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 9504#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 9505#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U 9506 9507/*Reserved. Return zeroes on reads.*/ 9508#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 9509#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 9510#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 9511#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 9512#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 9513#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U 9514 9515/*Delay select for the BDL on BA[0].*/ 9516#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL 9517#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT 9518#undef DDR_PHY_ACBDLR2_BA0BD_MASK 9519#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 9520#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 9521#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU 9522 9523/*Reserved. Return zeroes on reads.*/ 9524#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 9525#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 9526#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 9527#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 9528#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 9529#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U 9530 9531/*Delay select for the BDL on Address A[3].*/ 9532#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 9533#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 9534#undef DDR_PHY_ACBDLR6_A03BD_MASK 9535#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 9536#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 9537#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U 9538 9539/*Reserved. Return zeroes on reads.*/ 9540#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 9541#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 9542#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 9543#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 9544#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 9545#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U 9546 9547/*Delay select for the BDL on Address A[2].*/ 9548#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 9549#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 9550#undef DDR_PHY_ACBDLR6_A02BD_MASK 9551#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 9552#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 9553#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U 9554 9555/*Reserved. Return zeroes on reads.*/ 9556#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 9557#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 9558#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 9559#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 9560#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 9561#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U 9562 9563/*Delay select for the BDL on Address A[1].*/ 9564#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 9565#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 9566#undef DDR_PHY_ACBDLR6_A01BD_MASK 9567#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 9568#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 9569#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U 9570 9571/*Reserved. Return zeroes on reads.*/ 9572#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 9573#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 9574#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 9575#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 9576#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 9577#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U 9578 9579/*Delay select for the BDL on Address A[0].*/ 9580#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 9581#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 9582#undef DDR_PHY_ACBDLR6_A00BD_MASK 9583#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 9584#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 9585#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU 9586 9587/*Reserved. Return zeroes on reads.*/ 9588#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 9589#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 9590#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 9591#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 9592#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 9593#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U 9594 9595/*Delay select for the BDL on Address A[7].*/ 9596#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 9597#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 9598#undef DDR_PHY_ACBDLR7_A07BD_MASK 9599#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 9600#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 9601#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U 9602 9603/*Reserved. Return zeroes on reads.*/ 9604#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 9605#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 9606#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 9607#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 9608#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 9609#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U 9610 9611/*Delay select for the BDL on Address A[6].*/ 9612#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 9613#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 9614#undef DDR_PHY_ACBDLR7_A06BD_MASK 9615#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 9616#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 9617#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U 9618 9619/*Reserved. Return zeroes on reads.*/ 9620#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 9621#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 9622#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 9623#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 9624#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 9625#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U 9626 9627/*Delay select for the BDL on Address A[5].*/ 9628#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 9629#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 9630#undef DDR_PHY_ACBDLR7_A05BD_MASK 9631#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 9632#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 9633#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U 9634 9635/*Reserved. Return zeroes on reads.*/ 9636#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 9637#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 9638#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 9639#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 9640#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 9641#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U 9642 9643/*Delay select for the BDL on Address A[4].*/ 9644#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 9645#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 9646#undef DDR_PHY_ACBDLR7_A04BD_MASK 9647#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 9648#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 9649#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU 9650 9651/*Reserved. Return zeroes on reads.*/ 9652#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 9653#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 9654#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 9655#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 9656#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 9657#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U 9658 9659/*Delay select for the BDL on Address A[11].*/ 9660#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 9661#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 9662#undef DDR_PHY_ACBDLR8_A11BD_MASK 9663#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 9664#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 9665#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U 9666 9667/*Reserved. Return zeroes on reads.*/ 9668#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 9669#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 9670#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 9671#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 9672#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 9673#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U 9674 9675/*Delay select for the BDL on Address A[10].*/ 9676#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 9677#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 9678#undef DDR_PHY_ACBDLR8_A10BD_MASK 9679#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 9680#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 9681#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U 9682 9683/*Reserved. Return zeroes on reads.*/ 9684#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 9685#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 9686#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 9687#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 9688#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 9689#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U 9690 9691/*Delay select for the BDL on Address A[9].*/ 9692#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 9693#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 9694#undef DDR_PHY_ACBDLR8_A09BD_MASK 9695#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 9696#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 9697#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U 9698 9699/*Reserved. Return zeroes on reads.*/ 9700#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 9701#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 9702#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 9703#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 9704#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 9705#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U 9706 9707/*Delay select for the BDL on Address A[8].*/ 9708#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 9709#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 9710#undef DDR_PHY_ACBDLR8_A08BD_MASK 9711#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 9712#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 9713#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU 9714 9715/*Reserved. Return zeroes on reads.*/ 9716#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 9717#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 9718#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 9719#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 9720#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 9721#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U 9722 9723/*Delay select for the BDL on Address A[15].*/ 9724#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL 9725#undef DDR_PHY_ACBDLR9_A15BD_SHIFT 9726#undef DDR_PHY_ACBDLR9_A15BD_MASK 9727#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 9728#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 9729#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U 9730 9731/*Reserved. Return zeroes on reads.*/ 9732#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 9733#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 9734#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 9735#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 9736#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 9737#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U 9738 9739/*Delay select for the BDL on Address A[14].*/ 9740#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL 9741#undef DDR_PHY_ACBDLR9_A14BD_SHIFT 9742#undef DDR_PHY_ACBDLR9_A14BD_MASK 9743#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 9744#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 9745#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U 9746 9747/*Reserved. Return zeroes on reads.*/ 9748#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 9749#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 9750#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 9751#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 9752#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 9753#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U 9754 9755/*Delay select for the BDL on Address A[13].*/ 9756#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL 9757#undef DDR_PHY_ACBDLR9_A13BD_SHIFT 9758#undef DDR_PHY_ACBDLR9_A13BD_MASK 9759#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 9760#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 9761#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U 9762 9763/*Reserved. Return zeroes on reads.*/ 9764#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 9765#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 9766#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 9767#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 9768#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 9769#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U 9770 9771/*Delay select for the BDL on Address A[12].*/ 9772#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL 9773#undef DDR_PHY_ACBDLR9_A12BD_SHIFT 9774#undef DDR_PHY_ACBDLR9_A12BD_MASK 9775#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 9776#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 9777#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU 9778 9779/*Reserved. Return zeroes on reads.*/ 9780#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 9781#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 9782#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 9783#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 9784#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 9785#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U 9786 9787/*ZQ VREF Range*/ 9788#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 9789#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 9790#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 9791#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 9792#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 9793#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U 9794 9795/*Programmable Wait for Frequency B*/ 9796#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 9797#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 9798#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 9799#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 9800#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 9801#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U 9802 9803/*Programmable Wait for Frequency A*/ 9804#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 9805#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 9806#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 9807#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 9808#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 9809#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U 9810 9811/*ZQ VREF Pad Enable*/ 9812#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 9813#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 9814#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 9815#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 9816#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 9817#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U 9818 9819/*ZQ Internal VREF Enable*/ 9820#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 9821#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 9822#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 9823#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 9824#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 9825#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U 9826 9827/*Choice of termination mode*/ 9828#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 9829#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 9830#undef DDR_PHY_ZQCR_ODT_MODE_MASK 9831#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 9832#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 9833#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U 9834 9835/*Force ZCAL VT update*/ 9836#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 9837#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 9838#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 9839#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 9840#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 9841#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U 9842 9843/*IO VT Drift Limit*/ 9844#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 9845#undef DDR_PHY_ZQCR_IODLMT_SHIFT 9846#undef DDR_PHY_ZQCR_IODLMT_MASK 9847#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 9848#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 9849#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U 9850 9851/*Averaging algorithm enable, if set, enables averaging algorithm*/ 9852#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 9853#undef DDR_PHY_ZQCR_AVGEN_SHIFT 9854#undef DDR_PHY_ZQCR_AVGEN_MASK 9855#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 9856#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 9857#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U 9858 9859/*Maximum number of averaging rounds to be used by averaging algorithm*/ 9860#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 9861#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 9862#undef DDR_PHY_ZQCR_AVGMAX_MASK 9863#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 9864#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 9865#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU 9866 9867/*ZQ Calibration Type*/ 9868#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 9869#undef DDR_PHY_ZQCR_ZCALT_SHIFT 9870#undef DDR_PHY_ZQCR_ZCALT_MASK 9871#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 9872#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 9873#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U 9874 9875/*ZQ Power Down*/ 9876#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 9877#undef DDR_PHY_ZQCR_ZQPD_SHIFT 9878#undef DDR_PHY_ZQCR_ZQPD_MASK 9879#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 9880#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 9881#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U 9882 9883/*Pull-down drive strength ZCTRL over-ride enable*/ 9884#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 9885#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 9886#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 9887#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB 9888#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 9889#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U 9890 9891/*Pull-up drive strength ZCTRL over-ride enable*/ 9892#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 9893#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 9894#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 9895#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB 9896#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 9897#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U 9898 9899/*Pull-down termination ZCTRL over-ride enable*/ 9900#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 9901#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 9902#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 9903#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB 9904#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 9905#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U 9906 9907/*Pull-up termination ZCTRL over-ride enable*/ 9908#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 9909#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 9910#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 9911#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB 9912#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 9913#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U 9914 9915/*Calibration segment bypass*/ 9916#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 9917#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 9918#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 9919#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB 9920#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 9921#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U 9922 9923/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ 9924#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 9925#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 9926#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 9927#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB 9928#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 9929#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U 9930 9931/*Termination adjustment*/ 9932#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 9933#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 9934#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 9935#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB 9936#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 9937#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U 9938 9939/*Pulldown drive strength adjustment*/ 9940#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 9941#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 9942#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 9943#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB 9944#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 9945#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U 9946 9947/*Pullup drive strength adjustment*/ 9948#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 9949#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 9950#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 9951#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB 9952#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 9953#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U 9954 9955/*DRAM Impedance Divide Ratio*/ 9956#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 9957#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 9958#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 9959#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB 9960#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 9961#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U 9962 9963/*HOST Impedance Divide Ratio*/ 9964#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 9965#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 9966#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 9967#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB 9968#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 9969#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U 9970 9971/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ 9972#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 9973#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 9974#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 9975#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB 9976#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 9977#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U 9978 9979/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ 9980#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 9981#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 9982#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 9983#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB 9984#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 9985#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU 9986 9987/*Reserved. Return zeros on reads.*/ 9988#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 9989#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 9990#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 9991#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 9992#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 9993#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U 9994 9995/*Override value for the pull-up output impedance*/ 9996#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 9997#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 9998#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 9999#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 10000#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16
10001#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U 10002 10003/*Reserved. Return zeros on reads.*/ 10004#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 10005#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10006#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 10007#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 10008#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 10009#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U 10010 10011/*Override value for the pull-down output impedance*/ 10012#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 10013#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 10014#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 10015#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 10016#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 10017#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU 10018 10019/*Reserved. Return zeros on reads.*/ 10020#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 10021#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 10022#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 10023#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 10024#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 10025#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U 10026 10027/*Override value for the pull-up termination*/ 10028#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 10029#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 10030#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 10031#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 10032#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 10033#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U 10034 10035/*Reserved. Return zeros on reads.*/ 10036#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 10037#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10038#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 10039#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 10040#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 10041#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U 10042 10043/*Override value for the pull-down termination*/ 10044#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 10045#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 10046#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 10047#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 10048#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 10049#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU 10050 10051/*Pull-down drive strength ZCTRL over-ride enable*/ 10052#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 10053#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 10054#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 10055#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB 10056#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 10057#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U 10058 10059/*Pull-up drive strength ZCTRL over-ride enable*/ 10060#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 10061#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 10062#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 10063#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB 10064#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 10065#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U 10066 10067/*Pull-down termination ZCTRL over-ride enable*/ 10068#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 10069#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 10070#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 10071#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB 10072#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 10073#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U 10074 10075/*Pull-up termination ZCTRL over-ride enable*/ 10076#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 10077#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 10078#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 10079#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB 10080#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 10081#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U 10082 10083/*Calibration segment bypass*/ 10084#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 10085#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 10086#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 10087#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB 10088#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 10089#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U 10090 10091/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ 10092#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 10093#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 10094#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 10095#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB 10096#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 10097#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U 10098 10099/*Termination adjustment*/ 10100#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 10101#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 10102#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 10103#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB 10104#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 10105#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U 10106 10107/*Pulldown drive strength adjustment*/ 10108#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 10109#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 10110#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 10111#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB 10112#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 10113#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U 10114 10115/*Pullup drive strength adjustment*/ 10116#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 10117#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 10118#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 10119#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB 10120#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 10121#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U 10122 10123/*DRAM Impedance Divide Ratio*/ 10124#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 10125#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 10126#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 10127#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB 10128#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 10129#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U 10130 10131/*HOST Impedance Divide Ratio*/ 10132#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 10133#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 10134#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 10135#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB 10136#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 10137#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U 10138 10139/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ 10140#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 10141#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 10142#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 10143#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB 10144#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 10145#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U 10146 10147/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ 10148#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 10149#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 10150#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 10151#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB 10152#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 10153#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU 10154 10155/*Calibration Bypass*/ 10156#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 10157#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 10158#undef DDR_PHY_DX0GCR0_CALBYP_MASK 10159#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 10160#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 10161#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U 10162 10163/*Master Delay Line Enable*/ 10164#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 10165#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 10166#undef DDR_PHY_DX0GCR0_MDLEN_MASK 10167#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 10168#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 10169#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U 10170 10171/*Configurable ODT(TE) Phase Shift*/ 10172#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 10173#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 10174#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 10175#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 10176#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 10177#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U 10178 10179/*DQS Duty Cycle Correction*/ 10180#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 10181#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 10182#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 10183#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 10184#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 10185#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U 10186 10187/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 10188#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 10189#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 10190#undef DDR_PHY_DX0GCR0_RDDLY_MASK 10191#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 10192#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 10193#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U 10194 10195/*Reserved. Return zeroes on reads.*/ 10196#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 10197#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 10198#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 10199#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 10200#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 10201#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U 10202 10203/*DQSNSE Power Down Receiver*/ 10204#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 10205#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 10206#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 10207#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 10208#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 10209#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U 10210 10211/*DQSSE Power Down Receiver*/ 10212#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 10213#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 10214#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 10215#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 10216#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 10217#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U 10218 10219/*RTT On Additive Latency*/ 10220#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 10221#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 10222#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 10223#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 10224#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 10225#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U 10226 10227/*RTT Output Hold*/ 10228#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 10229#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 10230#undef DDR_PHY_DX0GCR0_RTTOH_MASK 10231#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 10232#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 10233#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U 10234 10235/*Configurable PDR Phase Shift*/ 10236#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 10237#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 10238#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 10239#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 10240#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 10241#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U 10242 10243/*DQSR Power Down*/ 10244#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 10245#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 10246#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 10247#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 10248#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 10249#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U 10250 10251/*DQSG Power Down Receiver*/ 10252#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 10253#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 10254#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 10255#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 10256#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 10257#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U 10258 10259/*Reserved. Return zeroes on reads.*/ 10260#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 10261#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 10262#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 10263#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 10264#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 10265#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U 10266 10267/*DQSG On-Die Termination*/ 10268#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 10269#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 10270#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 10271#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 10272#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 10273#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U 10274 10275/*DQSG Output Enable*/ 10276#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 10277#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 10278#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 10279#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 10280#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 10281#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U 10282 10283/*Reserved. Return zeroes on reads.*/ 10284#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 10285#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 10286#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 10287#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 10288#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 10289#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U 10290 10291/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 10292#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 10293#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 10294#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 10295#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 10296#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 10297#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U 10298 10299/*Byte Lane VREF Pad Enable*/ 10300#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 10301#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 10302#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 10303#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C 10304#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 10305#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U 10306 10307/*Byte Lane Internal VREF Enable*/ 10308#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 10309#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 10310#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 10311#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C 10312#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 10313#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U 10314 10315/*Byte Lane Single-End VREF Enable*/ 10316#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 10317#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 10318#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 10319#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C 10320#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 10321#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U 10322 10323/*Reserved. Returns zeros on reads.*/ 10324#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 10325#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 10326#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 10327#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C 10328#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 10329#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U 10330 10331/*External VREF generator REFSEL range select*/ 10332#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 10333#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 10334#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 10335#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 10336#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 10337#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U 10338 10339/*Byte Lane External VREF Select*/ 10340#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 10341#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 10342#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 10343#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C 10344#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 10345#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U 10346 10347/*Single ended VREF generator REFSEL range select*/ 10348#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 10349#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 10350#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 10351#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 10352#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 10353#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U 10354 10355/*Byte Lane Single-End VREF Select*/ 10356#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 10357#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 10358#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 10359#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C 10360#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 10361#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U 10362 10363/*Reserved. Returns zeros on reads.*/ 10364#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 10365#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 10366#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 10367#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 10368#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 10369#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U 10370 10371/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 10372#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 10373#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 10374#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 10375#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C 10376#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 10377#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU 10378 10379/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 10380#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 10381#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 10382#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 10383#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C 10384#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 10385#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U 10386 10387/*Reserved. Returns zeros on reads.*/ 10388#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 10389#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 10390#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 10391#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 10392#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 10393#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U 10394 10395/*Byte Lane internal VREF Select for Rank 3*/ 10396#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 10397#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 10398#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 10399#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 10400#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 10401#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U 10402 10403/*Reserved. Returns zeros on reads.*/ 10404#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 10405#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 10406#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 10407#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 10408#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 10409#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U 10410 10411/*Byte Lane internal VREF Select for Rank 2*/ 10412#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 10413#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 10414#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 10415#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 10416#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 10417#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U 10418 10419/*Reserved. Returns zeros on reads.*/ 10420#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 10421#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 10422#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 10423#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 10424#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 10425#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U 10426 10427/*Byte Lane internal VREF Select for Rank 1*/ 10428#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 10429#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 10430#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 10431#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 10432#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 10433#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U 10434 10435/*Reserved. Returns zeros on reads.*/ 10436#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 10437#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 10438#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 10439#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 10440#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 10441#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U 10442 10443/*Byte Lane internal VREF Select for Rank 0*/ 10444#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 10445#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 10446#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 10447#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 10448#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 10449#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU 10450 10451/*Reserved. Returns zeros on reads.*/ 10452#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 10453#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 10454#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 10455#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 10456#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 10457#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U 10458 10459/*DRAM DQ VREF Select for Rank3*/ 10460#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 10461#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 10462#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 10463#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 10464#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 10465#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U 10466 10467/*Reserved. Returns zeros on reads.*/ 10468#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 10469#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 10470#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 10471#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 10472#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 10473#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U 10474 10475/*DRAM DQ VREF Select for Rank2*/ 10476#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 10477#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 10478#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 10479#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 10480#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 10481#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U 10482 10483/*Reserved. Returns zeros on reads.*/ 10484#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 10485#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 10486#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 10487#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 10488#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 10489#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U 10490 10491/*DRAM DQ VREF Select for Rank1*/ 10492#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 10493#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 10494#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 10495#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 10496#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 10497#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U 10498 10499/*Reserved. Returns zeros on reads.*/ 10500#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 10501#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 10502#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 10503#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 10504#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 10505#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U 10506 10507/*DRAM DQ VREF Select for Rank0*/ 10508#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 10509#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 10510#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 10511#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 10512#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 10513#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU 10514 10515/*Reserved. Return zeroes on reads.*/ 10516#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 10517#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 10518#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 10519#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 10520#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25 10521#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U 10522 10523/*Reserved. Caution, do not write to this register field.*/ 10524#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 10525#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 10526#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 10527#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 10528#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16 10529#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 10530 10531/*Reserved. Return zeroes on reads.*/ 10532#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 10533#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 10534#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 10535#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 10536#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9 10537#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 10538 10539/*Read DQS Gating Delay*/ 10540#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 10541#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 10542#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK 10543#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000 10544#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0 10545#define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU 10546 10547/*Reserved. Return zeroes on reads.*/ 10548#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 10549#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 10550#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 10551#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000 10552#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27 10553#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U 10554 10555/*DQ Write Path Latency Pipeline*/ 10556#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL 10557#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT 10558#undef DDR_PHY_DX0GTR0_WDQSL_MASK 10559#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000 10560#define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24 10561#define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U 10562 10563/*Reserved. Caution, do not write to this register field.*/ 10564#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 10565#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 10566#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 10567#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000 10568#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20 10569#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U 10570 10571/*Write Leveling System Latency*/ 10572#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL 10573#undef DDR_PHY_DX0GTR0_WLSL_SHIFT 10574#undef DDR_PHY_DX0GTR0_WLSL_MASK 10575#define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000 10576#define DDR_PHY_DX0GTR0_WLSL_SHIFT 16 10577#define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U 10578 10579/*Reserved. Return zeroes on reads.*/ 10580#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 10581#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 10582#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 10583#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000 10584#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13 10585#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U 10586 10587/*Reserved. Caution, do not write to this register field.*/ 10588#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 10589#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 10590#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 10591#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000 10592#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8 10593#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U 10594 10595/*Reserved. Return zeroes on reads.*/ 10596#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 10597#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 10598#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 10599#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000 10600#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5 10601#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U 10602 10603/*DQS Gating System Latency*/ 10604#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL 10605#undef DDR_PHY_DX0GTR0_DGSL_SHIFT 10606#undef DDR_PHY_DX0GTR0_DGSL_MASK 10607#define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000 10608#define DDR_PHY_DX0GTR0_DGSL_SHIFT 0 10609#define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU 10610 10611/*Calibration Bypass*/ 10612#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 10613#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 10614#undef DDR_PHY_DX1GCR0_CALBYP_MASK 10615#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 10616#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 10617#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U 10618 10619/*Master Delay Line Enable*/ 10620#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 10621#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 10622#undef DDR_PHY_DX1GCR0_MDLEN_MASK 10623#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 10624#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 10625#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U 10626 10627/*Configurable ODT(TE) Phase Shift*/ 10628#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 10629#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 10630#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 10631#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 10632#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 10633#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U 10634 10635/*DQS Duty Cycle Correction*/ 10636#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 10637#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 10638#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 10639#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 10640#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 10641#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U 10642 10643/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 10644#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 10645#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 10646#undef DDR_PHY_DX1GCR0_RDDLY_MASK 10647#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 10648#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 10649#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U 10650 10651/*Reserved. Return zeroes on reads.*/ 10652#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 10653#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 10654#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 10655#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 10656#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 10657#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U 10658 10659/*DQSNSE Power Down Receiver*/ 10660#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 10661#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 10662#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 10663#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 10664#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 10665#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U 10666 10667/*DQSSE Power Down Receiver*/ 10668#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 10669#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 10670#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 10671#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 10672#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 10673#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U 10674 10675/*RTT On Additive Latency*/ 10676#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 10677#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 10678#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 10679#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 10680#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 10681#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U 10682 10683/*RTT Output Hold*/ 10684#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 10685#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 10686#undef DDR_PHY_DX1GCR0_RTTOH_MASK 10687#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 10688#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 10689#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U 10690 10691/*Configurable PDR Phase Shift*/ 10692#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 10693#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 10694#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 10695#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 10696#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 10697#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U 10698 10699/*DQSR Power Down*/ 10700#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 10701#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 10702#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 10703#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 10704#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 10705#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U 10706 10707/*DQSG Power Down Receiver*/ 10708#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 10709#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 10710#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 10711#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 10712#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 10713#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U 10714 10715/*Reserved. Return zeroes on reads.*/ 10716#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 10717#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 10718#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 10719#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 10720#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 10721#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U 10722 10723/*DQSG On-Die Termination*/ 10724#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 10725#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 10726#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 10727#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 10728#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 10729#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U 10730 10731/*DQSG Output Enable*/ 10732#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 10733#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 10734#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 10735#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 10736#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 10737#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U 10738 10739/*Reserved. Return zeroes on reads.*/ 10740#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 10741#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 10742#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 10743#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 10744#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 10745#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U 10746 10747/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 10748#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 10749#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 10750#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 10751#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 10752#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 10753#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U 10754 10755/*Byte Lane VREF Pad Enable*/ 10756#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 10757#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 10758#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 10759#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C 10760#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 10761#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U 10762 10763/*Byte Lane Internal VREF Enable*/ 10764#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 10765#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 10766#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 10767#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C 10768#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 10769#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U 10770 10771/*Byte Lane Single-End VREF Enable*/ 10772#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 10773#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 10774#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 10775#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C 10776#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 10777#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U 10778 10779/*Reserved. Returns zeros on reads.*/ 10780#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 10781#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 10782#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 10783#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C 10784#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 10785#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U 10786 10787/*External VREF generator REFSEL range select*/ 10788#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 10789#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 10790#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 10791#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 10792#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 10793#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U 10794 10795/*Byte Lane External VREF Select*/ 10796#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 10797#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 10798#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 10799#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C 10800#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 10801#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U 10802 10803/*Single ended VREF generator REFSEL range select*/ 10804#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 10805#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 10806#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 10807#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 10808#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 10809#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U 10810 10811/*Byte Lane Single-End VREF Select*/ 10812#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 10813#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 10814#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 10815#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C 10816#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 10817#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U 10818 10819/*Reserved. Returns zeros on reads.*/ 10820#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 10821#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 10822#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 10823#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 10824#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 10825#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U 10826 10827/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 10828#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 10829#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 10830#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 10831#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C 10832#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 10833#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU 10834 10835/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 10836#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 10837#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 10838#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 10839#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C 10840#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 10841#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U 10842 10843/*Reserved. Returns zeros on reads.*/ 10844#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 10845#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 10846#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 10847#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 10848#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 10849#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U 10850 10851/*Byte Lane internal VREF Select for Rank 3*/ 10852#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 10853#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 10854#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 10855#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 10856#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 10857#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U 10858 10859/*Reserved. Returns zeros on reads.*/ 10860#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 10861#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 10862#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 10863#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 10864#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 10865#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U 10866 10867/*Byte Lane internal VREF Select for Rank 2*/ 10868#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 10869#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 10870#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 10871#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 10872#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 10873#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U 10874 10875/*Reserved. Returns zeros on reads.*/ 10876#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 10877#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 10878#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 10879#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 10880#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 10881#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U 10882 10883/*Byte Lane internal VREF Select for Rank 1*/ 10884#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 10885#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 10886#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 10887#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 10888#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 10889#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U 10890 10891/*Reserved. Returns zeros on reads.*/ 10892#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 10893#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 10894#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 10895#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 10896#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 10897#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U 10898 10899/*Byte Lane internal VREF Select for Rank 0*/ 10900#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 10901#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 10902#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 10903#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 10904#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 10905#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU 10906 10907/*Reserved. Returns zeros on reads.*/ 10908#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 10909#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 10910#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 10911#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 10912#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 10913#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U 10914 10915/*DRAM DQ VREF Select for Rank3*/ 10916#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 10917#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 10918#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 10919#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 10920#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 10921#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U 10922 10923/*Reserved. Returns zeros on reads.*/ 10924#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 10925#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 10926#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 10927#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 10928#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 10929#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U 10930 10931/*DRAM DQ VREF Select for Rank2*/ 10932#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 10933#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 10934#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 10935#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 10936#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 10937#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U 10938 10939/*Reserved. Returns zeros on reads.*/ 10940#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 10941#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 10942#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 10943#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 10944#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 10945#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U 10946 10947/*DRAM DQ VREF Select for Rank1*/ 10948#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 10949#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 10950#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 10951#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 10952#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 10953#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U 10954 10955/*Reserved. Returns zeros on reads.*/ 10956#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 10957#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 10958#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 10959#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 10960#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 10961#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U 10962 10963/*DRAM DQ VREF Select for Rank0*/ 10964#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 10965#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 10966#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 10967#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 10968#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 10969#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU 10970 10971/*Reserved. Return zeroes on reads.*/ 10972#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 10973#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 10974#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 10975#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 10976#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25 10977#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U 10978 10979/*Reserved. Caution, do not write to this register field.*/ 10980#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 10981#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 10982#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 10983#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 10984#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16 10985#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 10986 10987/*Reserved. Return zeroes on reads.*/ 10988#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 10989#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 10990#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 10991#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 10992#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9 10993#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 10994 10995/*Read DQS Gating Delay*/ 10996#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 10997#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 10998#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK 10999#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000 11000#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0
11001#define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU 11002 11003/*Reserved. Return zeroes on reads.*/ 11004#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 11005#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 11006#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 11007#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000 11008#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27 11009#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U 11010 11011/*DQ Write Path Latency Pipeline*/ 11012#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL 11013#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT 11014#undef DDR_PHY_DX1GTR0_WDQSL_MASK 11015#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000 11016#define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24 11017#define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U 11018 11019/*Reserved. Caution, do not write to this register field.*/ 11020#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 11021#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 11022#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 11023#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000 11024#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20 11025#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U 11026 11027/*Write Leveling System Latency*/ 11028#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL 11029#undef DDR_PHY_DX1GTR0_WLSL_SHIFT 11030#undef DDR_PHY_DX1GTR0_WLSL_MASK 11031#define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000 11032#define DDR_PHY_DX1GTR0_WLSL_SHIFT 16 11033#define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U 11034 11035/*Reserved. Return zeroes on reads.*/ 11036#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 11037#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 11038#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 11039#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000 11040#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13 11041#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U 11042 11043/*Reserved. Caution, do not write to this register field.*/ 11044#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 11045#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 11046#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 11047#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000 11048#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8 11049#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U 11050 11051/*Reserved. Return zeroes on reads.*/ 11052#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 11053#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 11054#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 11055#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000 11056#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5 11057#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U 11058 11059/*DQS Gating System Latency*/ 11060#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL 11061#undef DDR_PHY_DX1GTR0_DGSL_SHIFT 11062#undef DDR_PHY_DX1GTR0_DGSL_MASK 11063#define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000 11064#define DDR_PHY_DX1GTR0_DGSL_SHIFT 0 11065#define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU 11066 11067/*Calibration Bypass*/ 11068#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 11069#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 11070#undef DDR_PHY_DX2GCR0_CALBYP_MASK 11071#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 11072#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 11073#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U 11074 11075/*Master Delay Line Enable*/ 11076#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 11077#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 11078#undef DDR_PHY_DX2GCR0_MDLEN_MASK 11079#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 11080#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 11081#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U 11082 11083/*Configurable ODT(TE) Phase Shift*/ 11084#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 11085#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 11086#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 11087#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 11088#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 11089#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U 11090 11091/*DQS Duty Cycle Correction*/ 11092#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 11093#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 11094#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 11095#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 11096#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 11097#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U 11098 11099/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 11100#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 11101#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 11102#undef DDR_PHY_DX2GCR0_RDDLY_MASK 11103#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 11104#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 11105#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U 11106 11107/*Reserved. Return zeroes on reads.*/ 11108#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 11109#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 11110#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 11111#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 11112#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 11113#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U 11114 11115/*DQSNSE Power Down Receiver*/ 11116#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 11117#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 11118#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 11119#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 11120#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 11121#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U 11122 11123/*DQSSE Power Down Receiver*/ 11124#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 11125#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 11126#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 11127#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 11128#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 11129#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U 11130 11131/*RTT On Additive Latency*/ 11132#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 11133#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11134#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 11135#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 11136#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 11137#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U 11138 11139/*RTT Output Hold*/ 11140#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 11141#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 11142#undef DDR_PHY_DX2GCR0_RTTOH_MASK 11143#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 11144#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 11145#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U 11146 11147/*Configurable PDR Phase Shift*/ 11148#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 11149#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 11150#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 11151#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 11152#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 11153#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U 11154 11155/*DQSR Power Down*/ 11156#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 11157#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 11158#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 11159#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 11160#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 11161#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U 11162 11163/*DQSG Power Down Receiver*/ 11164#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 11165#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 11166#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 11167#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 11168#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 11169#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U 11170 11171/*Reserved. Return zeroes on reads.*/ 11172#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 11173#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 11174#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 11175#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 11176#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 11177#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U 11178 11179/*DQSG On-Die Termination*/ 11180#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 11181#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 11182#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 11183#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 11184#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 11185#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U 11186 11187/*DQSG Output Enable*/ 11188#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 11189#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 11190#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 11191#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 11192#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 11193#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U 11194 11195/*Reserved. Return zeroes on reads.*/ 11196#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 11197#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 11198#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 11199#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 11200#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 11201#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U 11202 11203/*Enables the PDR mode for DQ[7:0]*/ 11204#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 11205#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 11206#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 11207#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF 11208#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 11209#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U 11210 11211/*Reserved. Returns zeroes on reads.*/ 11212#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 11213#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 11214#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 11215#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF 11216#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 11217#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U 11218 11219/*Select the delayed or non-delayed read data strobe #*/ 11220#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 11221#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 11222#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 11223#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF 11224#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 11225#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U 11226 11227/*Select the delayed or non-delayed read data strobe*/ 11228#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 11229#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 11230#undef DDR_PHY_DX2GCR1_QSSEL_MASK 11231#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF 11232#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 11233#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U 11234 11235/*Enables Read Data Strobe in a byte lane*/ 11236#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 11237#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 11238#undef DDR_PHY_DX2GCR1_OEEN_MASK 11239#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF 11240#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 11241#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U 11242 11243/*Enables PDR in a byte lane*/ 11244#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 11245#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 11246#undef DDR_PHY_DX2GCR1_PDREN_MASK 11247#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF 11248#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 11249#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U 11250 11251/*Enables ODT/TE in a byte lane*/ 11252#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 11253#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 11254#undef DDR_PHY_DX2GCR1_TEEN_MASK 11255#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF 11256#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 11257#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U 11258 11259/*Enables Write Data strobe in a byte lane*/ 11260#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 11261#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 11262#undef DDR_PHY_DX2GCR1_DSEN_MASK 11263#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF 11264#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 11265#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U 11266 11267/*Enables DM pin in a byte lane*/ 11268#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 11269#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 11270#undef DDR_PHY_DX2GCR1_DMEN_MASK 11271#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF 11272#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 11273#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U 11274 11275/*Enables DQ corresponding to each bit in a byte*/ 11276#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 11277#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 11278#undef DDR_PHY_DX2GCR1_DQEN_MASK 11279#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF 11280#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 11281#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU 11282 11283/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 11284#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 11285#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 11286#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 11287#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 11288#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 11289#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U 11290 11291/*Byte Lane VREF Pad Enable*/ 11292#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 11293#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 11294#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 11295#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C 11296#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 11297#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U 11298 11299/*Byte Lane Internal VREF Enable*/ 11300#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 11301#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 11302#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 11303#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C 11304#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 11305#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U 11306 11307/*Byte Lane Single-End VREF Enable*/ 11308#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 11309#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 11310#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 11311#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C 11312#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 11313#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U 11314 11315/*Reserved. Returns zeros on reads.*/ 11316#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 11317#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 11318#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 11319#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C 11320#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 11321#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U 11322 11323/*External VREF generator REFSEL range select*/ 11324#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 11325#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 11326#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 11327#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 11328#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 11329#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U 11330 11331/*Byte Lane External VREF Select*/ 11332#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 11333#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 11334#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 11335#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C 11336#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 11337#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U 11338 11339/*Single ended VREF generator REFSEL range select*/ 11340#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 11341#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 11342#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 11343#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 11344#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 11345#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U 11346 11347/*Byte Lane Single-End VREF Select*/ 11348#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 11349#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 11350#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 11351#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C 11352#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 11353#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U 11354 11355/*Reserved. Returns zeros on reads.*/ 11356#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 11357#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 11358#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 11359#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 11360#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 11361#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U 11362 11363/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 11364#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 11365#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 11366#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 11367#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C 11368#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 11369#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU 11370 11371/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 11372#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 11373#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 11374#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 11375#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C 11376#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 11377#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U 11378 11379/*Reserved. Returns zeros on reads.*/ 11380#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 11381#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 11382#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 11383#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 11384#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 11385#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U 11386 11387/*Byte Lane internal VREF Select for Rank 3*/ 11388#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 11389#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 11390#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 11391#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 11392#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 11393#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U 11394 11395/*Reserved. Returns zeros on reads.*/ 11396#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 11397#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 11398#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 11399#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 11400#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 11401#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U 11402 11403/*Byte Lane internal VREF Select for Rank 2*/ 11404#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 11405#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 11406#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 11407#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 11408#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 11409#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U 11410 11411/*Reserved. Returns zeros on reads.*/ 11412#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 11413#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 11414#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 11415#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 11416#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 11417#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U 11418 11419/*Byte Lane internal VREF Select for Rank 1*/ 11420#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 11421#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 11422#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 11423#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 11424#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 11425#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U 11426 11427/*Reserved. Returns zeros on reads.*/ 11428#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 11429#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 11430#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 11431#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 11432#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 11433#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U 11434 11435/*Byte Lane internal VREF Select for Rank 0*/ 11436#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 11437#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 11438#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 11439#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 11440#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 11441#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU 11442 11443/*Reserved. Returns zeros on reads.*/ 11444#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 11445#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 11446#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 11447#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 11448#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 11449#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U 11450 11451/*DRAM DQ VREF Select for Rank3*/ 11452#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 11453#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 11454#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 11455#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 11456#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 11457#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U 11458 11459/*Reserved. Returns zeros on reads.*/ 11460#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 11461#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 11462#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 11463#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 11464#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 11465#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U 11466 11467/*DRAM DQ VREF Select for Rank2*/ 11468#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 11469#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 11470#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 11471#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 11472#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 11473#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U 11474 11475/*Reserved. Returns zeros on reads.*/ 11476#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 11477#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 11478#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 11479#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 11480#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 11481#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U 11482 11483/*DRAM DQ VREF Select for Rank1*/ 11484#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 11485#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 11486#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 11487#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 11488#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 11489#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U 11490 11491/*Reserved. Returns zeros on reads.*/ 11492#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 11493#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 11494#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 11495#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 11496#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 11497#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U 11498 11499/*DRAM DQ VREF Select for Rank0*/ 11500#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 11501#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 11502#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 11503#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 11504#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 11505#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU 11506 11507/*Reserved. Return zeroes on reads.*/ 11508#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 11509#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 11510#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 11511#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 11512#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25 11513#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U 11514 11515/*Reserved. Caution, do not write to this register field.*/ 11516#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 11517#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 11518#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 11519#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 11520#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16 11521#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 11522 11523/*Reserved. Return zeroes on reads.*/ 11524#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 11525#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 11526#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 11527#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 11528#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9 11529#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 11530 11531/*Read DQS Gating Delay*/ 11532#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 11533#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 11534#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK 11535#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000 11536#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0 11537#define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU 11538 11539/*Reserved. Return zeroes on reads.*/ 11540#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 11541#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 11542#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 11543#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000 11544#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27 11545#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U 11546 11547/*DQ Write Path Latency Pipeline*/ 11548#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL 11549#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT 11550#undef DDR_PHY_DX2GTR0_WDQSL_MASK 11551#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000 11552#define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24 11553#define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U 11554 11555/*Reserved. Caution, do not write to this register field.*/ 11556#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 11557#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 11558#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 11559#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000 11560#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20 11561#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U 11562 11563/*Write Leveling System Latency*/ 11564#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL 11565#undef DDR_PHY_DX2GTR0_WLSL_SHIFT 11566#undef DDR_PHY_DX2GTR0_WLSL_MASK 11567#define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000 11568#define DDR_PHY_DX2GTR0_WLSL_SHIFT 16 11569#define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U 11570 11571/*Reserved. Return zeroes on reads.*/ 11572#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 11573#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 11574#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 11575#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000 11576#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13 11577#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U 11578 11579/*Reserved. Caution, do not write to this register field.*/ 11580#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 11581#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 11582#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 11583#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000 11584#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8 11585#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U 11586 11587/*Reserved. Return zeroes on reads.*/ 11588#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 11589#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 11590#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 11591#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000 11592#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5 11593#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U 11594 11595/*DQS Gating System Latency*/ 11596#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL 11597#undef DDR_PHY_DX2GTR0_DGSL_SHIFT 11598#undef DDR_PHY_DX2GTR0_DGSL_MASK 11599#define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000 11600#define DDR_PHY_DX2GTR0_DGSL_SHIFT 0 11601#define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU 11602 11603/*Calibration Bypass*/ 11604#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 11605#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 11606#undef DDR_PHY_DX3GCR0_CALBYP_MASK 11607#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 11608#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 11609#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U 11610 11611/*Master Delay Line Enable*/ 11612#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 11613#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 11614#undef DDR_PHY_DX3GCR0_MDLEN_MASK 11615#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 11616#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 11617#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U 11618 11619/*Configurable ODT(TE) Phase Shift*/ 11620#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 11621#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 11622#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 11623#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 11624#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 11625#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U 11626 11627/*DQS Duty Cycle Correction*/ 11628#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 11629#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 11630#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 11631#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 11632#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 11633#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U 11634 11635/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 11636#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 11637#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 11638#undef DDR_PHY_DX3GCR0_RDDLY_MASK 11639#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 11640#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 11641#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U 11642 11643/*Reserved. Return zeroes on reads.*/ 11644#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 11645#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 11646#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 11647#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 11648#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 11649#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U 11650 11651/*DQSNSE Power Down Receiver*/ 11652#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 11653#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 11654#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 11655#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 11656#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 11657#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U 11658 11659/*DQSSE Power Down Receiver*/ 11660#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 11661#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 11662#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 11663#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 11664#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 11665#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U 11666 11667/*RTT On Additive Latency*/ 11668#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 11669#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11670#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 11671#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 11672#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 11673#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U 11674 11675/*RTT Output Hold*/ 11676#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 11677#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 11678#undef DDR_PHY_DX3GCR0_RTTOH_MASK 11679#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 11680#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 11681#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U 11682 11683/*Configurable PDR Phase Shift*/ 11684#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 11685#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 11686#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 11687#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 11688#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 11689#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U 11690 11691/*DQSR Power Down*/ 11692#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 11693#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 11694#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 11695#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 11696#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 11697#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U 11698 11699/*DQSG Power Down Receiver*/ 11700#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 11701#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 11702#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 11703#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 11704#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 11705#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U 11706 11707/*Reserved. Return zeroes on reads.*/ 11708#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 11709#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 11710#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 11711#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 11712#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 11713#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U 11714 11715/*DQSG On-Die Termination*/ 11716#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 11717#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 11718#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 11719#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 11720#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 11721#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U 11722 11723/*DQSG Output Enable*/ 11724#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 11725#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 11726#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 11727#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 11728#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 11729#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U 11730 11731/*Reserved. Return zeroes on reads.*/ 11732#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 11733#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 11734#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 11735#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 11736#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 11737#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U 11738 11739/*Enables the PDR mode for DQ[7:0]*/ 11740#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 11741#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 11742#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 11743#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF 11744#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 11745#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U 11746 11747/*Reserved. Returns zeroes on reads.*/ 11748#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 11749#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 11750#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 11751#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF 11752#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 11753#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U 11754 11755/*Select the delayed or non-delayed read data strobe #*/ 11756#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 11757#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 11758#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 11759#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF 11760#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 11761#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U 11762 11763/*Select the delayed or non-delayed read data strobe*/ 11764#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 11765#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 11766#undef DDR_PHY_DX3GCR1_QSSEL_MASK 11767#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF 11768#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 11769#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U 11770 11771/*Enables Read Data Strobe in a byte lane*/ 11772#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 11773#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 11774#undef DDR_PHY_DX3GCR1_OEEN_MASK 11775#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF 11776#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 11777#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U 11778 11779/*Enables PDR in a byte lane*/ 11780#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 11781#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 11782#undef DDR_PHY_DX3GCR1_PDREN_MASK 11783#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF 11784#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 11785#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U 11786 11787/*Enables ODT/TE in a byte lane*/ 11788#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 11789#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 11790#undef DDR_PHY_DX3GCR1_TEEN_MASK 11791#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF 11792#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 11793#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U 11794 11795/*Enables Write Data strobe in a byte lane*/ 11796#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 11797#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 11798#undef DDR_PHY_DX3GCR1_DSEN_MASK 11799#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF 11800#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 11801#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U 11802 11803/*Enables DM pin in a byte lane*/ 11804#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 11805#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 11806#undef DDR_PHY_DX3GCR1_DMEN_MASK 11807#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF 11808#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 11809#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U 11810 11811/*Enables DQ corresponding to each bit in a byte*/ 11812#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 11813#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 11814#undef DDR_PHY_DX3GCR1_DQEN_MASK 11815#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF 11816#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 11817#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU 11818 11819/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 11820#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 11821#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 11822#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 11823#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 11824#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 11825#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U 11826 11827/*Byte Lane VREF Pad Enable*/ 11828#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 11829#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 11830#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 11831#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C 11832#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 11833#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U 11834 11835/*Byte Lane Internal VREF Enable*/ 11836#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 11837#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 11838#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 11839#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C 11840#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 11841#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U 11842 11843/*Byte Lane Single-End VREF Enable*/ 11844#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 11845#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 11846#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 11847#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C 11848#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 11849#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U 11850 11851/*Reserved. Returns zeros on reads.*/ 11852#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 11853#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 11854#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 11855#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C 11856#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 11857#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U 11858 11859/*External VREF generator REFSEL range select*/ 11860#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 11861#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 11862#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 11863#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 11864#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 11865#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U 11866 11867/*Byte Lane External VREF Select*/ 11868#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 11869#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 11870#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 11871#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C 11872#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 11873#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U 11874 11875/*Single ended VREF generator REFSEL range select*/ 11876#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 11877#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 11878#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 11879#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 11880#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 11881#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U 11882 11883/*Byte Lane Single-End VREF Select*/ 11884#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 11885#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 11886#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 11887#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C 11888#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 11889#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U 11890 11891/*Reserved. Returns zeros on reads.*/ 11892#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 11893#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 11894#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 11895#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 11896#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 11897#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U 11898 11899/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 11900#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 11901#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 11902#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 11903#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C 11904#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 11905#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU 11906 11907/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 11908#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 11909#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 11910#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 11911#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C 11912#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 11913#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U 11914 11915/*Reserved. Returns zeros on reads.*/ 11916#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 11917#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 11918#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 11919#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 11920#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 11921#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U 11922 11923/*Byte Lane internal VREF Select for Rank 3*/ 11924#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 11925#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 11926#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 11927#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 11928#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 11929#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U 11930 11931/*Reserved. Returns zeros on reads.*/ 11932#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 11933#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 11934#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 11935#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 11936#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 11937#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U 11938 11939/*Byte Lane internal VREF Select for Rank 2*/ 11940#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 11941#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 11942#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 11943#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 11944#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 11945#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U 11946 11947/*Reserved. Returns zeros on reads.*/ 11948#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 11949#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 11950#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 11951#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 11952#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 11953#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U 11954 11955/*Byte Lane internal VREF Select for Rank 1*/ 11956#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 11957#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 11958#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 11959#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 11960#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 11961#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U 11962 11963/*Reserved. Returns zeros on reads.*/ 11964#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 11965#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 11966#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 11967#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 11968#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 11969#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U 11970 11971/*Byte Lane internal VREF Select for Rank 0*/ 11972#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 11973#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 11974#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 11975#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 11976#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 11977#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU 11978 11979/*Reserved. Returns zeros on reads.*/ 11980#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 11981#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 11982#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 11983#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 11984#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 11985#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U 11986 11987/*DRAM DQ VREF Select for Rank3*/ 11988#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 11989#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 11990#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 11991#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 11992#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 11993#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U 11994 11995/*Reserved. Returns zeros on reads.*/ 11996#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 11997#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 11998#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 11999#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 12000#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22
12001#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U 12002 12003/*DRAM DQ VREF Select for Rank2*/ 12004#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 12005#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 12006#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 12007#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 12008#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 12009#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U 12010 12011/*Reserved. Returns zeros on reads.*/ 12012#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 12013#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 12014#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 12015#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 12016#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 12017#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U 12018 12019/*DRAM DQ VREF Select for Rank1*/ 12020#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 12021#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 12022#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 12023#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 12024#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 12025#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U 12026 12027/*Reserved. Returns zeros on reads.*/ 12028#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 12029#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 12030#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 12031#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 12032#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 12033#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U 12034 12035/*DRAM DQ VREF Select for Rank0*/ 12036#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 12037#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 12038#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 12039#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 12040#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 12041#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU 12042 12043/*Reserved. Return zeroes on reads.*/ 12044#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 12045#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 12046#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 12047#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 12048#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25 12049#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U 12050 12051/*Reserved. Caution, do not write to this register field.*/ 12052#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 12053#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 12054#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 12055#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 12056#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16 12057#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 12058 12059/*Reserved. Return zeroes on reads.*/ 12060#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 12061#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 12062#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 12063#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 12064#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9 12065#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 12066 12067/*Read DQS Gating Delay*/ 12068#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 12069#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 12070#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK 12071#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000 12072#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0 12073#define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU 12074 12075/*Reserved. Return zeroes on reads.*/ 12076#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 12077#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 12078#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 12079#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000 12080#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27 12081#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U 12082 12083/*DQ Write Path Latency Pipeline*/ 12084#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL 12085#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT 12086#undef DDR_PHY_DX3GTR0_WDQSL_MASK 12087#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000 12088#define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24 12089#define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U 12090 12091/*Reserved. Caution, do not write to this register field.*/ 12092#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 12093#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 12094#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 12095#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000 12096#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20 12097#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U 12098 12099/*Write Leveling System Latency*/ 12100#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL 12101#undef DDR_PHY_DX3GTR0_WLSL_SHIFT 12102#undef DDR_PHY_DX3GTR0_WLSL_MASK 12103#define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000 12104#define DDR_PHY_DX3GTR0_WLSL_SHIFT 16 12105#define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U 12106 12107/*Reserved. Return zeroes on reads.*/ 12108#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 12109#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 12110#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 12111#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000 12112#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13 12113#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U 12114 12115/*Reserved. Caution, do not write to this register field.*/ 12116#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 12117#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 12118#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 12119#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000 12120#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8 12121#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U 12122 12123/*Reserved. Return zeroes on reads.*/ 12124#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 12125#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 12126#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 12127#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000 12128#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5 12129#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U 12130 12131/*DQS Gating System Latency*/ 12132#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL 12133#undef DDR_PHY_DX3GTR0_DGSL_SHIFT 12134#undef DDR_PHY_DX3GTR0_DGSL_MASK 12135#define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000 12136#define DDR_PHY_DX3GTR0_DGSL_SHIFT 0 12137#define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU 12138 12139/*Calibration Bypass*/ 12140#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 12141#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 12142#undef DDR_PHY_DX4GCR0_CALBYP_MASK 12143#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 12144#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 12145#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U 12146 12147/*Master Delay Line Enable*/ 12148#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 12149#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 12150#undef DDR_PHY_DX4GCR0_MDLEN_MASK 12151#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 12152#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 12153#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U 12154 12155/*Configurable ODT(TE) Phase Shift*/ 12156#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 12157#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 12158#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 12159#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 12160#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 12161#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U 12162 12163/*DQS Duty Cycle Correction*/ 12164#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 12165#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 12166#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 12167#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 12168#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 12169#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U 12170 12171/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 12172#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 12173#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 12174#undef DDR_PHY_DX4GCR0_RDDLY_MASK 12175#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 12176#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 12177#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U 12178 12179/*Reserved. Return zeroes on reads.*/ 12180#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 12181#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 12182#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 12183#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 12184#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 12185#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U 12186 12187/*DQSNSE Power Down Receiver*/ 12188#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 12189#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 12190#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 12191#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 12192#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 12193#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U 12194 12195/*DQSSE Power Down Receiver*/ 12196#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 12197#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12198#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 12199#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 12200#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 12201#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U 12202 12203/*RTT On Additive Latency*/ 12204#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 12205#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 12206#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 12207#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 12208#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 12209#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U 12210 12211/*RTT Output Hold*/ 12212#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 12213#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 12214#undef DDR_PHY_DX4GCR0_RTTOH_MASK 12215#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 12216#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 12217#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U 12218 12219/*Configurable PDR Phase Shift*/ 12220#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 12221#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 12222#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 12223#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 12224#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 12225#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U 12226 12227/*DQSR Power Down*/ 12228#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 12229#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 12230#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 12231#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 12232#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 12233#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U 12234 12235/*DQSG Power Down Receiver*/ 12236#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 12237#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 12238#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 12239#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 12240#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 12241#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U 12242 12243/*Reserved. Return zeroes on reads.*/ 12244#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 12245#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 12246#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 12247#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 12248#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 12249#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U 12250 12251/*DQSG On-Die Termination*/ 12252#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 12253#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 12254#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 12255#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 12256#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 12257#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U 12258 12259/*DQSG Output Enable*/ 12260#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 12261#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 12262#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 12263#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 12264#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 12265#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U 12266 12267/*Reserved. Return zeroes on reads.*/ 12268#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 12269#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 12270#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 12271#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 12272#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 12273#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U 12274 12275/*Enables the PDR mode for DQ[7:0]*/ 12276#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 12277#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 12278#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 12279#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF 12280#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 12281#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U 12282 12283/*Reserved. Returns zeroes on reads.*/ 12284#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 12285#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 12286#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 12287#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF 12288#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 12289#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U 12290 12291/*Select the delayed or non-delayed read data strobe #*/ 12292#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 12293#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 12294#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 12295#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF 12296#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 12297#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U 12298 12299/*Select the delayed or non-delayed read data strobe*/ 12300#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 12301#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 12302#undef DDR_PHY_DX4GCR1_QSSEL_MASK 12303#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF 12304#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 12305#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U 12306 12307/*Enables Read Data Strobe in a byte lane*/ 12308#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 12309#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 12310#undef DDR_PHY_DX4GCR1_OEEN_MASK 12311#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF 12312#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 12313#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U 12314 12315/*Enables PDR in a byte lane*/ 12316#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 12317#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 12318#undef DDR_PHY_DX4GCR1_PDREN_MASK 12319#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF 12320#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 12321#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U 12322 12323/*Enables ODT/TE in a byte lane*/ 12324#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 12325#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 12326#undef DDR_PHY_DX4GCR1_TEEN_MASK 12327#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF 12328#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 12329#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U 12330 12331/*Enables Write Data strobe in a byte lane*/ 12332#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 12333#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 12334#undef DDR_PHY_DX4GCR1_DSEN_MASK 12335#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF 12336#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 12337#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U 12338 12339/*Enables DM pin in a byte lane*/ 12340#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 12341#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 12342#undef DDR_PHY_DX4GCR1_DMEN_MASK 12343#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF 12344#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 12345#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U 12346 12347/*Enables DQ corresponding to each bit in a byte*/ 12348#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 12349#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 12350#undef DDR_PHY_DX4GCR1_DQEN_MASK 12351#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF 12352#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 12353#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU 12354 12355/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 12356#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 12357#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 12358#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 12359#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 12360#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 12361#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U 12362 12363/*Byte Lane VREF Pad Enable*/ 12364#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 12365#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 12366#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 12367#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C 12368#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 12369#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U 12370 12371/*Byte Lane Internal VREF Enable*/ 12372#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 12373#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 12374#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 12375#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C 12376#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 12377#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U 12378 12379/*Byte Lane Single-End VREF Enable*/ 12380#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 12381#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 12382#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 12383#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C 12384#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 12385#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U 12386 12387/*Reserved. Returns zeros on reads.*/ 12388#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 12389#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 12390#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 12391#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C 12392#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 12393#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U 12394 12395/*External VREF generator REFSEL range select*/ 12396#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 12397#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 12398#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 12399#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 12400#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 12401#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U 12402 12403/*Byte Lane External VREF Select*/ 12404#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 12405#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 12406#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 12407#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C 12408#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 12409#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U 12410 12411/*Single ended VREF generator REFSEL range select*/ 12412#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 12413#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 12414#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 12415#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 12416#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 12417#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U 12418 12419/*Byte Lane Single-End VREF Select*/ 12420#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 12421#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 12422#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 12423#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C 12424#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 12425#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U 12426 12427/*Reserved. Returns zeros on reads.*/ 12428#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 12429#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 12430#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 12431#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 12432#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 12433#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U 12434 12435/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 12436#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 12437#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 12438#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 12439#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C 12440#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 12441#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU 12442 12443/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 12444#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 12445#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 12446#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 12447#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C 12448#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 12449#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U 12450 12451/*Reserved. Returns zeros on reads.*/ 12452#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 12453#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 12454#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 12455#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 12456#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 12457#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U 12458 12459/*Byte Lane internal VREF Select for Rank 3*/ 12460#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 12461#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 12462#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 12463#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 12464#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 12465#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U 12466 12467/*Reserved. Returns zeros on reads.*/ 12468#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 12469#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 12470#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 12471#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 12472#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 12473#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U 12474 12475/*Byte Lane internal VREF Select for Rank 2*/ 12476#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 12477#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 12478#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 12479#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 12480#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 12481#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U 12482 12483/*Reserved. Returns zeros on reads.*/ 12484#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 12485#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 12486#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 12487#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 12488#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 12489#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U 12490 12491/*Byte Lane internal VREF Select for Rank 1*/ 12492#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 12493#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 12494#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 12495#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 12496#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 12497#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U 12498 12499/*Reserved. Returns zeros on reads.*/ 12500#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 12501#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 12502#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 12503#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 12504#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 12505#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U 12506 12507/*Byte Lane internal VREF Select for Rank 0*/ 12508#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 12509#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 12510#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 12511#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 12512#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 12513#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU 12514 12515/*Reserved. Returns zeros on reads.*/ 12516#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 12517#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 12518#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 12519#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 12520#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 12521#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U 12522 12523/*DRAM DQ VREF Select for Rank3*/ 12524#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 12525#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 12526#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 12527#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 12528#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 12529#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U 12530 12531/*Reserved. Returns zeros on reads.*/ 12532#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 12533#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 12534#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 12535#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 12536#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 12537#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U 12538 12539/*DRAM DQ VREF Select for Rank2*/ 12540#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 12541#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 12542#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 12543#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 12544#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 12545#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U 12546 12547/*Reserved. Returns zeros on reads.*/ 12548#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 12549#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 12550#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 12551#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 12552#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 12553#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U 12554 12555/*DRAM DQ VREF Select for Rank1*/ 12556#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 12557#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 12558#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 12559#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 12560#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 12561#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U 12562 12563/*Reserved. Returns zeros on reads.*/ 12564#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 12565#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 12566#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 12567#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 12568#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 12569#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U 12570 12571/*DRAM DQ VREF Select for Rank0*/ 12572#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 12573#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 12574#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 12575#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 12576#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 12577#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU 12578 12579/*Reserved. Return zeroes on reads.*/ 12580#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 12581#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 12582#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 12583#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 12584#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25 12585#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U 12586 12587/*Reserved. Caution, do not write to this register field.*/ 12588#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 12589#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 12590#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 12591#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 12592#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16 12593#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 12594 12595/*Reserved. Return zeroes on reads.*/ 12596#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 12597#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 12598#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 12599#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 12600#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9 12601#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 12602 12603/*Read DQS Gating Delay*/ 12604#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 12605#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 12606#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK 12607#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000 12608#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0 12609#define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU 12610 12611/*Reserved. Return zeroes on reads.*/ 12612#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 12613#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 12614#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 12615#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000 12616#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27 12617#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U 12618 12619/*DQ Write Path Latency Pipeline*/ 12620#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL 12621#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT 12622#undef DDR_PHY_DX4GTR0_WDQSL_MASK 12623#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000 12624#define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24 12625#define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U 12626 12627/*Reserved. Caution, do not write to this register field.*/ 12628#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 12629#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 12630#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 12631#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000 12632#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20 12633#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U 12634 12635/*Write Leveling System Latency*/ 12636#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL 12637#undef DDR_PHY_DX4GTR0_WLSL_SHIFT 12638#undef DDR_PHY_DX4GTR0_WLSL_MASK 12639#define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000 12640#define DDR_PHY_DX4GTR0_WLSL_SHIFT 16 12641#define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U 12642 12643/*Reserved. Return zeroes on reads.*/ 12644#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 12645#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 12646#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 12647#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000 12648#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13 12649#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U 12650 12651/*Reserved. Caution, do not write to this register field.*/ 12652#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 12653#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 12654#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 12655#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000 12656#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8 12657#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U 12658 12659/*Reserved. Return zeroes on reads.*/ 12660#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 12661#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 12662#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 12663#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000 12664#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5 12665#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U 12666 12667/*DQS Gating System Latency*/ 12668#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL 12669#undef DDR_PHY_DX4GTR0_DGSL_SHIFT 12670#undef DDR_PHY_DX4GTR0_DGSL_MASK 12671#define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000 12672#define DDR_PHY_DX4GTR0_DGSL_SHIFT 0 12673#define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU 12674 12675/*Calibration Bypass*/ 12676#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 12677#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 12678#undef DDR_PHY_DX5GCR0_CALBYP_MASK 12679#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 12680#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 12681#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U 12682 12683/*Master Delay Line Enable*/ 12684#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 12685#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 12686#undef DDR_PHY_DX5GCR0_MDLEN_MASK 12687#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 12688#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 12689#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U 12690 12691/*Configurable ODT(TE) Phase Shift*/ 12692#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 12693#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 12694#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 12695#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 12696#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 12697#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U 12698 12699/*DQS Duty Cycle Correction*/ 12700#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 12701#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 12702#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 12703#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 12704#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 12705#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U 12706 12707/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 12708#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 12709#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 12710#undef DDR_PHY_DX5GCR0_RDDLY_MASK 12711#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 12712#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 12713#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U 12714 12715/*Reserved. Return zeroes on reads.*/ 12716#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 12717#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 12718#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 12719#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 12720#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 12721#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U 12722 12723/*DQSNSE Power Down Receiver*/ 12724#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 12725#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 12726#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 12727#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 12728#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 12729#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U 12730 12731/*DQSSE Power Down Receiver*/ 12732#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 12733#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12734#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 12735#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 12736#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 12737#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U 12738 12739/*RTT On Additive Latency*/ 12740#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 12741#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 12742#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 12743#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 12744#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 12745#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U 12746 12747/*RTT Output Hold*/ 12748#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 12749#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 12750#undef DDR_PHY_DX5GCR0_RTTOH_MASK 12751#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 12752#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 12753#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U 12754 12755/*Configurable PDR Phase Shift*/ 12756#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 12757#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 12758#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 12759#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 12760#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 12761#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U 12762 12763/*DQSR Power Down*/ 12764#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 12765#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 12766#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 12767#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 12768#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 12769#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U 12770 12771/*DQSG Power Down Receiver*/ 12772#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 12773#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 12774#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 12775#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 12776#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 12777#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U 12778 12779/*Reserved. Return zeroes on reads.*/ 12780#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 12781#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 12782#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 12783#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 12784#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 12785#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U 12786 12787/*DQSG On-Die Termination*/ 12788#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 12789#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 12790#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 12791#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 12792#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 12793#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U 12794 12795/*DQSG Output Enable*/ 12796#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 12797#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 12798#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 12799#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 12800#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 12801#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U 12802 12803/*Reserved. Return zeroes on reads.*/ 12804#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 12805#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 12806#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 12807#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 12808#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 12809#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U 12810 12811/*Enables the PDR mode for DQ[7:0]*/ 12812#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 12813#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 12814#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 12815#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF 12816#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 12817#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U 12818 12819/*Reserved. Returns zeroes on reads.*/ 12820#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 12821#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 12822#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 12823#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF 12824#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 12825#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U 12826 12827/*Select the delayed or non-delayed read data strobe #*/ 12828#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 12829#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 12830#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 12831#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF 12832#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 12833#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U 12834 12835/*Select the delayed or non-delayed read data strobe*/ 12836#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 12837#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 12838#undef DDR_PHY_DX5GCR1_QSSEL_MASK 12839#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF 12840#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 12841#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U 12842 12843/*Enables Read Data Strobe in a byte lane*/ 12844#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 12845#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 12846#undef DDR_PHY_DX5GCR1_OEEN_MASK 12847#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF 12848#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 12849#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U 12850 12851/*Enables PDR in a byte lane*/ 12852#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 12853#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 12854#undef DDR_PHY_DX5GCR1_PDREN_MASK 12855#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF 12856#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 12857#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U 12858 12859/*Enables ODT/TE in a byte lane*/ 12860#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 12861#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 12862#undef DDR_PHY_DX5GCR1_TEEN_MASK 12863#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF 12864#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 12865#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U 12866 12867/*Enables Write Data strobe in a byte lane*/ 12868#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 12869#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 12870#undef DDR_PHY_DX5GCR1_DSEN_MASK 12871#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF 12872#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 12873#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U 12874 12875/*Enables DM pin in a byte lane*/ 12876#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 12877#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 12878#undef DDR_PHY_DX5GCR1_DMEN_MASK 12879#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF 12880#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 12881#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U 12882 12883/*Enables DQ corresponding to each bit in a byte*/ 12884#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 12885#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 12886#undef DDR_PHY_DX5GCR1_DQEN_MASK 12887#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF 12888#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 12889#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU 12890 12891/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 12892#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 12893#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 12894#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 12895#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 12896#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 12897#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U 12898 12899/*Byte Lane VREF Pad Enable*/ 12900#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 12901#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 12902#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 12903#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C 12904#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 12905#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U 12906 12907/*Byte Lane Internal VREF Enable*/ 12908#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 12909#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 12910#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 12911#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C 12912#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 12913#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U 12914 12915/*Byte Lane Single-End VREF Enable*/ 12916#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 12917#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 12918#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 12919#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C 12920#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 12921#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U 12922 12923/*Reserved. Returns zeros on reads.*/ 12924#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 12925#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 12926#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 12927#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C 12928#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 12929#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U 12930 12931/*External VREF generator REFSEL range select*/ 12932#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 12933#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 12934#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 12935#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 12936#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 12937#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U 12938 12939/*Byte Lane External VREF Select*/ 12940#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 12941#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 12942#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 12943#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C 12944#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 12945#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U 12946 12947/*Single ended VREF generator REFSEL range select*/ 12948#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 12949#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 12950#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 12951#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 12952#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 12953#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U 12954 12955/*Byte Lane Single-End VREF Select*/ 12956#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 12957#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 12958#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 12959#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C 12960#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 12961#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U 12962 12963/*Reserved. Returns zeros on reads.*/ 12964#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 12965#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 12966#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 12967#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 12968#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 12969#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U 12970 12971/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 12972#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 12973#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 12974#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 12975#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C 12976#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 12977#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU 12978 12979/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 12980#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 12981#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 12982#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 12983#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C 12984#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 12985#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U 12986 12987/*Reserved. Returns zeros on reads.*/ 12988#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 12989#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 12990#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 12991#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 12992#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 12993#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U 12994 12995/*Byte Lane internal VREF Select for Rank 3*/ 12996#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 12997#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 12998#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 12999#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 13000#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24
13001#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U 13002 13003/*Reserved. Returns zeros on reads.*/ 13004#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 13005#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 13006#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 13007#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 13008#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 13009#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U 13010 13011/*Byte Lane internal VREF Select for Rank 2*/ 13012#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 13013#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 13014#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 13015#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 13016#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 13017#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U 13018 13019/*Reserved. Returns zeros on reads.*/ 13020#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 13021#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 13022#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 13023#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 13024#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 13025#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U 13026 13027/*Byte Lane internal VREF Select for Rank 1*/ 13028#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 13029#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 13030#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 13031#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 13032#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 13033#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U 13034 13035/*Reserved. Returns zeros on reads.*/ 13036#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 13037#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 13038#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 13039#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 13040#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 13041#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U 13042 13043/*Byte Lane internal VREF Select for Rank 0*/ 13044#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 13045#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 13046#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 13047#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 13048#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 13049#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU 13050 13051/*Reserved. Returns zeros on reads.*/ 13052#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 13053#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 13054#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 13055#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 13056#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 13057#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U 13058 13059/*DRAM DQ VREF Select for Rank3*/ 13060#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 13061#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 13062#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 13063#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 13064#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 13065#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U 13066 13067/*Reserved. Returns zeros on reads.*/ 13068#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 13069#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 13070#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 13071#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 13072#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 13073#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U 13074 13075/*DRAM DQ VREF Select for Rank2*/ 13076#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 13077#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 13078#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 13079#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 13080#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 13081#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U 13082 13083/*Reserved. Returns zeros on reads.*/ 13084#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 13085#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 13086#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 13087#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 13088#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 13089#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U 13090 13091/*DRAM DQ VREF Select for Rank1*/ 13092#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 13093#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 13094#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 13095#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 13096#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 13097#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U 13098 13099/*Reserved. Returns zeros on reads.*/ 13100#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 13101#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 13102#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 13103#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 13104#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 13105#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U 13106 13107/*DRAM DQ VREF Select for Rank0*/ 13108#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 13109#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 13110#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 13111#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 13112#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 13113#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU 13114 13115/*Reserved. Return zeroes on reads.*/ 13116#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 13117#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 13118#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 13119#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 13120#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25 13121#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U 13122 13123/*Reserved. Caution, do not write to this register field.*/ 13124#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 13125#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 13126#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 13127#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 13128#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16 13129#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 13130 13131/*Reserved. Return zeroes on reads.*/ 13132#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 13133#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 13134#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 13135#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 13136#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9 13137#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 13138 13139/*Read DQS Gating Delay*/ 13140#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 13141#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 13142#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK 13143#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000 13144#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0 13145#define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU 13146 13147/*Reserved. Return zeroes on reads.*/ 13148#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 13149#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 13150#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 13151#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000 13152#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27 13153#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U 13154 13155/*DQ Write Path Latency Pipeline*/ 13156#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL 13157#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT 13158#undef DDR_PHY_DX5GTR0_WDQSL_MASK 13159#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000 13160#define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24 13161#define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U 13162 13163/*Reserved. Caution, do not write to this register field.*/ 13164#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 13165#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 13166#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 13167#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000 13168#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20 13169#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U 13170 13171/*Write Leveling System Latency*/ 13172#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL 13173#undef DDR_PHY_DX5GTR0_WLSL_SHIFT 13174#undef DDR_PHY_DX5GTR0_WLSL_MASK 13175#define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000 13176#define DDR_PHY_DX5GTR0_WLSL_SHIFT 16 13177#define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U 13178 13179/*Reserved. Return zeroes on reads.*/ 13180#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 13181#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13182#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 13183#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000 13184#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13 13185#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U 13186 13187/*Reserved. Caution, do not write to this register field.*/ 13188#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 13189#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 13190#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 13191#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000 13192#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8 13193#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U 13194 13195/*Reserved. Return zeroes on reads.*/ 13196#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 13197#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 13198#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 13199#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000 13200#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5 13201#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U 13202 13203/*DQS Gating System Latency*/ 13204#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL 13205#undef DDR_PHY_DX5GTR0_DGSL_SHIFT 13206#undef DDR_PHY_DX5GTR0_DGSL_MASK 13207#define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000 13208#define DDR_PHY_DX5GTR0_DGSL_SHIFT 0 13209#define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU 13210 13211/*Calibration Bypass*/ 13212#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 13213#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 13214#undef DDR_PHY_DX6GCR0_CALBYP_MASK 13215#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 13216#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 13217#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U 13218 13219/*Master Delay Line Enable*/ 13220#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 13221#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 13222#undef DDR_PHY_DX6GCR0_MDLEN_MASK 13223#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 13224#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 13225#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U 13226 13227/*Configurable ODT(TE) Phase Shift*/ 13228#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 13229#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 13230#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 13231#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 13232#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 13233#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U 13234 13235/*DQS Duty Cycle Correction*/ 13236#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 13237#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 13238#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 13239#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 13240#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 13241#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U 13242 13243/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 13244#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 13245#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 13246#undef DDR_PHY_DX6GCR0_RDDLY_MASK 13247#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 13248#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 13249#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U 13250 13251/*Reserved. Return zeroes on reads.*/ 13252#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 13253#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 13254#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 13255#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 13256#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 13257#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U 13258 13259/*DQSNSE Power Down Receiver*/ 13260#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 13261#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13262#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 13263#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 13264#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 13265#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U 13266 13267/*DQSSE Power Down Receiver*/ 13268#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 13269#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 13270#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 13271#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 13272#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 13273#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U 13274 13275/*RTT On Additive Latency*/ 13276#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 13277#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 13278#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 13279#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 13280#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 13281#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U 13282 13283/*RTT Output Hold*/ 13284#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 13285#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 13286#undef DDR_PHY_DX6GCR0_RTTOH_MASK 13287#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 13288#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 13289#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U 13290 13291/*Configurable PDR Phase Shift*/ 13292#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 13293#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 13294#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 13295#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 13296#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 13297#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U 13298 13299/*DQSR Power Down*/ 13300#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 13301#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 13302#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 13303#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 13304#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 13305#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U 13306 13307/*DQSG Power Down Receiver*/ 13308#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 13309#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 13310#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 13311#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 13312#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 13313#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U 13314 13315/*Reserved. Return zeroes on reads.*/ 13316#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 13317#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 13318#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 13319#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 13320#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 13321#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U 13322 13323/*DQSG On-Die Termination*/ 13324#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 13325#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 13326#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 13327#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 13328#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 13329#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U 13330 13331/*DQSG Output Enable*/ 13332#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 13333#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 13334#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 13335#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 13336#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 13337#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U 13338 13339/*Reserved. Return zeroes on reads.*/ 13340#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 13341#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 13342#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 13343#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 13344#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 13345#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U 13346 13347/*Enables the PDR mode for DQ[7:0]*/ 13348#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 13349#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 13350#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 13351#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF 13352#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 13353#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U 13354 13355/*Reserved. Returns zeroes on reads.*/ 13356#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 13357#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 13358#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 13359#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF 13360#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 13361#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U 13362 13363/*Select the delayed or non-delayed read data strobe #*/ 13364#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 13365#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 13366#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 13367#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF 13368#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 13369#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U 13370 13371/*Select the delayed or non-delayed read data strobe*/ 13372#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 13373#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 13374#undef DDR_PHY_DX6GCR1_QSSEL_MASK 13375#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF 13376#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 13377#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U 13378 13379/*Enables Read Data Strobe in a byte lane*/ 13380#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 13381#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 13382#undef DDR_PHY_DX6GCR1_OEEN_MASK 13383#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF 13384#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 13385#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U 13386 13387/*Enables PDR in a byte lane*/ 13388#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 13389#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 13390#undef DDR_PHY_DX6GCR1_PDREN_MASK 13391#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF 13392#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 13393#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U 13394 13395/*Enables ODT/TE in a byte lane*/ 13396#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 13397#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 13398#undef DDR_PHY_DX6GCR1_TEEN_MASK 13399#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF 13400#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 13401#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U 13402 13403/*Enables Write Data strobe in a byte lane*/ 13404#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 13405#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 13406#undef DDR_PHY_DX6GCR1_DSEN_MASK 13407#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF 13408#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 13409#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U 13410 13411/*Enables DM pin in a byte lane*/ 13412#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 13413#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 13414#undef DDR_PHY_DX6GCR1_DMEN_MASK 13415#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF 13416#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 13417#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U 13418 13419/*Enables DQ corresponding to each bit in a byte*/ 13420#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 13421#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 13422#undef DDR_PHY_DX6GCR1_DQEN_MASK 13423#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF 13424#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 13425#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU 13426 13427/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 13428#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 13429#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 13430#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 13431#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 13432#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 13433#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U 13434 13435/*Byte Lane VREF Pad Enable*/ 13436#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 13437#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 13438#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 13439#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C 13440#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 13441#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U 13442 13443/*Byte Lane Internal VREF Enable*/ 13444#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 13445#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 13446#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 13447#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C 13448#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 13449#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U 13450 13451/*Byte Lane Single-End VREF Enable*/ 13452#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 13453#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 13454#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 13455#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C 13456#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 13457#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U 13458 13459/*Reserved. Returns zeros on reads.*/ 13460#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 13461#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 13462#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 13463#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C 13464#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 13465#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U 13466 13467/*External VREF generator REFSEL range select*/ 13468#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 13469#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 13470#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 13471#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 13472#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 13473#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U 13474 13475/*Byte Lane External VREF Select*/ 13476#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 13477#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 13478#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 13479#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C 13480#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 13481#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U 13482 13483/*Single ended VREF generator REFSEL range select*/ 13484#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 13485#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 13486#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 13487#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 13488#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 13489#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U 13490 13491/*Byte Lane Single-End VREF Select*/ 13492#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 13493#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 13494#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 13495#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C 13496#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 13497#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U 13498 13499/*Reserved. Returns zeros on reads.*/ 13500#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 13501#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 13502#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 13503#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 13504#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 13505#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U 13506 13507/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 13508#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 13509#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 13510#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 13511#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C 13512#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 13513#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU 13514 13515/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 13516#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 13517#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 13518#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 13519#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C 13520#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 13521#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U 13522 13523/*Reserved. Returns zeros on reads.*/ 13524#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 13525#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 13526#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 13527#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 13528#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 13529#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U 13530 13531/*Byte Lane internal VREF Select for Rank 3*/ 13532#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 13533#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 13534#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 13535#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 13536#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 13537#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U 13538 13539/*Reserved. Returns zeros on reads.*/ 13540#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 13541#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 13542#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 13543#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 13544#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 13545#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U 13546 13547/*Byte Lane internal VREF Select for Rank 2*/ 13548#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 13549#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 13550#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 13551#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 13552#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 13553#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U 13554 13555/*Reserved. Returns zeros on reads.*/ 13556#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 13557#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 13558#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 13559#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 13560#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 13561#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U 13562 13563/*Byte Lane internal VREF Select for Rank 1*/ 13564#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 13565#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 13566#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 13567#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 13568#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 13569#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U 13570 13571/*Reserved. Returns zeros on reads.*/ 13572#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 13573#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 13574#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 13575#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 13576#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 13577#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U 13578 13579/*Byte Lane internal VREF Select for Rank 0*/ 13580#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 13581#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 13582#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 13583#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 13584#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 13585#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU 13586 13587/*Reserved. Returns zeros on reads.*/ 13588#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 13589#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 13590#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 13591#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 13592#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 13593#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U 13594 13595/*DRAM DQ VREF Select for Rank3*/ 13596#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 13597#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 13598#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 13599#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 13600#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 13601#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U 13602 13603/*Reserved. Returns zeros on reads.*/ 13604#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 13605#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 13606#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 13607#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 13608#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 13609#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U 13610 13611/*DRAM DQ VREF Select for Rank2*/ 13612#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 13613#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 13614#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 13615#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 13616#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 13617#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U 13618 13619/*Reserved. Returns zeros on reads.*/ 13620#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 13621#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 13622#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 13623#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 13624#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 13625#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U 13626 13627/*DRAM DQ VREF Select for Rank1*/ 13628#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 13629#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 13630#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 13631#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 13632#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 13633#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U 13634 13635/*Reserved. Returns zeros on reads.*/ 13636#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 13637#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 13638#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 13639#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 13640#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 13641#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U 13642 13643/*DRAM DQ VREF Select for Rank0*/ 13644#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 13645#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 13646#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 13647#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 13648#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 13649#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU 13650 13651/*Reserved. Return zeroes on reads.*/ 13652#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 13653#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 13654#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 13655#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 13656#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25 13657#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U 13658 13659/*Reserved. Caution, do not write to this register field.*/ 13660#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 13661#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 13662#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 13663#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 13664#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16 13665#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 13666 13667/*Reserved. Return zeroes on reads.*/ 13668#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 13669#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 13670#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 13671#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 13672#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9 13673#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 13674 13675/*Read DQS Gating Delay*/ 13676#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 13677#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 13678#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK 13679#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000 13680#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0 13681#define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU 13682 13683/*Reserved. Return zeroes on reads.*/ 13684#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 13685#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 13686#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 13687#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000 13688#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27 13689#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U 13690 13691/*DQ Write Path Latency Pipeline*/ 13692#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL 13693#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT 13694#undef DDR_PHY_DX6GTR0_WDQSL_MASK 13695#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000 13696#define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24 13697#define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U 13698 13699/*Reserved. Caution, do not write to this register field.*/ 13700#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 13701#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 13702#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 13703#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000 13704#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20 13705#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U 13706 13707/*Write Leveling System Latency*/ 13708#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL 13709#undef DDR_PHY_DX6GTR0_WLSL_SHIFT 13710#undef DDR_PHY_DX6GTR0_WLSL_MASK 13711#define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000 13712#define DDR_PHY_DX6GTR0_WLSL_SHIFT 16 13713#define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U 13714 13715/*Reserved. Return zeroes on reads.*/ 13716#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 13717#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13718#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 13719#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000 13720#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13 13721#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U 13722 13723/*Reserved. Caution, do not write to this register field.*/ 13724#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 13725#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 13726#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 13727#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000 13728#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8 13729#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U 13730 13731/*Reserved. Return zeroes on reads.*/ 13732#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 13733#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 13734#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 13735#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000 13736#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5 13737#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U 13738 13739/*DQS Gating System Latency*/ 13740#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL 13741#undef DDR_PHY_DX6GTR0_DGSL_SHIFT 13742#undef DDR_PHY_DX6GTR0_DGSL_MASK 13743#define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000 13744#define DDR_PHY_DX6GTR0_DGSL_SHIFT 0 13745#define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU 13746 13747/*Calibration Bypass*/ 13748#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 13749#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 13750#undef DDR_PHY_DX7GCR0_CALBYP_MASK 13751#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 13752#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 13753#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U 13754 13755/*Master Delay Line Enable*/ 13756#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 13757#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 13758#undef DDR_PHY_DX7GCR0_MDLEN_MASK 13759#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 13760#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 13761#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U 13762 13763/*Configurable ODT(TE) Phase Shift*/ 13764#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 13765#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 13766#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 13767#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 13768#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 13769#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U 13770 13771/*DQS Duty Cycle Correction*/ 13772#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 13773#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 13774#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 13775#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 13776#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 13777#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U 13778 13779/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 13780#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 13781#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 13782#undef DDR_PHY_DX7GCR0_RDDLY_MASK 13783#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 13784#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 13785#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U 13786 13787/*Reserved. Return zeroes on reads.*/ 13788#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 13789#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 13790#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 13791#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 13792#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 13793#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U 13794 13795/*DQSNSE Power Down Receiver*/ 13796#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 13797#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13798#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 13799#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 13800#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 13801#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U 13802 13803/*DQSSE Power Down Receiver*/ 13804#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 13805#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 13806#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 13807#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 13808#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 13809#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U 13810 13811/*RTT On Additive Latency*/ 13812#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 13813#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 13814#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 13815#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 13816#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 13817#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U 13818 13819/*RTT Output Hold*/ 13820#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 13821#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 13822#undef DDR_PHY_DX7GCR0_RTTOH_MASK 13823#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 13824#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 13825#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U 13826 13827/*Configurable PDR Phase Shift*/ 13828#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 13829#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 13830#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 13831#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 13832#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 13833#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U 13834 13835/*DQSR Power Down*/ 13836#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 13837#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 13838#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 13839#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 13840#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 13841#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U 13842 13843/*DQSG Power Down Receiver*/ 13844#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 13845#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 13846#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 13847#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 13848#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 13849#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U 13850 13851/*Reserved. Return zeroes on reads.*/ 13852#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 13853#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 13854#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 13855#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 13856#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 13857#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U 13858 13859/*DQSG On-Die Termination*/ 13860#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 13861#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 13862#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 13863#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 13864#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 13865#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U 13866 13867/*DQSG Output Enable*/ 13868#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 13869#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 13870#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 13871#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 13872#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 13873#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U 13874 13875/*Reserved. Return zeroes on reads.*/ 13876#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 13877#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 13878#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 13879#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 13880#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 13881#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U 13882 13883/*Enables the PDR mode for DQ[7:0]*/ 13884#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 13885#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 13886#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 13887#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF 13888#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 13889#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U 13890 13891/*Reserved. Returns zeroes on reads.*/ 13892#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 13893#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 13894#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 13895#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF 13896#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 13897#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U 13898 13899/*Select the delayed or non-delayed read data strobe #*/ 13900#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 13901#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 13902#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 13903#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF 13904#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 13905#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U 13906 13907/*Select the delayed or non-delayed read data strobe*/ 13908#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 13909#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 13910#undef DDR_PHY_DX7GCR1_QSSEL_MASK 13911#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF 13912#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 13913#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U 13914 13915/*Enables Read Data Strobe in a byte lane*/ 13916#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 13917#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 13918#undef DDR_PHY_DX7GCR1_OEEN_MASK 13919#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF 13920#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 13921#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U 13922 13923/*Enables PDR in a byte lane*/ 13924#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 13925#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 13926#undef DDR_PHY_DX7GCR1_PDREN_MASK 13927#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF 13928#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 13929#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U 13930 13931/*Enables ODT/TE in a byte lane*/ 13932#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 13933#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 13934#undef DDR_PHY_DX7GCR1_TEEN_MASK 13935#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF 13936#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 13937#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U 13938 13939/*Enables Write Data strobe in a byte lane*/ 13940#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 13941#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 13942#undef DDR_PHY_DX7GCR1_DSEN_MASK 13943#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF 13944#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 13945#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U 13946 13947/*Enables DM pin in a byte lane*/ 13948#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 13949#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 13950#undef DDR_PHY_DX7GCR1_DMEN_MASK 13951#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF 13952#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 13953#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U 13954 13955/*Enables DQ corresponding to each bit in a byte*/ 13956#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 13957#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 13958#undef DDR_PHY_DX7GCR1_DQEN_MASK 13959#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF 13960#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 13961#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU 13962 13963/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 13964#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 13965#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 13966#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 13967#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 13968#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 13969#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U 13970 13971/*Byte Lane VREF Pad Enable*/ 13972#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 13973#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 13974#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 13975#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C 13976#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 13977#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U 13978 13979/*Byte Lane Internal VREF Enable*/ 13980#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 13981#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 13982#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 13983#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C 13984#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 13985#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U 13986 13987/*Byte Lane Single-End VREF Enable*/ 13988#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 13989#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 13990#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 13991#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C 13992#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 13993#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U 13994 13995/*Reserved. Returns zeros on reads.*/ 13996#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 13997#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 13998#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 13999#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C 14000#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24
14001#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U 14002 14003/*External VREF generator REFSEL range select*/ 14004#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 14005#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 14006#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 14007#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 14008#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 14009#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U 14010 14011/*Byte Lane External VREF Select*/ 14012#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 14013#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 14014#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 14015#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C 14016#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 14017#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U 14018 14019/*Single ended VREF generator REFSEL range select*/ 14020#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 14021#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 14022#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 14023#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 14024#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 14025#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U 14026 14027/*Byte Lane Single-End VREF Select*/ 14028#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 14029#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 14030#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 14031#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C 14032#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 14033#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U 14034 14035/*Reserved. Returns zeros on reads.*/ 14036#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 14037#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 14038#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 14039#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 14040#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 14041#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U 14042 14043/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 14044#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 14045#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 14046#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 14047#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C 14048#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 14049#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU 14050 14051/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 14052#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 14053#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 14054#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 14055#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C 14056#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 14057#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U 14058 14059/*Reserved. Returns zeros on reads.*/ 14060#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 14061#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 14062#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 14063#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 14064#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 14065#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U 14066 14067/*Byte Lane internal VREF Select for Rank 3*/ 14068#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 14069#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 14070#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 14071#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 14072#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 14073#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U 14074 14075/*Reserved. Returns zeros on reads.*/ 14076#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 14077#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 14078#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 14079#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 14080#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 14081#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U 14082 14083/*Byte Lane internal VREF Select for Rank 2*/ 14084#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 14085#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 14086#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 14087#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 14088#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 14089#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U 14090 14091/*Reserved. Returns zeros on reads.*/ 14092#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 14093#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 14094#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 14095#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 14096#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 14097#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U 14098 14099/*Byte Lane internal VREF Select for Rank 1*/ 14100#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 14101#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 14102#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 14103#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 14104#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 14105#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U 14106 14107/*Reserved. Returns zeros on reads.*/ 14108#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 14109#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 14110#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 14111#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 14112#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 14113#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U 14114 14115/*Byte Lane internal VREF Select for Rank 0*/ 14116#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 14117#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 14118#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 14119#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 14120#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 14121#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU 14122 14123/*Reserved. Returns zeros on reads.*/ 14124#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 14125#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 14126#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 14127#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 14128#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 14129#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U 14130 14131/*DRAM DQ VREF Select for Rank3*/ 14132#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 14133#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 14134#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 14135#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 14136#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 14137#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U 14138 14139/*Reserved. Returns zeros on reads.*/ 14140#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 14141#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 14142#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 14143#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 14144#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 14145#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U 14146 14147/*DRAM DQ VREF Select for Rank2*/ 14148#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 14149#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 14150#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 14151#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 14152#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 14153#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U 14154 14155/*Reserved. Returns zeros on reads.*/ 14156#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 14157#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14158#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 14159#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 14160#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 14161#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U 14162 14163/*DRAM DQ VREF Select for Rank1*/ 14164#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 14165#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 14166#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 14167#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 14168#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 14169#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U 14170 14171/*Reserved. Returns zeros on reads.*/ 14172#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 14173#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 14174#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 14175#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 14176#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 14177#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U 14178 14179/*DRAM DQ VREF Select for Rank0*/ 14180#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 14181#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 14182#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 14183#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 14184#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 14185#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU 14186 14187/*Reserved. Return zeroes on reads.*/ 14188#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 14189#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 14190#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 14191#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 14192#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25 14193#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U 14194 14195/*Reserved. Caution, do not write to this register field.*/ 14196#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 14197#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 14198#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 14199#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 14200#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16 14201#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 14202 14203/*Reserved. Return zeroes on reads.*/ 14204#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 14205#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 14206#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 14207#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 14208#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9 14209#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 14210 14211/*Read DQS Gating Delay*/ 14212#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 14213#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 14214#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK 14215#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000 14216#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0 14217#define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU 14218 14219/*Reserved. Return zeroes on reads.*/ 14220#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 14221#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 14222#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 14223#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000 14224#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27 14225#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U 14226 14227/*DQ Write Path Latency Pipeline*/ 14228#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL 14229#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT 14230#undef DDR_PHY_DX7GTR0_WDQSL_MASK 14231#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000 14232#define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24 14233#define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U 14234 14235/*Reserved. Caution, do not write to this register field.*/ 14236#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 14237#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 14238#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 14239#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000 14240#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20 14241#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U 14242 14243/*Write Leveling System Latency*/ 14244#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL 14245#undef DDR_PHY_DX7GTR0_WLSL_SHIFT 14246#undef DDR_PHY_DX7GTR0_WLSL_MASK 14247#define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000 14248#define DDR_PHY_DX7GTR0_WLSL_SHIFT 16 14249#define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U 14250 14251/*Reserved. Return zeroes on reads.*/ 14252#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 14253#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 14254#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 14255#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000 14256#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13 14257#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U 14258 14259/*Reserved. Caution, do not write to this register field.*/ 14260#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 14261#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 14262#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 14263#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000 14264#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8 14265#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U 14266 14267/*Reserved. Return zeroes on reads.*/ 14268#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 14269#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 14270#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 14271#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000 14272#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5 14273#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U 14274 14275/*DQS Gating System Latency*/ 14276#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL 14277#undef DDR_PHY_DX7GTR0_DGSL_SHIFT 14278#undef DDR_PHY_DX7GTR0_DGSL_MASK 14279#define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000 14280#define DDR_PHY_DX7GTR0_DGSL_SHIFT 0 14281#define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU 14282 14283/*Calibration Bypass*/ 14284#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 14285#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 14286#undef DDR_PHY_DX8GCR0_CALBYP_MASK 14287#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 14288#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 14289#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U 14290 14291/*Master Delay Line Enable*/ 14292#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 14293#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 14294#undef DDR_PHY_DX8GCR0_MDLEN_MASK 14295#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 14296#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 14297#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U 14298 14299/*Configurable ODT(TE) Phase Shift*/ 14300#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 14301#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 14302#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 14303#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 14304#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 14305#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U 14306 14307/*DQS Duty Cycle Correction*/ 14308#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 14309#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 14310#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 14311#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 14312#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 14313#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U 14314 14315/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ 14316#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 14317#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 14318#undef DDR_PHY_DX8GCR0_RDDLY_MASK 14319#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 14320#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 14321#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U 14322 14323/*Reserved. Return zeroes on reads.*/ 14324#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 14325#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14326#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 14327#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 14328#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 14329#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U 14330 14331/*DQSNSE Power Down Receiver*/ 14332#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 14333#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 14334#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 14335#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 14336#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 14337#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U 14338 14339/*DQSSE Power Down Receiver*/ 14340#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 14341#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 14342#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 14343#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 14344#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 14345#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U 14346 14347/*RTT On Additive Latency*/ 14348#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 14349#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 14350#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 14351#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 14352#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 14353#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U 14354 14355/*RTT Output Hold*/ 14356#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 14357#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 14358#undef DDR_PHY_DX8GCR0_RTTOH_MASK 14359#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 14360#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 14361#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U 14362 14363/*Configurable PDR Phase Shift*/ 14364#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 14365#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 14366#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 14367#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 14368#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 14369#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U 14370 14371/*DQSR Power Down*/ 14372#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 14373#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 14374#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 14375#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 14376#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 14377#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U 14378 14379/*DQSG Power Down Receiver*/ 14380#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 14381#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 14382#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 14383#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 14384#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 14385#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U 14386 14387/*Reserved. Return zeroes on reads.*/ 14388#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 14389#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 14390#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 14391#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 14392#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 14393#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U 14394 14395/*DQSG On-Die Termination*/ 14396#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 14397#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 14398#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 14399#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 14400#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 14401#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U 14402 14403/*DQSG Output Enable*/ 14404#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 14405#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 14406#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 14407#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 14408#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 14409#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U 14410 14411/*Reserved. Return zeroes on reads.*/ 14412#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 14413#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 14414#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 14415#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 14416#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 14417#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U 14418 14419/*Enables the PDR mode for DQ[7:0]*/ 14420#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 14421#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 14422#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 14423#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF 14424#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 14425#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U 14426 14427/*Reserved. Returns zeroes on reads.*/ 14428#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 14429#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 14430#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 14431#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF 14432#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 14433#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U 14434 14435/*Select the delayed or non-delayed read data strobe #*/ 14436#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 14437#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14438#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 14439#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF 14440#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 14441#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U 14442 14443/*Select the delayed or non-delayed read data strobe*/ 14444#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 14445#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 14446#undef DDR_PHY_DX8GCR1_QSSEL_MASK 14447#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF 14448#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 14449#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U 14450 14451/*Enables Read Data Strobe in a byte lane*/ 14452#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 14453#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 14454#undef DDR_PHY_DX8GCR1_OEEN_MASK 14455#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF 14456#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 14457#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U 14458 14459/*Enables PDR in a byte lane*/ 14460#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 14461#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 14462#undef DDR_PHY_DX8GCR1_PDREN_MASK 14463#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF 14464#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 14465#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U 14466 14467/*Enables ODT/TE in a byte lane*/ 14468#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 14469#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 14470#undef DDR_PHY_DX8GCR1_TEEN_MASK 14471#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF 14472#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 14473#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U 14474 14475/*Enables Write Data strobe in a byte lane*/ 14476#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 14477#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 14478#undef DDR_PHY_DX8GCR1_DSEN_MASK 14479#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF 14480#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 14481#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U 14482 14483/*Enables DM pin in a byte lane*/ 14484#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 14485#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 14486#undef DDR_PHY_DX8GCR1_DMEN_MASK 14487#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF 14488#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 14489#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U 14490 14491/*Enables DQ corresponding to each bit in a byte*/ 14492#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 14493#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 14494#undef DDR_PHY_DX8GCR1_DQEN_MASK 14495#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF 14496#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 14497#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU 14498 14499/*Byte lane VREF IOM (Used only by D4MU IOs)*/ 14500#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 14501#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 14502#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 14503#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C 14504#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 14505#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U 14506 14507/*Byte Lane VREF Pad Enable*/ 14508#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 14509#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 14510#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 14511#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C 14512#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 14513#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U 14514 14515/*Byte Lane Internal VREF Enable*/ 14516#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 14517#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 14518#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 14519#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C 14520#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 14521#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U 14522 14523/*Byte Lane Single-End VREF Enable*/ 14524#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 14525#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 14526#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 14527#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C 14528#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 14529#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U 14530 14531/*Reserved. Returns zeros on reads.*/ 14532#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 14533#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 14534#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 14535#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C 14536#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 14537#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U 14538 14539/*External VREF generator REFSEL range select*/ 14540#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 14541#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 14542#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 14543#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C 14544#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 14545#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U 14546 14547/*Byte Lane External VREF Select*/ 14548#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 14549#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 14550#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 14551#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C 14552#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 14553#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U 14554 14555/*Single ended VREF generator REFSEL range select*/ 14556#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 14557#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 14558#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 14559#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C 14560#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 14561#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U 14562 14563/*Byte Lane Single-End VREF Select*/ 14564#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 14565#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 14566#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 14567#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C 14568#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 14569#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U 14570 14571/*Reserved. Returns zeros on reads.*/ 14572#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 14573#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 14574#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 14575#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C 14576#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 14577#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U 14578 14579/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ 14580#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 14581#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 14582#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 14583#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C 14584#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 14585#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU 14586 14587/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ 14588#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 14589#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 14590#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 14591#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C 14592#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 14593#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U 14594 14595/*Reserved. Returns zeros on reads.*/ 14596#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 14597#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 14598#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 14599#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 14600#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 14601#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U 14602 14603/*Byte Lane internal VREF Select for Rank 3*/ 14604#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 14605#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 14606#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 14607#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 14608#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 14609#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U 14610 14611/*Reserved. Returns zeros on reads.*/ 14612#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 14613#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 14614#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 14615#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 14616#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 14617#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U 14618 14619/*Byte Lane internal VREF Select for Rank 2*/ 14620#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 14621#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 14622#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 14623#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 14624#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 14625#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U 14626 14627/*Reserved. Returns zeros on reads.*/ 14628#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 14629#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 14630#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 14631#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 14632#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 14633#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U 14634 14635/*Byte Lane internal VREF Select for Rank 1*/ 14636#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 14637#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 14638#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 14639#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 14640#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 14641#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U 14642 14643/*Reserved. Returns zeros on reads.*/ 14644#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 14645#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 14646#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 14647#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 14648#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 14649#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U 14650 14651/*Byte Lane internal VREF Select for Rank 0*/ 14652#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 14653#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 14654#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 14655#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 14656#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 14657#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU 14658 14659/*Reserved. Returns zeros on reads.*/ 14660#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 14661#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 14662#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 14663#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 14664#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 14665#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U 14666 14667/*DRAM DQ VREF Select for Rank3*/ 14668#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 14669#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 14670#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 14671#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 14672#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 14673#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U 14674 14675/*Reserved. Returns zeros on reads.*/ 14676#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 14677#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 14678#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 14679#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 14680#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 14681#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U 14682 14683/*DRAM DQ VREF Select for Rank2*/ 14684#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 14685#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 14686#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 14687#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 14688#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 14689#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U 14690 14691/*Reserved. Returns zeros on reads.*/ 14692#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 14693#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14694#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 14695#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 14696#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 14697#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U 14698 14699/*DRAM DQ VREF Select for Rank1*/ 14700#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 14701#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 14702#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 14703#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 14704#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 14705#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U 14706 14707/*Reserved. Returns zeros on reads.*/ 14708#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 14709#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 14710#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 14711#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 14712#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 14713#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U 14714 14715/*DRAM DQ VREF Select for Rank0*/ 14716#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 14717#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 14718#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 14719#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 14720#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 14721#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU 14722 14723/*Reserved. Return zeroes on reads.*/ 14724#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 14725#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 14726#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 14727#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 14728#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25 14729#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U 14730 14731/*Reserved. Caution, do not write to this register field.*/ 14732#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 14733#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 14734#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 14735#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 14736#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16 14737#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U 14738 14739/*Reserved. Return zeroes on reads.*/ 14740#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 14741#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 14742#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 14743#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 14744#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9 14745#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U 14746 14747/*Read DQS Gating Delay*/ 14748#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 14749#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 14750#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK 14751#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000 14752#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0 14753#define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU 14754 14755/*Reserved. Return zeroes on reads.*/ 14756#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 14757#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 14758#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 14759#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000 14760#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27 14761#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U 14762 14763/*DQ Write Path Latency Pipeline*/ 14764#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL 14765#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT 14766#undef DDR_PHY_DX8GTR0_WDQSL_MASK 14767#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000 14768#define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24 14769#define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U 14770 14771/*Reserved. Caution, do not write to this register field.*/ 14772#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 14773#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 14774#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 14775#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000 14776#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20 14777#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U 14778 14779/*Write Leveling System Latency*/ 14780#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL 14781#undef DDR_PHY_DX8GTR0_WLSL_SHIFT 14782#undef DDR_PHY_DX8GTR0_WLSL_MASK 14783#define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000 14784#define DDR_PHY_DX8GTR0_WLSL_SHIFT 16 14785#define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U 14786 14787/*Reserved. Return zeroes on reads.*/ 14788#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 14789#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 14790#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 14791#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000 14792#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13 14793#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U 14794 14795/*Reserved. Caution, do not write to this register field.*/ 14796#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 14797#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 14798#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 14799#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000 14800#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8 14801#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U 14802 14803/*Reserved. Return zeroes on reads.*/ 14804#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 14805#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 14806#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 14807#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000 14808#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5 14809#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U 14810 14811/*DQS Gating System Latency*/ 14812#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL 14813#undef DDR_PHY_DX8GTR0_DGSL_SHIFT 14814#undef DDR_PHY_DX8GTR0_DGSL_MASK 14815#define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000 14816#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0 14817#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU 14818 14819/*Reserved. Return zeroes on reads.*/ 14820#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 14821#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 14822#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 14823#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE 14824#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 14825#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U 14826 14827/*Enable Clock Gating for DX ddr_clk*/ 14828#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 14829#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 14830#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 14831#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE 14832#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 14833#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U 14834 14835/*Enable Clock Gating for DX ctl_rd_clk*/ 14836#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 14837#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 14838#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 14839#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE 14840#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 14841#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U 14842 14843/*Enable Clock Gating for DX ctl_clk*/ 14844#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 14845#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 14846#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 14847#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE 14848#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 14849#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U 14850 14851/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ 14852#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 14853#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 14854#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 14855#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE 14856#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 14857#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U 14858 14859/*Loopback Mode*/ 14860#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 14861#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 14862#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK 14863#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE 14864#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 14865#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U 14866 14867/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ 14868#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 14869#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 14870#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 14871#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE 14872#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 14873#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U 14874 14875/*Loopback DQS Gating*/ 14876#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 14877#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 14878#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK 14879#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE 14880#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 14881#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U 14882 14883/*Loopback DQS Shift*/ 14884#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 14885#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 14886#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK 14887#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE 14888#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 14889#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U 14890 14891/*PHY High-Speed Reset*/ 14892#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 14893#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 14894#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK 14895#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE 14896#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 14897#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U 14898 14899/*PHY FIFO Reset*/ 14900#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 14901#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 14902#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK 14903#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE 14904#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 14905#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U 14906 14907/*Delay Line Test Start*/ 14908#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 14909#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14910#undef DDR_PHY_DX8SL0OSC_DLTST_MASK 14911#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE 14912#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 14913#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U 14914 14915/*Delay Line Test Mode*/ 14916#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 14917#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 14918#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK 14919#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE 14920#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 14921#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U 14922 14923/*Reserved. Caution, do not write to this register field.*/ 14924#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 14925#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 14926#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 14927#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE 14928#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 14929#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U 14930 14931/*Oscillator Mode Write-Data Delay Line Select*/ 14932#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 14933#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 14934#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 14935#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE 14936#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 14937#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U 14938 14939/*Reserved. Caution, do not write to this register field.*/ 14940#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 14941#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 14942#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 14943#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE 14944#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 14945#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U 14946 14947/*Oscillator Mode Write-Leveling Delay Line Select*/ 14948#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 14949#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 14950#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK 14951#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE 14952#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 14953#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U 14954 14955/*Oscillator Mode Division*/ 14956#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 14957#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 14958#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK 14959#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE 14960#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 14961#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU 14962 14963/*Oscillator Enable*/ 14964#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 14965#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 14966#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK 14967#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE 14968#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 14969#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U 14970 14971/*Reserved. Return zeroes on reads.*/ 14972#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 14973#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 14974#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 14975#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 14976#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 14977#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U 14978 14979/*Read Path Rise-to-Rise Mode*/ 14980#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 14981#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 14982#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 14983#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 14984#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 14985#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U 14986 14987/*Reserved. Return zeroes on reads.*/ 14988#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 14989#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 14990#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 14991#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 14992#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 14993#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U 14994 14995/*Write Path Rise-to-Rise Mode*/ 14996#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 14997#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 14998#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 14999#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 15000#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21
15001#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U 15002 15003/*DQS Gate Extension*/ 15004#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 15005#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 15006#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 15007#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 15008#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 15009#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U 15010 15011/*Low Power PLL Power Down*/ 15012#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 15013#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 15014#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 15015#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 15016#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 15017#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U 15018 15019/*Low Power I/O Power Down*/ 15020#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 15021#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 15022#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 15023#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 15024#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 15025#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U 15026 15027/*Reserved. Return zeroes on reads.*/ 15028#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 15029#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15030#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 15031#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 15032#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 15033#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U 15034 15035/*QS Counter Enable*/ 15036#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 15037#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 15038#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 15039#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 15040#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 15041#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U 15042 15043/*Unused DQ I/O Mode*/ 15044#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 15045#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 15046#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 15047#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 15048#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 15049#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U 15050 15051/*Reserved. Return zeroes on reads.*/ 15052#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 15053#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 15054#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 15055#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 15056#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 15057#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U 15058 15059/*Data Slew Rate*/ 15060#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 15061#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 15062#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 15063#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 15064#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 15065#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U 15066 15067/*DQS_N Resistor*/ 15068#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 15069#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 15070#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 15071#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 15072#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 15073#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U 15074 15075/*DQS Resistor*/ 15076#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 15077#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 15078#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 15079#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 15080#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 15081#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU 15082 15083/*Reserved. Return zeroes on reads.*/ 15084#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 15085#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 15086#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 15087#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 15088#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 15089#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U 15090 15091/*Configurable Read Data Enable*/ 15092#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 15093#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 15094#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 15095#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 15096#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 15097#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U 15098 15099/*OX Extension during Post-amble*/ 15100#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 15101#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 15102#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 15103#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 15104#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 15105#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U 15106 15107/*OE Extension during Pre-amble*/ 15108#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 15109#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 15110#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 15111#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 15112#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 15113#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U 15114 15115/*Reserved. Return zeroes on reads.*/ 15116#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 15117#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 15118#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 15119#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 15120#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 15121#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U 15122 15123/*I/O Assisted Gate Select*/ 15124#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 15125#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 15126#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 15127#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 15128#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 15129#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U 15130 15131/*I/O Loopback Select*/ 15132#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 15133#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15134#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 15135#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 15136#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 15137#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U 15138 15139/*Reserved. Return zeroes on reads.*/ 15140#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 15141#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 15142#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 15143#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 15144#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 15145#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U 15146 15147/*Low Power Wakeup Threshold*/ 15148#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 15149#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 15150#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 15151#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 15152#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 15153#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U 15154 15155/*Read Data Bus Inversion Enable*/ 15156#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 15157#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 15158#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 15159#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 15160#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 15161#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U 15162 15163/*Write Data Bus Inversion Enable*/ 15164#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 15165#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 15166#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 15167#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 15168#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 15169#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U 15170 15171/*PUB Read FIFO Bypass*/ 15172#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 15173#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 15174#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 15175#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 15176#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 15177#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U 15178 15179/*DATX8 Receive FIFO Read Mode*/ 15180#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 15181#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 15182#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 15183#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 15184#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 15185#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U 15186 15187/*Disables the Read FIFO Reset*/ 15188#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 15189#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 15190#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 15191#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 15192#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 15193#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U 15194 15195/*Read DQS Gate I/O Loopback*/ 15196#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 15197#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 15198#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 15199#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 15200#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 15201#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U 15202 15203/*Reserved. Return zeroes on reads.*/ 15204#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 15205#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 15206#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 15207#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 15208#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 15209#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U 15210 15211/*Reserved. Return zeroes on reads.*/ 15212#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 15213#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 15214#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 15215#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 15216#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 15217#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U 15218 15219/*PVREF_DAC REFSEL range select*/ 15220#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 15221#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 15222#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 15223#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 15224#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 15225#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U 15226 15227/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ 15228#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 15229#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 15230#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 15231#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 15232#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 15233#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U 15234 15235/*DX IO Mode*/ 15236#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 15237#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 15238#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK 15239#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 15240#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 15241#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U 15242 15243/*DX IO Transmitter Mode*/ 15244#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 15245#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 15246#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK 15247#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 15248#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 15249#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U 15250 15251/*DX IO Receiver Mode*/ 15252#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 15253#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 15254#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK 15255#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 15256#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 15257#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU 15258 15259/*Reserved. Return zeroes on reads.*/ 15260#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 15261#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 15262#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 15263#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE 15264#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 15265#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U 15266 15267/*Enable Clock Gating for DX ddr_clk*/ 15268#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 15269#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 15270#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 15271#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE 15272#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 15273#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U 15274 15275/*Enable Clock Gating for DX ctl_rd_clk*/ 15276#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 15277#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 15278#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 15279#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE 15280#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 15281#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U 15282 15283/*Enable Clock Gating for DX ctl_clk*/ 15284#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 15285#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 15286#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 15287#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE 15288#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 15289#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U 15290 15291/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ 15292#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 15293#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 15294#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 15295#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE 15296#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 15297#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U 15298 15299/*Loopback Mode*/ 15300#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 15301#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 15302#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK 15303#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE 15304#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 15305#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U 15306 15307/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ 15308#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 15309#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 15310#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 15311#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE 15312#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 15313#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U 15314 15315/*Loopback DQS Gating*/ 15316#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 15317#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 15318#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK 15319#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE 15320#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 15321#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U 15322 15323/*Loopback DQS Shift*/ 15324#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 15325#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 15326#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK 15327#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE 15328#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 15329#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U 15330 15331/*PHY High-Speed Reset*/ 15332#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 15333#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 15334#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK 15335#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE 15336#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 15337#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U 15338 15339/*PHY FIFO Reset*/ 15340#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 15341#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15342#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK 15343#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE 15344#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 15345#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U 15346 15347/*Delay Line Test Start*/ 15348#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 15349#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT 15350#undef DDR_PHY_DX8SL1OSC_DLTST_MASK 15351#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE 15352#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 15353#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U 15354 15355/*Delay Line Test Mode*/ 15356#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 15357#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 15358#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK 15359#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE 15360#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 15361#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U 15362 15363/*Reserved. Caution, do not write to this register field.*/ 15364#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 15365#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 15366#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 15367#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE 15368#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 15369#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U 15370 15371/*Oscillator Mode Write-Data Delay Line Select*/ 15372#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 15373#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 15374#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 15375#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE 15376#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 15377#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U 15378 15379/*Reserved. Caution, do not write to this register field.*/ 15380#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 15381#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 15382#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 15383#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE 15384#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 15385#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U 15386 15387/*Oscillator Mode Write-Leveling Delay Line Select*/ 15388#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 15389#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 15390#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK 15391#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE 15392#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 15393#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U 15394 15395/*Oscillator Mode Division*/ 15396#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 15397#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 15398#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK 15399#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE 15400#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 15401#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU 15402 15403/*Oscillator Enable*/ 15404#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 15405#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 15406#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK 15407#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE 15408#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 15409#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U 15410 15411/*Reserved. Return zeroes on reads.*/ 15412#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 15413#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 15414#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 15415#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 15416#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 15417#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U 15418 15419/*Read Path Rise-to-Rise Mode*/ 15420#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 15421#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 15422#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 15423#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 15424#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 15425#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U 15426 15427/*Reserved. Return zeroes on reads.*/ 15428#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 15429#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 15430#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 15431#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 15432#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 15433#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U 15434 15435/*Write Path Rise-to-Rise Mode*/ 15436#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 15437#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 15438#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 15439#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 15440#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 15441#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U 15442 15443/*DQS Gate Extension*/ 15444#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 15445#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 15446#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 15447#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 15448#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 15449#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U 15450 15451/*Low Power PLL Power Down*/ 15452#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 15453#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 15454#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 15455#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 15456#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 15457#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U 15458 15459/*Low Power I/O Power Down*/ 15460#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 15461#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 15462#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 15463#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 15464#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 15465#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U 15466 15467/*Reserved. Return zeroes on reads.*/ 15468#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 15469#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15470#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 15471#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 15472#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 15473#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U 15474 15475/*QS Counter Enable*/ 15476#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 15477#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 15478#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 15479#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 15480#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 15481#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U 15482 15483/*Unused DQ I/O Mode*/ 15484#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 15485#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 15486#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 15487#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 15488#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 15489#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U 15490 15491/*Reserved. Return zeroes on reads.*/ 15492#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 15493#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 15494#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 15495#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 15496#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 15497#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U 15498 15499/*Data Slew Rate*/ 15500#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 15501#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 15502#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 15503#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 15504#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 15505#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U 15506 15507/*DQS_N Resistor*/ 15508#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 15509#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 15510#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 15511#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 15512#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 15513#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U 15514 15515/*DQS Resistor*/ 15516#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 15517#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 15518#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 15519#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 15520#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 15521#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU 15522 15523/*Reserved. Return zeroes on reads.*/ 15524#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 15525#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 15526#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 15527#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 15528#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 15529#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U 15530 15531/*Configurable Read Data Enable*/ 15532#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 15533#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 15534#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 15535#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 15536#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 15537#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U 15538 15539/*OX Extension during Post-amble*/ 15540#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 15541#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 15542#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 15543#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 15544#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 15545#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U 15546 15547/*OE Extension during Pre-amble*/ 15548#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 15549#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 15550#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 15551#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 15552#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 15553#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U 15554 15555/*Reserved. Return zeroes on reads.*/ 15556#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 15557#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 15558#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 15559#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 15560#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 15561#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U 15562 15563/*I/O Assisted Gate Select*/ 15564#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 15565#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 15566#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 15567#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 15568#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 15569#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U 15570 15571/*I/O Loopback Select*/ 15572#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 15573#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15574#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 15575#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 15576#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 15577#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U 15578 15579/*Reserved. Return zeroes on reads.*/ 15580#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 15581#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 15582#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 15583#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 15584#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 15585#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U 15586 15587/*Low Power Wakeup Threshold*/ 15588#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 15589#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 15590#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 15591#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 15592#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 15593#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U 15594 15595/*Read Data Bus Inversion Enable*/ 15596#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 15597#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 15598#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 15599#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 15600#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 15601#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U 15602 15603/*Write Data Bus Inversion Enable*/ 15604#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 15605#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 15606#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 15607#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 15608#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 15609#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U 15610 15611/*PUB Read FIFO Bypass*/ 15612#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 15613#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 15614#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 15615#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 15616#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 15617#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U 15618 15619/*DATX8 Receive FIFO Read Mode*/ 15620#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 15621#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 15622#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 15623#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 15624#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 15625#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U 15626 15627/*Disables the Read FIFO Reset*/ 15628#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 15629#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 15630#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 15631#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 15632#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 15633#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U 15634 15635/*Read DQS Gate I/O Loopback*/ 15636#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 15637#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 15638#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 15639#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 15640#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 15641#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U 15642 15643/*Reserved. Return zeroes on reads.*/ 15644#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 15645#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 15646#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 15647#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 15648#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 15649#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U 15650 15651/*Reserved. Return zeroes on reads.*/ 15652#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 15653#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 15654#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 15655#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 15656#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 15657#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U 15658 15659/*PVREF_DAC REFSEL range select*/ 15660#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 15661#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 15662#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 15663#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 15664#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 15665#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U 15666 15667/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ 15668#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 15669#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 15670#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 15671#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 15672#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 15673#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U 15674 15675/*DX IO Mode*/ 15676#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 15677#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 15678#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK 15679#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 15680#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 15681#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U 15682 15683/*DX IO Transmitter Mode*/ 15684#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 15685#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 15686#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK 15687#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 15688#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 15689#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U 15690 15691/*DX IO Receiver Mode*/ 15692#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 15693#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 15694#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK 15695#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 15696#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 15697#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU 15698 15699/*Reserved. Return zeroes on reads.*/ 15700#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 15701#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 15702#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 15703#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE 15704#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 15705#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U 15706 15707/*Enable Clock Gating for DX ddr_clk*/ 15708#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 15709#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 15710#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 15711#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE 15712#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 15713#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U 15714 15715/*Enable Clock Gating for DX ctl_rd_clk*/ 15716#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 15717#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 15718#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 15719#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE 15720#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 15721#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U 15722 15723/*Enable Clock Gating for DX ctl_clk*/ 15724#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 15725#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 15726#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 15727#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE 15728#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 15729#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U 15730 15731/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ 15732#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 15733#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 15734#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 15735#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE 15736#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 15737#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U 15738 15739/*Loopback Mode*/ 15740#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 15741#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 15742#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK 15743#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE 15744#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 15745#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U 15746 15747/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ 15748#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 15749#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 15750#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 15751#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE 15752#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 15753#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U 15754 15755/*Loopback DQS Gating*/ 15756#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 15757#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 15758#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK 15759#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE 15760#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 15761#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U 15762 15763/*Loopback DQS Shift*/ 15764#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 15765#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 15766#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK 15767#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE 15768#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 15769#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U 15770 15771/*PHY High-Speed Reset*/ 15772#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 15773#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 15774#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK 15775#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE 15776#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 15777#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U 15778 15779/*PHY FIFO Reset*/ 15780#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 15781#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15782#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK 15783#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE 15784#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 15785#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U 15786 15787/*Delay Line Test Start*/ 15788#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 15789#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT 15790#undef DDR_PHY_DX8SL2OSC_DLTST_MASK 15791#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE 15792#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 15793#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U 15794 15795/*Delay Line Test Mode*/ 15796#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 15797#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 15798#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK 15799#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE 15800#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 15801#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U 15802 15803/*Reserved. Caution, do not write to this register field.*/ 15804#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 15805#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 15806#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 15807#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE 15808#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 15809#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U 15810 15811/*Oscillator Mode Write-Data Delay Line Select*/ 15812#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 15813#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 15814#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 15815#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE 15816#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 15817#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U 15818 15819/*Reserved. Caution, do not write to this register field.*/ 15820#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 15821#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 15822#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 15823#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE 15824#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 15825#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U 15826 15827/*Oscillator Mode Write-Leveling Delay Line Select*/ 15828#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 15829#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 15830#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK 15831#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE 15832#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 15833#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U 15834 15835/*Oscillator Mode Division*/ 15836#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 15837#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 15838#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK 15839#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE 15840#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 15841#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU 15842 15843/*Oscillator Enable*/ 15844#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 15845#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 15846#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK 15847#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE 15848#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 15849#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U 15850 15851/*Reserved. Return zeroes on reads.*/ 15852#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 15853#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 15854#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 15855#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 15856#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 15857#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U 15858 15859/*Read Path Rise-to-Rise Mode*/ 15860#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 15861#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 15862#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 15863#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 15864#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 15865#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U 15866 15867/*Reserved. Return zeroes on reads.*/ 15868#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 15869#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 15870#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 15871#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 15872#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 15873#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U 15874 15875/*Write Path Rise-to-Rise Mode*/ 15876#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 15877#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 15878#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 15879#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 15880#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 15881#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U 15882 15883/*DQS Gate Extension*/ 15884#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 15885#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 15886#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 15887#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 15888#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 15889#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U 15890 15891/*Low Power PLL Power Down*/ 15892#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 15893#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 15894#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 15895#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 15896#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 15897#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U 15898 15899/*Low Power I/O Power Down*/ 15900#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 15901#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 15902#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 15903#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 15904#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 15905#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U 15906 15907/*Reserved. Return zeroes on reads.*/ 15908#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 15909#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15910#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 15911#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 15912#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 15913#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U 15914 15915/*QS Counter Enable*/ 15916#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 15917#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 15918#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 15919#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 15920#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 15921#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U 15922 15923/*Unused DQ I/O Mode*/ 15924#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 15925#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 15926#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 15927#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 15928#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 15929#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U 15930 15931/*Reserved. Return zeroes on reads.*/ 15932#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 15933#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 15934#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 15935#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 15936#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 15937#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U 15938 15939/*Data Slew Rate*/ 15940#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 15941#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 15942#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 15943#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 15944#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 15945#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U 15946 15947/*DQS_N Resistor*/ 15948#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 15949#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 15950#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 15951#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 15952#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 15953#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U 15954 15955/*DQS Resistor*/ 15956#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 15957#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 15958#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 15959#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 15960#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 15961#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU 15962 15963/*Reserved. Return zeroes on reads.*/ 15964#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 15965#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 15966#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 15967#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 15968#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 15969#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U 15970 15971/*Configurable Read Data Enable*/ 15972#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 15973#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 15974#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 15975#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 15976#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 15977#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U 15978 15979/*OX Extension during Post-amble*/ 15980#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 15981#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 15982#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 15983#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 15984#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 15985#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U 15986 15987/*OE Extension during Pre-amble*/ 15988#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 15989#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 15990#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 15991#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 15992#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 15993#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U 15994 15995/*Reserved. Return zeroes on reads.*/ 15996#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 15997#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 15998#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 15999#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 16000#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17
16001#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U 16002 16003/*I/O Assisted Gate Select*/ 16004#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 16005#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16006#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 16007#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 16008#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 16009#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U 16010 16011/*I/O Loopback Select*/ 16012#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 16013#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 16014#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 16015#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 16016#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 16017#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U 16018 16019/*Reserved. Return zeroes on reads.*/ 16020#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 16021#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 16022#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 16023#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 16024#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 16025#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U 16026 16027/*Low Power Wakeup Threshold*/ 16028#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 16029#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 16030#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 16031#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 16032#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 16033#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U 16034 16035/*Read Data Bus Inversion Enable*/ 16036#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 16037#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 16038#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 16039#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 16040#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 16041#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U 16042 16043/*Write Data Bus Inversion Enable*/ 16044#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 16045#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 16046#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 16047#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 16048#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 16049#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U 16050 16051/*PUB Read FIFO Bypass*/ 16052#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 16053#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 16054#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 16055#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 16056#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 16057#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U 16058 16059/*DATX8 Receive FIFO Read Mode*/ 16060#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 16061#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 16062#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 16063#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 16064#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 16065#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U 16066 16067/*Disables the Read FIFO Reset*/ 16068#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 16069#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 16070#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 16071#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 16072#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 16073#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U 16074 16075/*Read DQS Gate I/O Loopback*/ 16076#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 16077#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 16078#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 16079#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 16080#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 16081#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U 16082 16083/*Reserved. Return zeroes on reads.*/ 16084#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 16085#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 16086#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 16087#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 16088#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 16089#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U 16090 16091/*Reserved. Return zeroes on reads.*/ 16092#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 16093#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 16094#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 16095#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 16096#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 16097#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U 16098 16099/*PVREF_DAC REFSEL range select*/ 16100#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 16101#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 16102#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 16103#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 16104#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 16105#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U 16106 16107/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ 16108#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 16109#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 16110#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 16111#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 16112#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 16113#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U 16114 16115/*DX IO Mode*/ 16116#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 16117#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 16118#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK 16119#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 16120#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 16121#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U 16122 16123/*DX IO Transmitter Mode*/ 16124#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 16125#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 16126#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK 16127#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 16128#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 16129#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U 16130 16131/*DX IO Receiver Mode*/ 16132#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 16133#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 16134#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK 16135#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 16136#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 16137#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU 16138 16139/*Reserved. Return zeroes on reads.*/ 16140#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 16141#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 16142#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 16143#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE 16144#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 16145#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U 16146 16147/*Enable Clock Gating for DX ddr_clk*/ 16148#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 16149#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 16150#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 16151#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE 16152#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 16153#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U 16154 16155/*Enable Clock Gating for DX ctl_rd_clk*/ 16156#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 16157#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 16158#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 16159#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE 16160#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 16161#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U 16162 16163/*Enable Clock Gating for DX ctl_clk*/ 16164#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 16165#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 16166#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 16167#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE 16168#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 16169#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U 16170 16171/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ 16172#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 16173#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 16174#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 16175#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE 16176#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 16177#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U 16178 16179/*Loopback Mode*/ 16180#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 16181#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 16182#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK 16183#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE 16184#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 16185#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U 16186 16187/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ 16188#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 16189#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 16190#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 16191#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE 16192#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 16193#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U 16194 16195/*Loopback DQS Gating*/ 16196#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 16197#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 16198#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK 16199#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE 16200#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 16201#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U 16202 16203/*Loopback DQS Shift*/ 16204#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 16205#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 16206#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK 16207#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE 16208#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 16209#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U 16210 16211/*PHY High-Speed Reset*/ 16212#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 16213#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16214#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK 16215#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE 16216#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 16217#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U 16218 16219/*PHY FIFO Reset*/ 16220#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 16221#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 16222#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK 16223#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE 16224#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 16225#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U 16226 16227/*Delay Line Test Start*/ 16228#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 16229#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT 16230#undef DDR_PHY_DX8SL3OSC_DLTST_MASK 16231#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE 16232#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 16233#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U 16234 16235/*Delay Line Test Mode*/ 16236#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 16237#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 16238#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK 16239#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE 16240#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 16241#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U 16242 16243/*Reserved. Caution, do not write to this register field.*/ 16244#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 16245#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 16246#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 16247#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE 16248#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 16249#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U 16250 16251/*Oscillator Mode Write-Data Delay Line Select*/ 16252#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 16253#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 16254#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 16255#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE 16256#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 16257#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U 16258 16259/*Reserved. Caution, do not write to this register field.*/ 16260#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 16261#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 16262#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 16263#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE 16264#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 16265#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U 16266 16267/*Oscillator Mode Write-Leveling Delay Line Select*/ 16268#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 16269#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 16270#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK 16271#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE 16272#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 16273#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U 16274 16275/*Oscillator Mode Division*/ 16276#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 16277#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 16278#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK 16279#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE 16280#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 16281#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU 16282 16283/*Oscillator Enable*/ 16284#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 16285#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 16286#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK 16287#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE 16288#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 16289#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U 16290 16291/*Reserved. Return zeroes on reads.*/ 16292#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 16293#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 16294#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 16295#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 16296#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 16297#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U 16298 16299/*Read Path Rise-to-Rise Mode*/ 16300#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 16301#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 16302#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 16303#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 16304#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 16305#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U 16306 16307/*Reserved. Return zeroes on reads.*/ 16308#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 16309#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 16310#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 16311#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 16312#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 16313#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U 16314 16315/*Write Path Rise-to-Rise Mode*/ 16316#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 16317#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 16318#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 16319#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 16320#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 16321#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U 16322 16323/*DQS Gate Extension*/ 16324#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 16325#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 16326#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 16327#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 16328#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 16329#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U 16330 16331/*Low Power PLL Power Down*/ 16332#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 16333#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 16334#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 16335#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 16336#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 16337#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U 16338 16339/*Low Power I/O Power Down*/ 16340#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 16341#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 16342#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 16343#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 16344#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 16345#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U 16346 16347/*Reserved. Return zeroes on reads.*/ 16348#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 16349#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 16350#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 16351#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 16352#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 16353#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U 16354 16355/*QS Counter Enable*/ 16356#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 16357#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 16358#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 16359#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 16360#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 16361#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U 16362 16363/*Unused DQ I/O Mode*/ 16364#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 16365#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 16366#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 16367#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 16368#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 16369#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U 16370 16371/*Reserved. Return zeroes on reads.*/ 16372#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 16373#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 16374#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 16375#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 16376#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 16377#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U 16378 16379/*Data Slew Rate*/ 16380#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 16381#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 16382#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 16383#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 16384#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 16385#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U 16386 16387/*DQS_N Resistor*/ 16388#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 16389#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 16390#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 16391#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 16392#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 16393#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U 16394 16395/*DQS Resistor*/ 16396#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 16397#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 16398#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 16399#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 16400#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 16401#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU 16402 16403/*Reserved. Return zeroes on reads.*/ 16404#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 16405#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 16406#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 16407#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 16408#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 16409#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U 16410 16411/*Configurable Read Data Enable*/ 16412#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 16413#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 16414#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 16415#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 16416#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 16417#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U 16418 16419/*OX Extension during Post-amble*/ 16420#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 16421#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 16422#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 16423#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 16424#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 16425#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U 16426 16427/*OE Extension during Pre-amble*/ 16428#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 16429#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 16430#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 16431#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 16432#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 16433#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U 16434 16435/*Reserved. Return zeroes on reads.*/ 16436#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 16437#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 16438#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 16439#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 16440#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 16441#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U 16442 16443/*I/O Assisted Gate Select*/ 16444#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 16445#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16446#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 16447#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 16448#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 16449#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U 16450 16451/*I/O Loopback Select*/ 16452#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 16453#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 16454#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 16455#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 16456#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 16457#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U 16458 16459/*Reserved. Return zeroes on reads.*/ 16460#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 16461#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 16462#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 16463#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 16464#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 16465#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U 16466 16467/*Low Power Wakeup Threshold*/ 16468#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 16469#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 16470#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 16471#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 16472#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 16473#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U 16474 16475/*Read Data Bus Inversion Enable*/ 16476#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 16477#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 16478#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 16479#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 16480#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 16481#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U 16482 16483/*Write Data Bus Inversion Enable*/ 16484#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 16485#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 16486#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 16487#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 16488#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 16489#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U 16490 16491/*PUB Read FIFO Bypass*/ 16492#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 16493#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 16494#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 16495#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 16496#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 16497#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U 16498 16499/*DATX8 Receive FIFO Read Mode*/ 16500#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 16501#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 16502#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 16503#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 16504#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 16505#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U 16506 16507/*Disables the Read FIFO Reset*/ 16508#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 16509#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 16510#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 16511#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 16512#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 16513#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U 16514 16515/*Read DQS Gate I/O Loopback*/ 16516#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 16517#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 16518#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 16519#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 16520#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 16521#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U 16522 16523/*Reserved. Return zeroes on reads.*/ 16524#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 16525#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 16526#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 16527#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 16528#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 16529#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U 16530 16531/*Reserved. Return zeroes on reads.*/ 16532#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 16533#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 16534#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 16535#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 16536#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 16537#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U 16538 16539/*PVREF_DAC REFSEL range select*/ 16540#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 16541#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 16542#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 16543#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 16544#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 16545#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U 16546 16547/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ 16548#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 16549#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 16550#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 16551#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 16552#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 16553#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U 16554 16555/*DX IO Mode*/ 16556#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 16557#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 16558#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK 16559#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 16560#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 16561#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U 16562 16563/*DX IO Transmitter Mode*/ 16564#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 16565#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 16566#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK 16567#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 16568#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 16569#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U 16570 16571/*DX IO Receiver Mode*/ 16572#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 16573#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 16574#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK 16575#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 16576#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 16577#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU 16578 16579/*Reserved. Return zeroes on reads.*/ 16580#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 16581#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 16582#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 16583#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE 16584#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 16585#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U 16586 16587/*Enable Clock Gating for DX ddr_clk*/ 16588#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 16589#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 16590#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 16591#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE 16592#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 16593#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U 16594 16595/*Enable Clock Gating for DX ctl_rd_clk*/ 16596#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 16597#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 16598#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 16599#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE 16600#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 16601#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U 16602 16603/*Enable Clock Gating for DX ctl_clk*/ 16604#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 16605#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 16606#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 16607#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE 16608#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 16609#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U 16610 16611/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ 16612#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 16613#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 16614#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 16615#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE 16616#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 16617#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U 16618 16619/*Loopback Mode*/ 16620#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 16621#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 16622#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK 16623#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE 16624#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 16625#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U 16626 16627/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ 16628#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 16629#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 16630#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 16631#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE 16632#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 16633#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U 16634 16635/*Loopback DQS Gating*/ 16636#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 16637#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 16638#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK 16639#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE 16640#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 16641#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U 16642 16643/*Loopback DQS Shift*/ 16644#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 16645#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 16646#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK 16647#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE 16648#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 16649#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U 16650 16651/*PHY High-Speed Reset*/ 16652#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 16653#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16654#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK 16655#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE 16656#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 16657#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U 16658 16659/*PHY FIFO Reset*/ 16660#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 16661#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 16662#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK 16663#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE 16664#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 16665#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U 16666 16667/*Delay Line Test Start*/ 16668#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 16669#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT 16670#undef DDR_PHY_DX8SL4OSC_DLTST_MASK 16671#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE 16672#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 16673#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U 16674 16675/*Delay Line Test Mode*/ 16676#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 16677#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 16678#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK 16679#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE 16680#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 16681#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U 16682 16683/*Reserved. Caution, do not write to this register field.*/ 16684#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 16685#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 16686#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 16687#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE 16688#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 16689#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U 16690 16691/*Oscillator Mode Write-Data Delay Line Select*/ 16692#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 16693#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 16694#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 16695#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE 16696#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 16697#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U 16698 16699/*Reserved. Caution, do not write to this register field.*/ 16700#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 16701#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 16702#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 16703#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE 16704#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 16705#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U 16706 16707/*Oscillator Mode Write-Leveling Delay Line Select*/ 16708#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 16709#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 16710#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK 16711#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE 16712#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 16713#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U 16714 16715/*Oscillator Mode Division*/ 16716#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 16717#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 16718#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK 16719#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE 16720#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 16721#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU 16722 16723/*Oscillator Enable*/ 16724#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 16725#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 16726#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK 16727#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE 16728#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 16729#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U 16730 16731/*Reserved. Return zeroes on reads.*/ 16732#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 16733#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 16734#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 16735#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 16736#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 16737#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U 16738 16739/*Read Path Rise-to-Rise Mode*/ 16740#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 16741#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 16742#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 16743#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 16744#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 16745#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U 16746 16747/*Reserved. Return zeroes on reads.*/ 16748#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 16749#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 16750#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 16751#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 16752#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 16753#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U 16754 16755/*Write Path Rise-to-Rise Mode*/ 16756#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 16757#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 16758#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 16759#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 16760#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 16761#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U 16762 16763/*DQS Gate Extension*/ 16764#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 16765#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 16766#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 16767#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 16768#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 16769#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U 16770 16771/*Low Power PLL Power Down*/ 16772#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 16773#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 16774#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 16775#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 16776#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 16777#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U 16778 16779/*Low Power I/O Power Down*/ 16780#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 16781#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 16782#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 16783#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 16784#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 16785#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U 16786 16787/*Reserved. Return zeroes on reads.*/ 16788#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 16789#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 16790#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 16791#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 16792#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 16793#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U 16794 16795/*QS Counter Enable*/ 16796#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 16797#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 16798#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 16799#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 16800#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 16801#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U 16802 16803/*Unused DQ I/O Mode*/ 16804#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 16805#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 16806#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 16807#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 16808#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 16809#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U 16810 16811/*Reserved. Return zeroes on reads.*/ 16812#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 16813#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 16814#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 16815#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 16816#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 16817#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U 16818 16819/*Data Slew Rate*/ 16820#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 16821#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 16822#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 16823#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 16824#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 16825#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U 16826 16827/*DQS_N Resistor*/ 16828#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 16829#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 16830#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 16831#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 16832#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 16833#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U 16834 16835/*DQS Resistor*/ 16836#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 16837#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 16838#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 16839#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 16840#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 16841#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU 16842 16843/*Reserved. Return zeroes on reads.*/ 16844#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 16845#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 16846#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 16847#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 16848#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 16849#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U 16850 16851/*Configurable Read Data Enable*/ 16852#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 16853#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 16854#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 16855#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 16856#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 16857#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U 16858 16859/*OX Extension during Post-amble*/ 16860#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 16861#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 16862#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 16863#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 16864#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 16865#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U 16866 16867/*OE Extension during Pre-amble*/ 16868#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 16869#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 16870#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 16871#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 16872#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 16873#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U 16874 16875/*Reserved. Return zeroes on reads.*/ 16876#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 16877#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 16878#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 16879#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 16880#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 16881#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U 16882 16883/*I/O Assisted Gate Select*/ 16884#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 16885#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16886#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 16887#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 16888#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 16889#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U 16890 16891/*I/O Loopback Select*/ 16892#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 16893#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 16894#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 16895#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 16896#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 16897#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U 16898 16899/*Reserved. Return zeroes on reads.*/ 16900#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 16901#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 16902#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 16903#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 16904#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 16905#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U 16906 16907/*Low Power Wakeup Threshold*/ 16908#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 16909#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 16910#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 16911#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 16912#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 16913#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U 16914 16915/*Read Data Bus Inversion Enable*/ 16916#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 16917#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 16918#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 16919#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 16920#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 16921#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U 16922 16923/*Write Data Bus Inversion Enable*/ 16924#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 16925#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 16926#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 16927#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 16928#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 16929#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U 16930 16931/*PUB Read FIFO Bypass*/ 16932#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 16933#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 16934#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 16935#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 16936#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 16937#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U 16938 16939/*DATX8 Receive FIFO Read Mode*/ 16940#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 16941#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 16942#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 16943#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 16944#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 16945#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U 16946 16947/*Disables the Read FIFO Reset*/ 16948#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 16949#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 16950#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 16951#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 16952#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 16953#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U 16954 16955/*Read DQS Gate I/O Loopback*/ 16956#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 16957#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 16958#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 16959#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 16960#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 16961#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U 16962 16963/*Reserved. Return zeroes on reads.*/ 16964#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 16965#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 16966#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 16967#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 16968#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 16969#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U 16970 16971/*Reserved. Return zeroes on reads.*/ 16972#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 16973#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 16974#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 16975#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 16976#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 16977#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U 16978 16979/*PVREF_DAC REFSEL range select*/ 16980#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 16981#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 16982#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 16983#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 16984#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 16985#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U 16986 16987/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ 16988#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 16989#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 16990#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 16991#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 16992#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 16993#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U 16994 16995/*DX IO Mode*/ 16996#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 16997#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 16998#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK 16999#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 17000#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22
17001#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U 17002 17003/*DX IO Transmitter Mode*/ 17004#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 17005#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 17006#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK 17007#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 17008#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 17009#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U 17010 17011/*DX IO Receiver Mode*/ 17012#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 17013#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 17014#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK 17015#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 17016#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 17017#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU 17018 17019/*Reserved. Return zeroes on reads.*/ 17020#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 17021#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 17022#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 17023#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 17024#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 17025#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U 17026 17027/*Read Path Rise-to-Rise Mode*/ 17028#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 17029#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 17030#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 17031#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 17032#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 17033#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U 17034 17035/*Reserved. Return zeroes on reads.*/ 17036#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 17037#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 17038#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 17039#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 17040#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 17041#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U 17042 17043/*Write Path Rise-to-Rise Mode*/ 17044#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 17045#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 17046#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 17047#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 17048#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 17049#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U 17050 17051/*DQS Gate Extension*/ 17052#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 17053#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 17054#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 17055#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 17056#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 17057#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U 17058 17059/*Low Power PLL Power Down*/ 17060#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 17061#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 17062#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 17063#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 17064#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 17065#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U 17066 17067/*Low Power I/O Power Down*/ 17068#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 17069#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17070#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 17071#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 17072#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 17073#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U 17074 17075/*Reserved. Return zeroes on reads.*/ 17076#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 17077#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 17078#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 17079#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 17080#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 17081#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U 17082 17083/*QS Counter Enable*/ 17084#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 17085#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 17086#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 17087#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 17088#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 17089#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U 17090 17091/*Unused DQ I/O Mode*/ 17092#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 17093#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 17094#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 17095#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 17096#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 17097#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U 17098 17099/*Reserved. Return zeroes on reads.*/ 17100#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 17101#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 17102#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 17103#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 17104#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 17105#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U 17106 17107/*Data Slew Rate*/ 17108#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 17109#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 17110#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 17111#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 17112#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 17113#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U 17114 17115/*DQS# Resistor*/ 17116#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 17117#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 17118#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 17119#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 17120#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 17121#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U 17122 17123/*DQS Resistor*/ 17124#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 17125#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 17126#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 17127#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 17128#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 17129#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU 17130 17131/*Reserved. Return zeroes on reads.*/ 17132#undef DDR_PHY_PIR_RESERVED_31_DEFVAL 17133#undef DDR_PHY_PIR_RESERVED_31_SHIFT 17134#undef DDR_PHY_PIR_RESERVED_31_MASK 17135#define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000 17136#define DDR_PHY_PIR_RESERVED_31_SHIFT 31 17137#define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U 17138 17139/*Impedance Calibration Bypass*/ 17140#undef DDR_PHY_PIR_ZCALBYP_DEFVAL 17141#undef DDR_PHY_PIR_ZCALBYP_SHIFT 17142#undef DDR_PHY_PIR_ZCALBYP_MASK 17143#define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000 17144#define DDR_PHY_PIR_ZCALBYP_SHIFT 30 17145#define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U 17146 17147/*Digital Delay Line (DDL) Calibration Pause*/ 17148#undef DDR_PHY_PIR_DCALPSE_DEFVAL 17149#undef DDR_PHY_PIR_DCALPSE_SHIFT 17150#undef DDR_PHY_PIR_DCALPSE_MASK 17151#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000 17152#define DDR_PHY_PIR_DCALPSE_SHIFT 29 17153#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U 17154 17155/*Reserved. Return zeroes on reads.*/ 17156#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL 17157#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT 17158#undef DDR_PHY_PIR_RESERVED_28_21_MASK 17159#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000 17160#define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21 17161#define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U 17162 17163/*Write DQS2DQ Training*/ 17164#undef DDR_PHY_PIR_DQS2DQ_DEFVAL 17165#undef DDR_PHY_PIR_DQS2DQ_SHIFT 17166#undef DDR_PHY_PIR_DQS2DQ_MASK 17167#define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000 17168#define DDR_PHY_PIR_DQS2DQ_SHIFT 20 17169#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U 17170 17171/*RDIMM Initialization*/ 17172#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL 17173#undef DDR_PHY_PIR_RDIMMINIT_SHIFT 17174#undef DDR_PHY_PIR_RDIMMINIT_MASK 17175#define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000 17176#define DDR_PHY_PIR_RDIMMINIT_SHIFT 19 17177#define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U 17178 17179/*Controller DRAM Initialization*/ 17180#undef DDR_PHY_PIR_CTLDINIT_DEFVAL 17181#undef DDR_PHY_PIR_CTLDINIT_SHIFT 17182#undef DDR_PHY_PIR_CTLDINIT_MASK 17183#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000 17184#define DDR_PHY_PIR_CTLDINIT_SHIFT 18 17185#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U 17186 17187/*VREF Training*/ 17188#undef DDR_PHY_PIR_VREF_DEFVAL 17189#undef DDR_PHY_PIR_VREF_SHIFT 17190#undef DDR_PHY_PIR_VREF_MASK 17191#define DDR_PHY_PIR_VREF_DEFVAL 0x00000000 17192#define DDR_PHY_PIR_VREF_SHIFT 17 17193#define DDR_PHY_PIR_VREF_MASK 0x00020000U 17194 17195/*Static Read Training*/ 17196#undef DDR_PHY_PIR_SRD_DEFVAL 17197#undef DDR_PHY_PIR_SRD_SHIFT 17198#undef DDR_PHY_PIR_SRD_MASK 17199#define DDR_PHY_PIR_SRD_DEFVAL 0x00000000 17200#define DDR_PHY_PIR_SRD_SHIFT 16 17201#define DDR_PHY_PIR_SRD_MASK 0x00010000U 17202 17203/*Write Data Eye Training*/ 17204#undef DDR_PHY_PIR_WREYE_DEFVAL 17205#undef DDR_PHY_PIR_WREYE_SHIFT 17206#undef DDR_PHY_PIR_WREYE_MASK 17207#define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000 17208#define DDR_PHY_PIR_WREYE_SHIFT 15 17209#define DDR_PHY_PIR_WREYE_MASK 0x00008000U 17210 17211/*Read Data Eye Training*/ 17212#undef DDR_PHY_PIR_RDEYE_DEFVAL 17213#undef DDR_PHY_PIR_RDEYE_SHIFT 17214#undef DDR_PHY_PIR_RDEYE_MASK 17215#define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000 17216#define DDR_PHY_PIR_RDEYE_SHIFT 14 17217#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U 17218 17219/*Write Data Bit Deskew*/ 17220#undef DDR_PHY_PIR_WRDSKW_DEFVAL 17221#undef DDR_PHY_PIR_WRDSKW_SHIFT 17222#undef DDR_PHY_PIR_WRDSKW_MASK 17223#define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000 17224#define DDR_PHY_PIR_WRDSKW_SHIFT 13 17225#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U 17226 17227/*Read Data Bit Deskew*/ 17228#undef DDR_PHY_PIR_RDDSKW_DEFVAL 17229#undef DDR_PHY_PIR_RDDSKW_SHIFT 17230#undef DDR_PHY_PIR_RDDSKW_MASK 17231#define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000 17232#define DDR_PHY_PIR_RDDSKW_SHIFT 12 17233#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U 17234 17235/*Write Leveling Adjust*/ 17236#undef DDR_PHY_PIR_WLADJ_DEFVAL 17237#undef DDR_PHY_PIR_WLADJ_SHIFT 17238#undef DDR_PHY_PIR_WLADJ_MASK 17239#define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000 17240#define DDR_PHY_PIR_WLADJ_SHIFT 11 17241#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U 17242 17243/*Read DQS Gate Training*/ 17244#undef DDR_PHY_PIR_QSGATE_DEFVAL 17245#undef DDR_PHY_PIR_QSGATE_SHIFT 17246#undef DDR_PHY_PIR_QSGATE_MASK 17247#define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000 17248#define DDR_PHY_PIR_QSGATE_SHIFT 10 17249#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U 17250 17251/*Write Leveling*/ 17252#undef DDR_PHY_PIR_WL_DEFVAL 17253#undef DDR_PHY_PIR_WL_SHIFT 17254#undef DDR_PHY_PIR_WL_MASK 17255#define DDR_PHY_PIR_WL_DEFVAL 0x00000000 17256#define DDR_PHY_PIR_WL_SHIFT 9 17257#define DDR_PHY_PIR_WL_MASK 0x00000200U 17258 17259/*DRAM Initialization*/ 17260#undef DDR_PHY_PIR_DRAMINIT_DEFVAL 17261#undef DDR_PHY_PIR_DRAMINIT_SHIFT 17262#undef DDR_PHY_PIR_DRAMINIT_MASK 17263#define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000 17264#define DDR_PHY_PIR_DRAMINIT_SHIFT 8 17265#define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U 17266 17267/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/ 17268#undef DDR_PHY_PIR_DRAMRST_DEFVAL 17269#undef DDR_PHY_PIR_DRAMRST_SHIFT 17270#undef DDR_PHY_PIR_DRAMRST_MASK 17271#define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000 17272#define DDR_PHY_PIR_DRAMRST_SHIFT 7 17273#define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U 17274 17275/*PHY Reset*/ 17276#undef DDR_PHY_PIR_PHYRST_DEFVAL 17277#undef DDR_PHY_PIR_PHYRST_SHIFT 17278#undef DDR_PHY_PIR_PHYRST_MASK 17279#define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000 17280#define DDR_PHY_PIR_PHYRST_SHIFT 6 17281#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U 17282 17283/*Digital Delay Line (DDL) Calibration*/ 17284#undef DDR_PHY_PIR_DCAL_DEFVAL 17285#undef DDR_PHY_PIR_DCAL_SHIFT 17286#undef DDR_PHY_PIR_DCAL_MASK 17287#define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000 17288#define DDR_PHY_PIR_DCAL_SHIFT 5 17289#define DDR_PHY_PIR_DCAL_MASK 0x00000020U 17290 17291/*PLL Initialiazation*/ 17292#undef DDR_PHY_PIR_PLLINIT_DEFVAL 17293#undef DDR_PHY_PIR_PLLINIT_SHIFT 17294#undef DDR_PHY_PIR_PLLINIT_MASK 17295#define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000 17296#define DDR_PHY_PIR_PLLINIT_SHIFT 4 17297#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U 17298 17299/*Reserved. Return zeroes on reads.*/ 17300#undef DDR_PHY_PIR_RESERVED_3_DEFVAL 17301#undef DDR_PHY_PIR_RESERVED_3_SHIFT 17302#undef DDR_PHY_PIR_RESERVED_3_MASK 17303#define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000 17304#define DDR_PHY_PIR_RESERVED_3_SHIFT 3 17305#define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U 17306 17307/*CA Training*/ 17308#undef DDR_PHY_PIR_CA_DEFVAL 17309#undef DDR_PHY_PIR_CA_SHIFT 17310#undef DDR_PHY_PIR_CA_MASK 17311#define DDR_PHY_PIR_CA_DEFVAL 0x00000000 17312#define DDR_PHY_PIR_CA_SHIFT 2 17313#define DDR_PHY_PIR_CA_MASK 0x00000004U 17314 17315/*Impedance Calibration*/ 17316#undef DDR_PHY_PIR_ZCAL_DEFVAL 17317#undef DDR_PHY_PIR_ZCAL_SHIFT 17318#undef DDR_PHY_PIR_ZCAL_MASK 17319#define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000 17320#define DDR_PHY_PIR_ZCAL_SHIFT 1 17321#define DDR_PHY_PIR_ZCAL_MASK 0x00000002U 17322 17323/*Initialization Trigger*/ 17324#undef DDR_PHY_PIR_INIT_DEFVAL 17325#undef DDR_PHY_PIR_INIT_SHIFT 17326#undef DDR_PHY_PIR_INIT_MASK 17327#define DDR_PHY_PIR_INIT_DEFVAL 0x00000000 17328#define DDR_PHY_PIR_INIT_SHIFT 0 17329#define DDR_PHY_PIR_INIT_MASK 0x00000001U 17330#undef IOU_SLCR_MIO_PIN_0_OFFSET 17331#define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 17332#undef IOU_SLCR_MIO_PIN_1_OFFSET 17333#define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004 17334#undef IOU_SLCR_MIO_PIN_2_OFFSET 17335#define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008 17336#undef IOU_SLCR_MIO_PIN_3_OFFSET 17337#define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C 17338#undef IOU_SLCR_MIO_PIN_4_OFFSET 17339#define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010 17340#undef IOU_SLCR_MIO_PIN_5_OFFSET 17341#define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014 17342#undef IOU_SLCR_MIO_PIN_6_OFFSET 17343#define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018 17344#undef IOU_SLCR_MIO_PIN_7_OFFSET 17345#define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C 17346#undef IOU_SLCR_MIO_PIN_8_OFFSET 17347#define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020 17348#undef IOU_SLCR_MIO_PIN_9_OFFSET 17349#define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024 17350#undef IOU_SLCR_MIO_PIN_10_OFFSET 17351#define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028 17352#undef IOU_SLCR_MIO_PIN_11_OFFSET 17353#define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C 17354#undef IOU_SLCR_MIO_PIN_12_OFFSET 17355#define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030 17356#undef IOU_SLCR_MIO_PIN_13_OFFSET 17357#define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034 17358#undef IOU_SLCR_MIO_PIN_14_OFFSET 17359#define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038 17360#undef IOU_SLCR_MIO_PIN_15_OFFSET 17361#define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C 17362#undef IOU_SLCR_MIO_PIN_16_OFFSET 17363#define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040 17364#undef IOU_SLCR_MIO_PIN_17_OFFSET 17365#define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044 17366#undef IOU_SLCR_MIO_PIN_18_OFFSET 17367#define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048 17368#undef IOU_SLCR_MIO_PIN_19_OFFSET 17369#define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C 17370#undef IOU_SLCR_MIO_PIN_20_OFFSET 17371#define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050 17372#undef IOU_SLCR_MIO_PIN_21_OFFSET 17373#define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054 17374#undef IOU_SLCR_MIO_PIN_22_OFFSET 17375#define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058 17376#undef IOU_SLCR_MIO_PIN_23_OFFSET 17377#define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C 17378#undef IOU_SLCR_MIO_PIN_24_OFFSET 17379#define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060 17380#undef IOU_SLCR_MIO_PIN_25_OFFSET 17381#define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064 17382#undef IOU_SLCR_MIO_PIN_26_OFFSET 17383#define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068 17384#undef IOU_SLCR_MIO_PIN_27_OFFSET 17385#define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C 17386#undef IOU_SLCR_MIO_PIN_28_OFFSET 17387#define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070 17388#undef IOU_SLCR_MIO_PIN_29_OFFSET 17389#define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074 17390#undef IOU_SLCR_MIO_PIN_30_OFFSET 17391#define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078 17392#undef IOU_SLCR_MIO_PIN_31_OFFSET 17393#define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C 17394#undef IOU_SLCR_MIO_PIN_32_OFFSET 17395#define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080 17396#undef IOU_SLCR_MIO_PIN_33_OFFSET 17397#define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084 17398#undef IOU_SLCR_MIO_PIN_34_OFFSET 17399#define IOU_SLCR_MIO_PIN_34_OFFSET 0XFF180088 17400#undef IOU_SLCR_MIO_PIN_35_OFFSET 17401#define IOU_SLCR_MIO_PIN_35_OFFSET 0XFF18008C 17402#undef IOU_SLCR_MIO_PIN_36_OFFSET 17403#define IOU_SLCR_MIO_PIN_36_OFFSET 0XFF180090 17404#undef IOU_SLCR_MIO_PIN_37_OFFSET 17405#define IOU_SLCR_MIO_PIN_37_OFFSET 0XFF180094 17406#undef IOU_SLCR_MIO_PIN_38_OFFSET 17407#define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098 17408#undef IOU_SLCR_MIO_PIN_39_OFFSET 17409#define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C 17410#undef IOU_SLCR_MIO_PIN_40_OFFSET 17411#define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0 17412#undef IOU_SLCR_MIO_PIN_41_OFFSET 17413#define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4 17414#undef IOU_SLCR_MIO_PIN_42_OFFSET 17415#define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8 17416#undef IOU_SLCR_MIO_PIN_43_OFFSET 17417#define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC 17418#undef IOU_SLCR_MIO_PIN_44_OFFSET 17419#define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0 17420#undef IOU_SLCR_MIO_PIN_45_OFFSET 17421#define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4 17422#undef IOU_SLCR_MIO_PIN_46_OFFSET 17423#define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8 17424#undef IOU_SLCR_MIO_PIN_47_OFFSET 17425#define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC 17426#undef IOU_SLCR_MIO_PIN_48_OFFSET 17427#define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0 17428#undef IOU_SLCR_MIO_PIN_49_OFFSET 17429#define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4 17430#undef IOU_SLCR_MIO_PIN_50_OFFSET 17431#define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8 17432#undef IOU_SLCR_MIO_PIN_51_OFFSET 17433#define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC 17434#undef IOU_SLCR_MIO_PIN_52_OFFSET 17435#define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0 17436#undef IOU_SLCR_MIO_PIN_53_OFFSET 17437#define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4 17438#undef IOU_SLCR_MIO_PIN_54_OFFSET 17439#define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8 17440#undef IOU_SLCR_MIO_PIN_55_OFFSET 17441#define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC 17442#undef IOU_SLCR_MIO_PIN_56_OFFSET 17443#define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0 17444#undef IOU_SLCR_MIO_PIN_57_OFFSET 17445#define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4 17446#undef IOU_SLCR_MIO_PIN_58_OFFSET 17447#define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8 17448#undef IOU_SLCR_MIO_PIN_59_OFFSET 17449#define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC 17450#undef IOU_SLCR_MIO_PIN_60_OFFSET 17451#define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0 17452#undef IOU_SLCR_MIO_PIN_61_OFFSET 17453#define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4 17454#undef IOU_SLCR_MIO_PIN_62_OFFSET 17455#define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8 17456#undef IOU_SLCR_MIO_PIN_63_OFFSET 17457#define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC 17458#undef IOU_SLCR_MIO_PIN_64_OFFSET 17459#define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100 17460#undef IOU_SLCR_MIO_PIN_65_OFFSET 17461#define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104 17462#undef IOU_SLCR_MIO_PIN_66_OFFSET 17463#define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108 17464#undef IOU_SLCR_MIO_PIN_67_OFFSET 17465#define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C 17466#undef IOU_SLCR_MIO_PIN_68_OFFSET 17467#define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110 17468#undef IOU_SLCR_MIO_PIN_69_OFFSET 17469#define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114 17470#undef IOU_SLCR_MIO_PIN_70_OFFSET 17471#define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118 17472#undef IOU_SLCR_MIO_PIN_71_OFFSET 17473#define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C 17474#undef IOU_SLCR_MIO_PIN_72_OFFSET 17475#define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120 17476#undef IOU_SLCR_MIO_PIN_73_OFFSET 17477#define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124 17478#undef IOU_SLCR_MIO_PIN_74_OFFSET 17479#define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128 17480#undef IOU_SLCR_MIO_PIN_75_OFFSET 17481#define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C 17482#undef IOU_SLCR_MIO_PIN_76_OFFSET 17483#define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130 17484#undef IOU_SLCR_MIO_PIN_77_OFFSET 17485#define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134 17486#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 17487#define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204 17488#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 17489#define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208 17490#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 17491#define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C 17492#undef IOU_SLCR_BANK0_CTRL0_OFFSET 17493#define IOU_SLCR_BANK0_CTRL0_OFFSET 0XFF180138 17494#undef IOU_SLCR_BANK0_CTRL1_OFFSET 17495#define IOU_SLCR_BANK0_CTRL1_OFFSET 0XFF18013C 17496#undef IOU_SLCR_BANK0_CTRL3_OFFSET 17497#define IOU_SLCR_BANK0_CTRL3_OFFSET 0XFF180140 17498#undef IOU_SLCR_BANK0_CTRL4_OFFSET 17499#define IOU_SLCR_BANK0_CTRL4_OFFSET 0XFF180144 17500#undef IOU_SLCR_BANK0_CTRL5_OFFSET 17501#define IOU_SLCR_BANK0_CTRL5_OFFSET 0XFF180148 17502#undef IOU_SLCR_BANK0_CTRL6_OFFSET 17503#define IOU_SLCR_BANK0_CTRL6_OFFSET 0XFF18014C 17504#undef IOU_SLCR_BANK1_CTRL0_OFFSET 17505#define IOU_SLCR_BANK1_CTRL0_OFFSET 0XFF180154 17506#undef IOU_SLCR_BANK1_CTRL1_OFFSET 17507#define IOU_SLCR_BANK1_CTRL1_OFFSET 0XFF180158 17508#undef IOU_SLCR_BANK1_CTRL3_OFFSET 17509#define IOU_SLCR_BANK1_CTRL3_OFFSET 0XFF18015C 17510#undef IOU_SLCR_BANK1_CTRL4_OFFSET 17511#define IOU_SLCR_BANK1_CTRL4_OFFSET 0XFF180160 17512#undef IOU_SLCR_BANK1_CTRL5_OFFSET 17513#define IOU_SLCR_BANK1_CTRL5_OFFSET 0XFF180164 17514#undef IOU_SLCR_BANK1_CTRL6_OFFSET 17515#define IOU_SLCR_BANK1_CTRL6_OFFSET 0XFF180168 17516#undef IOU_SLCR_BANK2_CTRL0_OFFSET 17517#define IOU_SLCR_BANK2_CTRL0_OFFSET 0XFF180170 17518#undef IOU_SLCR_BANK2_CTRL1_OFFSET 17519#define IOU_SLCR_BANK2_CTRL1_OFFSET 0XFF180174 17520#undef IOU_SLCR_BANK2_CTRL3_OFFSET 17521#define IOU_SLCR_BANK2_CTRL3_OFFSET 0XFF180178 17522#undef IOU_SLCR_BANK2_CTRL4_OFFSET 17523#define IOU_SLCR_BANK2_CTRL4_OFFSET 0XFF18017C 17524#undef IOU_SLCR_BANK2_CTRL5_OFFSET 17525#define IOU_SLCR_BANK2_CTRL5_OFFSET 0XFF180180 17526#undef IOU_SLCR_BANK2_CTRL6_OFFSET 17527#define IOU_SLCR_BANK2_CTRL6_OFFSET 0XFF180184 17528#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 17529#define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 17530 17531/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/ 17532#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 17533#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 17534#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 17535#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 17536#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 17537#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U 17538 17539/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17540#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 17541#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 17542#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 17543#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 17544#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 17545#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U 17546 17547/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp 17548 t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/ 17549#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 17550#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 17551#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 17552#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 17553#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 17554#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U 17555 17556/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can 17557 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 17558 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc 17559 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ 17560 lk- (Trace Port Clock)*/ 17561#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 17562#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 17563#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 17564#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 17565#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 17566#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U 17567 17568/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data 17569 us)*/ 17570#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 17571#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 17572#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 17573#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 17574#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 17575#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U 17576 17577/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17578#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 17579#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 17580#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 17581#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 17582#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 17583#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U 17584 17585/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp 17586 t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/ 17587#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 17588#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 17589#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 17590#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 17591#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 17592#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U 17593 17594/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can 17595 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 17596 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o 17597 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control 17598 Signal)*/ 17599#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 17600#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 17601#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 17602#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 17603#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 17604#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U 17605 17606/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/ 17607#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 17608#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 17609#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 17610#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 17611#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 17612#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U 17613 17614/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17615#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 17616#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 17617#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 17618#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 17619#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 17620#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U 17621 17622/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp 17623 t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/ 17624#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 17625#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 17626#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 17627#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 17628#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 17629#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U 17630 17631/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can 17632 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 17633 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in 17634 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ 17635#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 17636#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 17637#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 17638#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 17639#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 17640#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U 17641 17642/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/ 17643#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 17644#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 17645#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 17646#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 17647#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 17648#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U 17649 17650/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17651#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 17652#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 17653#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 17654#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 17655#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 17656#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U 17657 17658/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp 17659 t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/ 17660#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 17661#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 17662#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 17663#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 17664#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 17665#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U 17666 17667/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can 17668 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 17669 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 17670 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial 17671 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ 17672#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 17673#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 17674#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 17675#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 17676#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 17677#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U 17678 17679/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data 17680 us)*/ 17681#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 17682#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 17683#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 17684#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 17685#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 17686#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U 17687 17688/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17689#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 17690#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 17691#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 17692#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 17693#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 17694#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U 17695 17696/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp 17697 t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/ 17698#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 17699#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 17700#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 17701#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 17702#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 17703#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U 17704 17705/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can 17706 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 17707 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s 17708 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 17709 utput, tracedq[2]- (Trace Port Databus)*/ 17710#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 17711#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 17712#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 17713#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 17714#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 17715#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U 17716 17717/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/ 17718#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 17719#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 17720#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 17721#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 17722#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 17723#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U 17724 17725/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17726#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 17727#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 17728#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 17729#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 17730#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 17731#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U 17732 17733/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp 17734 t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/ 17735#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 17736#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 17737#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 17738#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 17739#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 17740#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U 17741 17742/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can 17743 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 17744 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 17745 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 17746 trace, Output, tracedq[3]- (Trace Port Databus)*/ 17747#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 17748#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 17749#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 17750#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 17751#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 17752#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U 17753 17754/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/ 17755#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 17756#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 17757#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 17758#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 17759#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 17760#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U 17761 17762/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17763#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 17764#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 17765#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 17766#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 17767#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 17768#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U 17769 17770/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp 17771 t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/ 17772#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 17773#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 17774#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 17775#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 17776#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 17777#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U 17778 17779/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can 17780 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 17781 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 17782 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, 17783 Output, tracedq[4]- (Trace Port Databus)*/ 17784#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 17785#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 17786#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 17787#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 17788#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 17789#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U 17790 17791/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/ 17792#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 17793#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 17794#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 17795#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 17796#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 17797#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U 17798 17799/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17800#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 17801#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 17802#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 17803#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 17804#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 17805#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U 17806 17807/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp 17808 t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/ 17809#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 17810#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 17811#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 17812#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 17813#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 17814#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U 17815 17816/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can 17817 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 17818 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 17819 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 17820 racedq[5]- (Trace Port Databus)*/ 17821#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 17822#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 17823#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 17824#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 17825#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 17826#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U 17827 17828/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe 17829 [0]- (QSPI Upper Databus)*/ 17830#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 17831#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 17832#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 17833#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 17834#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 17835#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U 17836 17837/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 17838#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 17839#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 17840#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 17841#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 17842#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 17843#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U 17844 17845/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp 17846 t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/ 17847#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 17848#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 17849#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 17850#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 17851#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 17852#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U 17853 17854/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can 17855 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 17856 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc 17857 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr 17858 ce Port Databus)*/ 17859#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 17860#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 17861#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 17862#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 17863#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 17864#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U 17865 17866/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe 17867 [1]- (QSPI Upper Databus)*/ 17868#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 17869#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 17870#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 17871#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 17872#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 17873#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U 17874 17875/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ 17876#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 17877#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 17878#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 17879#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 17880#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 17881#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U 17882 17883/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp 17884 t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/ 17885#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 17886#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 17887#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 17888#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 17889#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 17890#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U 17891 17892/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can 17893 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 17894 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 17895 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U 17896 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ 17897#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 17898#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 17899#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 17900#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 17901#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 17902#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U 17903 17904/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe 17905 [2]- (QSPI Upper Databus)*/ 17906#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 17907#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 17908#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 17909#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 17910#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 17911#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U 17912 17913/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ 17914#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 17915#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 17916#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 17917#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 17918#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 17919#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U 17920 17921/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out 17922 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/ 17923#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 17924#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 17925#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 17926#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 17927#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 17928#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U 17929 17930/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c 17931 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 17932 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ 17933 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp 17934 t, tracedq[8]- (Trace Port Databus)*/ 17935#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 17936#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 17937#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 17938#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 17939#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 17940#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U 17941 17942/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe 17943 [3]- (QSPI Upper Databus)*/ 17944#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 17945#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 17946#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 17947#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 17948#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 17949#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U 17950 17951/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ 17952#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 17953#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 17954#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 17955#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 17956#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 17957#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U 17958 17959/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out 17960 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/ 17961#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 17962#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 17963#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 17964#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 17965#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 17966#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U 17967 17968/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c 17969 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 17970 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s 17971 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o 17972 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ 17973#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 17974#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 17975#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 17976#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 17977#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 17978#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U 17979 17980/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/ 17981#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 17982#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 17983#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 17984#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 17985#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 17986#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U 17987 17988/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe 17989 */ 17990#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 17991#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 17992#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 17993#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 17994#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 17995#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U 17996 17997/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out 17998 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/ 17999#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 18000#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
18001#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 18002#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 18003#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 18004#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U 18005 18006/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c 18007 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 18008 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl 18009 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac 18010 dq[10]- (Trace Port Databus)*/ 18011#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 18012#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 18013#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 18014#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 18015#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 18016#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U 18017 18018/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18019#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 18020#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 18021#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 18022#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 18023#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 18024#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U 18025 18026/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/ 18027#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 18028#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 18029#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 18030#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 18031#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 18032#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U 18033 18034/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 18035 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port 18036 3= Not Used*/ 18037#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 18038#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 18039#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 18040#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 18041#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 18042#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U 18043 18044/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c 18045 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 18046 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave 18047 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat 18048 bus)*/ 18049#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 18050#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 18051#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 18052#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 18053#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 18054#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U 18055 18056/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18057#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 18058#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 18059#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 18060#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 18061#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 18062#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U 18063 18064/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/ 18065#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 18066#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 18067#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 18068#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 18069#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 18070#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U 18071 18072/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 18073 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port 18074 3= Not Used*/ 18075#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 18076#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 18077#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 18078#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 18079#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 18080#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U 18081 18082/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c 18083 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 18084 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ 18085 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/ 18086#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 18087#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 18088#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 18089#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 18090#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 18091#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U 18092 18093/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18094#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 18095#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 18096#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 18097#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 18098#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 18099#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U 18100 18101/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/ 18102#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 18103#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 18104#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 18105#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 18106#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 18107#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U 18108 18109/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 18110 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port 18111 3= Not Used*/ 18112#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 18113#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 18114#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 18115#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 18116#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 18117#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U 18118 18119/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c 18120 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 18121 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out 18122 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri 18123 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ 18124#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 18125#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 18126#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 18127#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 18128#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 18129#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U 18130 18131/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18132#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 18133#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 18134#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 18135#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 18136#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 18137#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U 18138 18139/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 18140 ata Bus)*/ 18141#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 18142#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 18143#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 18144#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 18145#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 18146#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U 18147 18148/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 18149 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port 18150 3= Not Used*/ 18151#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 18152#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 18153#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 18154#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 18155#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 18156#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U 18157 18158/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c 18159 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 18160 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 18161 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace 18162 Output, tracedq[14]- (Trace Port Databus)*/ 18163#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 18164#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 18165#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 18166#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 18167#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 18168#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U 18169 18170/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18171#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 18172#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 18173#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 18174#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 18175#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 18176#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U 18177 18178/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 18179 ata Bus)*/ 18180#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 18181#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 18182#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 18183#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 18184#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 18185#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U 18186 18187/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 18188 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port 18189 3= Not Used*/ 18190#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 18191#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 18192#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 18193#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 18194#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 18195#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U 18196 18197/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c 18198 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 18199 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp 18200 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 18201 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ 18202#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 18203#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 18204#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 18205#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 18206#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 18207#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U 18208 18209/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18210#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 18211#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 18212#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 18213#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 18214#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 18215#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U 18216 18217/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 18218 ata Bus)*/ 18219#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 18220#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 18221#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 18222#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 18223#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 18224#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U 18225 18226/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 18227 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port 18228 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18229#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 18230#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 18231#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 18232#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 18233#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 18234#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U 18235 18236/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c 18237 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 18238 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ 18239 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ 18240#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 18241#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 18242#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 18243#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 18244#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 18245#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U 18246 18247/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18248#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 18249#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 18250#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 18251#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 18252#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 18253#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U 18254 18255/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 18256 ata Bus)*/ 18257#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 18258#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 18259#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 18260#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 18261#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 18262#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U 18263 18264/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 18265 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port 18266 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18267#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 18268#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 18269#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 18270#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 18271#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 18272#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U 18273 18274/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c 18275 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 18276 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 18277 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ 18278#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 18279#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 18280#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 18281#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 18282#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 18283#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U 18284 18285/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18286#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 18287#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 18288#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 18289#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 18290#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 18291#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U 18292 18293/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 18294 ata Bus)*/ 18295#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 18296#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 18297#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 18298#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 18299#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 18300#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U 18301 18302/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 18303 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port 18304 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18305#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 18306#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 18307#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 18308#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 18309#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 18310#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U 18311 18312/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c 18313 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 18314 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t 18315 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ 18316#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 18317#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 18318#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 18319#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 18320#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 18321#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U 18322 18323/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18324#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 18325#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 18326#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 18327#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 18328#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 18329#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U 18330 18331/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 18332 ata Bus)*/ 18333#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 18334#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 18335#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 18336#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 18337#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 18338#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U 18339 18340/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman 18341 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 18342 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18343#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 18344#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 18345#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 18346#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 18347#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 18348#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U 18349 18350/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c 18351 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 18352 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 18353 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 18354 UART receiver serial input) 7= Not Used*/ 18355#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 18356#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 18357#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 18358#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 18359#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 18360#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U 18361 18362/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18363#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 18364#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 18365#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 18366#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 18367#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 18368#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U 18369 18370/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/ 18371#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 18372#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 18373#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 18374#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 18375#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 18376#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U 18377 18378/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- 18379 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18380#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 18381#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 18382#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 18383#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 18384#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 18385#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U 18386 18387/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c 18388 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 18389 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp 18390 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 18391 sed*/ 18392#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 18393#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 18394#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 18395#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 18396#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 18397#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U 18398 18399/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18400#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 18401#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 18402#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 18403#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 18404#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 18405#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U 18406 18407/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 18408 ata Bus)*/ 18409#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 18410#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 18411#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 18412#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 18413#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 18414#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U 18415 18416/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in 18417 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper 18418 */ 18419#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 18420#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 18421#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 18422#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 18423#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 18424#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U 18425 18426/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c 18427 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 18428 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s 18429 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o 18430 tput) 7= Not Used*/ 18431#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 18432#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 18433#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 18434#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 18435#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 18436#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U 18437 18438/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18439#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 18440#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 18441#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 18442#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 18443#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 18444#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U 18445 18446/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 18447 ata Bus)*/ 18448#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 18449#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 18450#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 18451#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 18452#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 18453#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U 18454 18455/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test 18456 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex 18457 Tamper)*/ 18458#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 18459#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 18460#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 18461#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 18462#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 18463#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U 18464 18465/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c 18466 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 18467 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, 18468 Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ 18469#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 18470#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 18471#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 18472#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 18473#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 18474#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U 18475 18476/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 18477#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 18478#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 18479#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 18480#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 18481#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 18482#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U 18483 18484/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/ 18485#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 18486#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 18487#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 18488#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 18489#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 18490#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U 18491 18492/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, 18493 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C 18494 U Ext Tamper)*/ 18495#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 18496#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 18497#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 18498#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 18499#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 18500#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U 18501 18502/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c 18503 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 18504 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 18505 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ 18506#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 18507#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 18508#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 18509#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 18510#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 18511#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U 18512 18513/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/ 18514#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 18515#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 18516#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 18517#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 18518#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 18519#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U 18520 18521/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ 18522#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 18523#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 18524#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 18525#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 18526#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 18527#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U 18528 18529/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc 18530 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18531#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 18532#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 18533#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 18534#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 18535#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 18536#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U 18537 18538/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can 18539 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 18540 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock 18541 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 18542 Trace Port Databus)*/ 18543#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 18544#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 18545#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 18546#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 18547#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 18548#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U 18549 18550/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/ 18551#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 18552#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 18553#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 18554#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 18555#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 18556#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U 18557 18558/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ 18559#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 18560#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 18561#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 18562#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 18563#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 18564#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U 18565 18566/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc 18567 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp 18568 t, dp_aux_data_out- (Dp Aux Data)*/ 18569#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 18570#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 18571#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 18572#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 18573#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 18574#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U 18575 18576/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can 18577 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 18578 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ 18579 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 18580 atabus)*/ 18581#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 18582#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 18583#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 18584#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 18585#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 18586#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U 18587 18588/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/ 18589#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 18590#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 18591#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 18592#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 18593#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 18594#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U 18595 18596/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ 18597#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 18598#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 18599#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 18600#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 18601#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 18602#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U 18603 18604/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc 18605 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ 18606#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 18607#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 18608#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 18609#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 18610#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 18611#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U 18612 18613/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can 18614 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 18615 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i 18616 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ 18617#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 18618#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 18619#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 18620#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 18621#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 18622#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U 18623 18624/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/ 18625#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 18626#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 18627#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 18628#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 18629#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 18630#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U 18631 18632/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18633#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 18634#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 18635#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 18636#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 18637#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 18638#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U 18639 18640/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc 18641 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp 18642 t, dp_aux_data_out- (Dp Aux Data)*/ 18643#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 18644#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 18645#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 18646#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 18647#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 18648#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U 18649 18650/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can 18651 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 18652 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] 18653 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu 18654 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ 18655#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 18656#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 18657#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 18658#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 18659#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 18660#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U 18661 18662/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/ 18663#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 18664#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 18665#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 18666#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 18667#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 18668#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U 18669 18670/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18671#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 18672#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 18673#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 18674#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 18675#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 18676#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U 18677 18678/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc 18679 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ 18680#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 18681#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 18682#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 18683#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 18684#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 18685#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U 18686 18687/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can 18688 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 18689 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so 18690 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output 18691 tracedq[8]- (Trace Port Databus)*/ 18692#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 18693#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 18694#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 18695#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 18696#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 18697#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U 18698 18699/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/ 18700#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 18701#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 18702#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 18703#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 18704#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 18705#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U 18706 18707/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18708#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 18709#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 18710#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 18711#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 18712#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 18713#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U 18714 18715/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc 18716 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18717#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 18718#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 18719#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 18720#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 18721#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 18722#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U 18723 18724/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can 18725 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 18726 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi 18727 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out 18728 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ 18729#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 18730#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 18731#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 18732#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 18733#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 18734#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U 18735 18736/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/ 18737#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 18738#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 18739#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 18740#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 18741#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 18742#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U 18743 18744/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe 18745 */ 18746#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 18747#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 18748#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 18749#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 18750#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 18751#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U 18752 18753/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S 18754 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18755#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 18756#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 18757#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 18758#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 18759#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 18760#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U 18761 18762/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can 18763 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 18764 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi 18765 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 18766 race, Output, tracedq[10]- (Trace Port Databus)*/ 18767#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 18768#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 18769#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 18770#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 18771#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 18772#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U 18773 18774/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/ 18775#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 18776#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 18777#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 18778#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 18779#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 18780#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U 18781 18782/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18783#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 18784#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 18785#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 18786#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 18787#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 18788#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U 18789 18790/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S 18791 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ 18792#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 18793#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 18794#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 18795#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 18796#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 18797#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U 18798 18799/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can 18800 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 18801 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t 18802 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced 18803 [11]- (Trace Port Databus)*/ 18804#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 18805#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 18806#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 18807#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 18808#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 18809#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U 18810 18811/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/ 18812#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 18813#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 18814#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 18815#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 18816#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 18817#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U 18818 18819/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18820#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 18821#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 18822#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 18823#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 18824#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 18825#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U 18826 18827/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S 18828 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out 18829 ut, dp_aux_data_out- (Dp Aux Data)*/ 18830#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 18831#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 18832#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 18833#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 18834#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 18835#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U 18836 18837/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can 18838 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 18839 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 18840 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P 18841 rt Databus)*/ 18842#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 18843#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 18844#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 18845#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 18846#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 18847#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U 18848 18849/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/ 18850#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 18851#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 18852#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 18853#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 18854#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 18855#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U 18856 18857/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18858#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 18859#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 18860#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 18861#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 18862#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 18863#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U 18864 18865/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S 18866 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ 18867#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 18868#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 18869#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 18870#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 18871#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 18872#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U 18873 18874/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can 18875 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 18876 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 18877 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 18878 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ 18879#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 18880#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 18881#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 18882#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 18883#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 18884#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U 18885 18886/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/ 18887#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 18888#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 18889#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 18890#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 18891#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 18892#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U 18893 18894/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18895#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 18896#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 18897#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 18898#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 18899#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 18900#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U 18901 18902/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S 18903 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out 18904 ut, dp_aux_data_out- (Dp Aux Data)*/ 18905#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 18906#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 18907#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 18908#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 18909#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 18910#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U 18911 18912/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c 18913 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 18914 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 18915 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace 18916 Output, tracedq[14]- (Trace Port Databus)*/ 18917#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 18918#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 18919#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 18920#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 18921#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 18922#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U 18923 18924/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/ 18925#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 18926#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 18927#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 18928#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 18929#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 18930#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U 18931 18932/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ 18933#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 18934#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 18935#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 18936#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 18937#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 18938#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U 18939 18940/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S 18941 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ 18942#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 18943#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 18944#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 18945#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 18946#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 18947#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U 18948 18949/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c 18950 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 18951 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp 18952 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 18953 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ 18954#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 18955#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 18956#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 18957#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 18958#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 18959#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U 18960 18961/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/ 18962#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 18963#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 18964#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 18965#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 18966#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 18967#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U 18968 18969/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 18970#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 18971#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 18972#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 18973#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 18974#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 18975#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U 18976 18977/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ 18978#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 18979#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 18980#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 18981#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 18982#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 18983#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U 18984 18985/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c 18986 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 18987 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo 18988 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- 18989 (Trace Port Clock)*/ 18990#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 18991#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 18992#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 18993#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 18994#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 18995#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U 18996 18997/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/ 18998#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 18999#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 19000#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
19001#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 19002#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 19003#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U 19004 19005/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19006#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 19007#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 19008#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 19009#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 19010#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 19011#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U 19012 19013/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i 19014 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/ 19015#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 19016#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 19017#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 19018#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 19019#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 19020#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U 19021 19022/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c 19023 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 19024 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav 19025 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port 19026 Control Signal)*/ 19027#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 19028#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 19029#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 19030#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 19031#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 19032#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U 19033 19034/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/ 19035#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 19036#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 19037#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 19038#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 19039#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 19040#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U 19041 19042/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19043#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 19044#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 19045#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 19046#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 19047#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 19048#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U 19049 19050/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman 19051 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/ 19052#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 19053#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 19054#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 19055#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 19056#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 19057#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U 19058 19059/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c 19060 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 19061 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk 19062 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ 19063#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 19064#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 19065#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 19066#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 19067#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 19068#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U 19069 19070/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/ 19071#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 19072#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 19073#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 19074#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 19075#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 19076#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U 19077 19078/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19079#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 19080#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 19081#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 19082#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 19083#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 19084#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U 19085 19086/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 19087 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/ 19088#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 19089#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 19090#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 19091#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 19092#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 19093#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U 19094 19095/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c 19096 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 19097 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ 19098 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in 19099 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ 19100#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 19101#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 19102#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 19103#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 19104#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 19105#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U 19106 19107/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/ 19108#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 19109#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 19110#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 19111#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 19112#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 19113#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U 19114 19115/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19116#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 19117#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 19118#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 19119#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 19120#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 19121#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U 19122 19123/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 19124 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/ 19125#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 19126#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 19127#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 19128#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 19129#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 19130#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U 19131 19132/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c 19133 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 19134 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ 19135 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp 19136 t, tracedq[2]- (Trace Port Databus)*/ 19137#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 19138#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 19139#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 19140#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 19141#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 19142#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U 19143 19144/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/ 19145#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 19146#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 19147#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 19148#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 19149#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 19150#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U 19151 19152/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19153#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 19154#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 19155#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 19156#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 19157#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 19158#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U 19159 19160/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 19161 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ 19162#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 19163#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 19164#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 19165#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 19166#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 19167#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U 19168 19169/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c 19170 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 19171 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s 19172 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o 19173 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/ 19174#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 19175#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 19176#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 19177#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 19178#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 19179#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U 19180 19181/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/ 19182#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 19183#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 19184#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 19185#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 19186#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 19187#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U 19188 19189/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19190#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 19191#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 19192#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 19193#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 19194#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 19195#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U 19196 19197/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 19198 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ 19199#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 19200#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 19201#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 19202#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 19203#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 19204#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U 19205 19206/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c 19207 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 19208 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s 19209 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 19210 Not Used*/ 19211#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 19212#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 19213#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 19214#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 19215#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 19216#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U 19217 19218/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/ 19219#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 19220#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 19221#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 19222#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 19223#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 19224#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U 19225 19226/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19227#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 19228#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 19229#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 19230#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 19231#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 19232#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U 19233 19234/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 19235 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ 19236#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 19237#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 19238#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 19239#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 19240#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 19241#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U 19242 19243/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c 19244 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 19245 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 19246 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ 19247#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 19248#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 19249#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 19250#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 19251#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 19252#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U 19253 19254/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/ 19255#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 19256#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 19257#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 19258#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 19259#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 19260#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U 19261 19262/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19263#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 19264#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 19265#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 19266#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 19267#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 19268#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U 19269 19270/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 19271 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ 19272#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 19273#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 19274#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 19275#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 19276#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 19277#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U 19278 19279/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c 19280 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 19281 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt 19282 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ 19283#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 19284#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 19285#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 19286#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 19287#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 19288#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U 19289 19290/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/ 19291#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 19292#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 19293#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 19294#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 19295#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 19296#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U 19297 19298/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19299#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 19300#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 19301#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 19302#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 19303#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 19304#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U 19305 19306/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 19307 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ 19308#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 19309#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 19310#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 19311#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 19312#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 19313#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U 19314 19315/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c 19316 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 19317 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi 19318 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd 19319 (UART transmitter serial output) 7= Not Used*/ 19320#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 19321#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 19322#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 19323#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 19324#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 19325#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U 19326 19327/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/ 19328#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 19329#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 19330#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 19331#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 19332#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 19333#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U 19334 19335/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19336#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 19337#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 19338#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 19339#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 19340#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 19341#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U 19342 19343/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 19344 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ 19345#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 19346#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 19347#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 19348#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 19349#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 19350#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U 19351 19352/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c 19353 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 19354 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 19355 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U 19356 ed*/ 19357#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 19358#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 19359#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 19360#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 19361#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 19362#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U 19363 19364/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/ 19365#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 19366#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 19367#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 19368#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 19369#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 19370#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U 19371 19372/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19373#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 19374#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 19375#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 19376#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 19377#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 19378#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U 19379 19380/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 19381 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ 19382#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 19383#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 19384#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 19385#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 19386#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 19387#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U 19388 19389/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c 19390 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 19391 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp 19392 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 19393 7= Not Used*/ 19394#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 19395#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 19396#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 19397#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 19398#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 19399#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U 19400 19401/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ 19402#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 19403#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 19404#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 19405#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 19406#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 19407#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U 19408 19409/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19410#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 19411#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 19412#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 19413#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 19414#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 19415#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U 19416 19417/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c 19418 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ 19419#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 19420#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 19421#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 19422#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 19423#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 19424#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U 19425 19426/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c 19427 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 19428 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 19429 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ 19430#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 19431#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 19432#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 19433#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 19434#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 19435#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U 19436 19437/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ 19438#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 19439#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 19440#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 19441#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 19442#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 19443#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U 19444 19445/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 19446#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 19447#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 19448#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 19449#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 19450#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 19451#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U 19452 19453/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/ 19454#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 19455#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 19456#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 19457#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 19458#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 19459#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U 19460 19461/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c 19462 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 19463 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp 19464 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter 19465 serial output) 7= Not Used*/ 19466#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 19467#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 19468#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 19469#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 19470#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 19471#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U 19472 19473/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/ 19474#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 19475#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 19476#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 19477#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 19478#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 19479#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U 19480 19481/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/ 19482#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 19483#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 19484#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 19485#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 19486#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 19487#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U 19488 19489/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19490#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 19491#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 19492#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 19493#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 19494#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 19495#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U 19496 19497/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can 19498 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 19499 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc 19500 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ 19501 lk- (Trace Port Clock)*/ 19502#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 19503#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 19504#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 19505#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 19506#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 19507#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U 19508 19509/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/ 19510#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 19511#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 19512#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 19513#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 19514#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 19515#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U 19516 19517/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/ 19518#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 19519#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 19520#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 19521#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 19522#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 19523#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U 19524 19525/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19526#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 19527#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 19528#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 19529#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 19530#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 19531#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U 19532 19533/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can 19534 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 19535 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o 19536 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control 19537 Signal)*/ 19538#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 19539#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 19540#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 19541#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 19542#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 19543#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U 19544 19545/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/ 19546#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 19547#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 19548#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 19549#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 19550#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 19551#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U 19552 19553/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19554 ata[2]- (ULPI data bus)*/ 19555#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 19556#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 19557#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 19558#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 19559#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 19560#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U 19561 19562/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19563#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 19564#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 19565#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 19566#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 19567#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 19568#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U 19569 19570/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can 19571 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 19572 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in 19573 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ 19574#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 19575#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 19576#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 19577#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 19578#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 19579#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U 19580 19581/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/ 19582#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 19583#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 19584#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 19585#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 19586#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 19587#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U 19588 19589/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/ 19590#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 19591#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 19592#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 19593#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 19594#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 19595#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U 19596 19597/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19598#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 19599#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 19600#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 19601#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 19602#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 19603#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U 19604 19605/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can 19606 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 19607 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 19608 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial 19609 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ 19610#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 19611#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 19612#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 19613#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 19614#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 19615#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U 19616 19617/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/ 19618#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 19619#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 19620#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 19621#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 19622#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 19623#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U 19624 19625/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19626 ata[0]- (ULPI data bus)*/ 19627#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 19628#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 19629#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 19630#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 19631#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 19632#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U 19633 19634/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19635#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 19636#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 19637#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 19638#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 19639#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 19640#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U 19641 19642/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can 19643 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 19644 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s 19645 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 19646 utput, tracedq[2]- (Trace Port Databus)*/ 19647#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 19648#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 19649#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 19650#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 19651#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 19652#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U 19653 19654/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/ 19655#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 19656#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 19657#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 19658#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 19659#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 19660#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U 19661 19662/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19663 ata[1]- (ULPI data bus)*/ 19664#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 19665#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 19666#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 19667#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 19668#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 19669#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U 19670 19671/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19672#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 19673#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 19674#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 19675#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 19676#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 19677#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U 19678 19679/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can 19680 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 19681 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 19682 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 19683 trace, Output, tracedq[3]- (Trace Port Databus)*/ 19684#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 19685#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 19686#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 19687#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 19688#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 19689#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U 19690 19691/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/ 19692#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 19693#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 19694#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 19695#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 19696#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 19697#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U 19698 19699/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/ 19700#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 19701#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 19702#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 19703#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 19704#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 19705#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U 19706 19707/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19708#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 19709#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 19710#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 19711#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 19712#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 19713#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U 19714 19715/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can 19716 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal 19717 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock 19718 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 19719 Trace Port Databus)*/ 19720#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 19721#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 19722#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 19723#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 19724#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 19725#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U 19726 19727/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/ 19728#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 19729#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 19730#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 19731#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 19732#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 19733#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U 19734 19735/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19736 ata[3]- (ULPI data bus)*/ 19737#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 19738#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 19739#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 19740#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 19741#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 19742#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U 19743 19744/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19745#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 19746#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 19747#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 19748#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 19749#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 19750#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U 19751 19752/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can 19753 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa 19754 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ 19755 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 19756 atabus)*/ 19757#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 19758#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 19759#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 19760#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 19761#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 19762#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U 19763 19764/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/ 19765#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 19766#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 19767#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 19768#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 19769#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 19770#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U 19771 19772/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19773 ata[4]- (ULPI data bus)*/ 19774#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 19775#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 19776#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 19777#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 19778#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 19779#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U 19780 19781/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19782#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 19783#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 19784#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 19785#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 19786#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 19787#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U 19788 19789/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can 19790 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa 19791 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i 19792 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ 19793#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 19794#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 19795#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 19796#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 19797#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 19798#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U 19799 19800/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/ 19801#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 19802#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 19803#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 19804#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 19805#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 19806#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U 19807 19808/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19809 ata[5]- (ULPI data bus)*/ 19810#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 19811#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 19812#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 19813#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 19814#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 19815#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U 19816 19817/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19818#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 19819#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 19820#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 19821#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 19822#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 19823#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U 19824 19825/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can 19826 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal 19827 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] 19828 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu 19829 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ 19830#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 19831#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 19832#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 19833#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 19834#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 19835#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U 19836 19837/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/ 19838#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 19839#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 19840#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 19841#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 19842#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 19843#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U 19844 19845/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19846 ata[6]- (ULPI data bus)*/ 19847#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 19848#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 19849#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 19850#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 19851#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 19852#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U 19853 19854/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19855#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 19856#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 19857#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 19858#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 19859#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 19860#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U 19861 19862/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c 19863 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 19864 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ 19865 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp 19866 t, tracedq[8]- (Trace Port Databus)*/ 19867#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 19868#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 19869#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 19870#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 19871#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 19872#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U 19873 19874/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/ 19875#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 19876#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 19877#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 19878#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 19879#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 19880#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U 19881 19882/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ 19883 ata[7]- (ULPI data bus)*/ 19884#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 19885#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 19886#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 19887#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 19888#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 19889#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U 19890 19891/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ 19892#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 19893#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 19894#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 19895#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 19896#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 19897#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U 19898 19899/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c 19900 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 19901 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s 19902 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o 19903 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ 19904#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 19905#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 19906#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 19907#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 19908#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 19909#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U 19910 19911/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/ 19912#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 19913#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 19914#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 19915#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 19916#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 19917#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U 19918 19919/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/ 19920#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 19921#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 19922#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 19923#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 19924#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 19925#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U 19926 19927/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ 19928#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 19929#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 19930#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 19931#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 19932#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 19933#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U 19934 19935/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c 19936 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 19937 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s 19938 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 19939 trace, Output, tracedq[10]- (Trace Port Databus)*/ 19940#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 19941#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 19942#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 19943#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 19944#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 19945#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U 19946 19947/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/ 19948#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 19949#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 19950#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 19951#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 19952#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 19953#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U 19954 19955/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/ 19956#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 19957#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 19958#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 19959#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 19960#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 19961#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U 19962 19963/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/ 19964#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 19965#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 19966#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 19967#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 19968#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 19969#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U 19970 19971/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c 19972 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 19973 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= 19974 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac 19975 dq[11]- (Trace Port Databus)*/ 19976#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 19977#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 19978#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 19979#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 19980#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 19981#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U 19982 19983/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/ 19984#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 19985#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 19986#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 19987#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 19988#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 19989#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U 19990 19991/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 19992 ata[2]- (ULPI data bus)*/ 19993#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 19994#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 19995#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 19996#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 19997#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 19998#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U 19999 20000/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
20001 Indicator) 2= Not Used 3= Not Used*/ 20002#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 20003#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 20004#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 20005#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 20006#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 20007#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U 20008 20009/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c 20010 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 20011 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt 20012 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace 20013 Port Databus)*/ 20014#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 20015#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 20016#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 20017#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 20018#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 20019#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U 20020 20021/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/ 20022#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 20023#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 20024#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 20025#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 20026#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 20027#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U 20028 20029/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/ 20030#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 20031#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 20032#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 20033#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 20034#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 20035#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U 20036 20037/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 20038 bit Data bus) 2= Not Used 3= Not Used*/ 20039#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 20040#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 20041#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 20042#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 20043#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 20044#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U 20045 20046/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c 20047 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 20048 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi 20049 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd 20050 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ 20051#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 20052#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 20053#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 20054#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 20055#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 20056#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U 20057 20058/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/ 20059#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 20060#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 20061#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 20062#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 20063#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 20064#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U 20065 20066/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20067 ata[0]- (ULPI data bus)*/ 20068#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 20069#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 20070#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 20071#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 20072#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 20073#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U 20074 20075/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 20076 bit Data bus) 2= Not Used 3= Not Used*/ 20077#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 20078#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 20079#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 20080#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 20081#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 20082#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U 20083 20084/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c 20085 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 20086 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 20087 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace 20088 Output, tracedq[14]- (Trace Port Databus)*/ 20089#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 20090#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 20091#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 20092#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 20093#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 20094#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U 20095 20096/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/ 20097#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 20098#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 20099#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 20100#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 20101#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 20102#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U 20103 20104/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20105 ata[1]- (ULPI data bus)*/ 20106#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 20107#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 20108#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 20109#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 20110#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 20111#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U 20112 20113/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 20114 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ 20115#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 20116#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 20117#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 20118#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 20119#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 20120#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U 20121 20122/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c 20123 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 20124 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp 20125 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 20126 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ 20127#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 20128#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 20129#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 20130#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 20131#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 20132#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U 20133 20134/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/ 20135#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 20136#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 20137#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 20138#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 20139#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 20140#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U 20141 20142/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/ 20143#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 20144#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 20145#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 20146#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 20147#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 20148#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U 20149 20150/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 20151 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ 20152#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 20153#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 20154#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 20155#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 20156#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 20157#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U 20158 20159/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c 20160 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 20161 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp 20162 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 20163 sed*/ 20164#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 20165#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 20166#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 20167#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 20168#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 20169#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U 20170 20171/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/ 20172#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 20173#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 20174#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 20175#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 20176#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 20177#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U 20178 20179/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20180 ata[3]- (ULPI data bus)*/ 20181#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 20182#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 20183#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 20184#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 20185#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 20186#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U 20187 20188/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 20189 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ 20190#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 20191#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 20192#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 20193#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 20194#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 20195#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U 20196 20197/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c 20198 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 20199 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 20200 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ 20201#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 20202#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 20203#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 20204#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 20205#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 20206#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U 20207 20208/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/ 20209#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 20210#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 20211#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 20212#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 20213#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 20214#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U 20215 20216/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20217 ata[4]- (ULPI data bus)*/ 20218#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 20219#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 20220#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 20221#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 20222#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 20223#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U 20224 20225/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 20226 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ 20227#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 20228#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 20229#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 20230#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 20231#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 20232#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U 20233 20234/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c 20235 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 20236 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N 20237 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ 20238#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 20239#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 20240#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 20241#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 20242#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 20243#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U 20244 20245/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/ 20246#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 20247#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 20248#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 20249#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 20250#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 20251#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U 20252 20253/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20254 ata[5]- (ULPI data bus)*/ 20255#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 20256#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 20257#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 20258#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 20259#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 20260#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U 20261 20262/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 20263 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ 20264#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 20265#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 20266#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 20267#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 20268#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 20269#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U 20270 20271/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c 20272 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 20273 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 20274 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ 20275#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 20276#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 20277#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 20278#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 20279#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 20280#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U 20281 20282/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/ 20283#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 20284#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 20285#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 20286#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 20287#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 20288#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U 20289 20290/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20291 ata[6]- (ULPI data bus)*/ 20292#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 20293#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 20294#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 20295#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 20296#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 20297#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U 20298 20299/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 20300 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ 20301#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 20302#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 20303#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 20304#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 20305#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 20306#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U 20307 20308/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c 20309 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign 20310 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ 20311 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ 20312#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 20313#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 20314#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 20315#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 20316#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 20317#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U 20318 20319/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/ 20320#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 20321#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 20322#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 20323#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 20324#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 20325#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U 20326 20327/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ 20328 ata[7]- (ULPI data bus)*/ 20329#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 20330#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 20331#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 20332#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 20333#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 20334#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U 20335 20336/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma 20337 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ 20338#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 20339#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 20340#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 20341#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 20342#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 20343#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U 20344 20345/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c 20346 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig 20347 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s 20348 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ 20349#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 20350#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 20351#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 20352#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 20353#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 20354#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U 20355 20356/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 20357#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 20358#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 20359#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 20360#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 20361#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 20362#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U 20363 20364/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 20365#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 20366#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 20367#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 20368#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 20369#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 20370#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U 20371 20372/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio 20373 _clk_out- (SDSDIO clock) 3= Not Used*/ 20374#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 20375#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 20376#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 20377#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 20378#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 20379#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U 20380 20381/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c 20382 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig 20383 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock 20384 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/ 20385#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 20386#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 20387#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 20388#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 20389#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 20390#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U 20391 20392/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ 20393#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 20394#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 20395#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 20396#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 20397#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 20398#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U 20399 20400/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ 20401#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 20402#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 20403#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 20404#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 20405#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 20406#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U 20407 20408/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ 20409#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 20410#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 20411#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 20412#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 20413#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 20414#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U 20415 20416/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c 20417 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign 20418 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD 20419 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o 20420 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/ 20421#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 20422#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 20423#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 20424#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 20425#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 20426#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U 20427 20428/*Master Tri-state Enable for pin 0, active high*/ 20429#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 20430#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 20431#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 20432#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF 20433#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 20434#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U 20435 20436/*Master Tri-state Enable for pin 1, active high*/ 20437#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 20438#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 20439#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 20440#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF 20441#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 20442#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U 20443 20444/*Master Tri-state Enable for pin 2, active high*/ 20445#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 20446#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 20447#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 20448#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF 20449#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 20450#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U 20451 20452/*Master Tri-state Enable for pin 3, active high*/ 20453#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 20454#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 20455#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 20456#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF 20457#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 20458#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U 20459 20460/*Master Tri-state Enable for pin 4, active high*/ 20461#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 20462#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 20463#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 20464#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF 20465#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 20466#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U 20467 20468/*Master Tri-state Enable for pin 5, active high*/ 20469#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 20470#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 20471#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 20472#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF 20473#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 20474#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U 20475 20476/*Master Tri-state Enable for pin 6, active high*/ 20477#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 20478#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 20479#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 20480#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF 20481#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 20482#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U 20483 20484/*Master Tri-state Enable for pin 7, active high*/ 20485#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 20486#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 20487#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 20488#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF 20489#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 20490#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U 20491 20492/*Master Tri-state Enable for pin 8, active high*/ 20493#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 20494#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 20495#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 20496#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF 20497#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 20498#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U 20499 20500/*Master Tri-state Enable for pin 9, active high*/ 20501#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 20502#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 20503#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 20504#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF 20505#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 20506#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U 20507 20508/*Master Tri-state Enable for pin 10, active high*/ 20509#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 20510#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 20511#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 20512#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF 20513#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 20514#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U 20515 20516/*Master Tri-state Enable for pin 11, active high*/ 20517#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 20518#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 20519#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 20520#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF 20521#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 20522#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U 20523 20524/*Master Tri-state Enable for pin 12, active high*/ 20525#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 20526#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 20527#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 20528#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF 20529#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 20530#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U 20531 20532/*Master Tri-state Enable for pin 13, active high*/ 20533#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 20534#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 20535#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 20536#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF 20537#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 20538#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U 20539 20540/*Master Tri-state Enable for pin 14, active high*/ 20541#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 20542#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 20543#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 20544#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF 20545#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 20546#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U 20547 20548/*Master Tri-state Enable for pin 15, active high*/ 20549#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 20550#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 20551#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 20552#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF 20553#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 20554#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U 20555 20556/*Master Tri-state Enable for pin 16, active high*/ 20557#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 20558#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 20559#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 20560#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF 20561#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 20562#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U 20563 20564/*Master Tri-state Enable for pin 17, active high*/ 20565#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 20566#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 20567#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 20568#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF 20569#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 20570#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U 20571 20572/*Master Tri-state Enable for pin 18, active high*/ 20573#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 20574#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 20575#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 20576#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF 20577#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 20578#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U 20579 20580/*Master Tri-state Enable for pin 19, active high*/ 20581#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 20582#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 20583#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 20584#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF 20585#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 20586#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U 20587 20588/*Master Tri-state Enable for pin 20, active high*/ 20589#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 20590#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20591#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 20592#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF 20593#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 20594#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U 20595 20596/*Master Tri-state Enable for pin 21, active high*/ 20597#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 20598#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 20599#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 20600#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF 20601#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 20602#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U 20603 20604/*Master Tri-state Enable for pin 22, active high*/ 20605#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 20606#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 20607#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 20608#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF 20609#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 20610#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U 20611 20612/*Master Tri-state Enable for pin 23, active high*/ 20613#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 20614#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 20615#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 20616#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF 20617#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 20618#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U 20619 20620/*Master Tri-state Enable for pin 24, active high*/ 20621#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 20622#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 20623#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 20624#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF 20625#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 20626#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U 20627 20628/*Master Tri-state Enable for pin 25, active high*/ 20629#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 20630#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 20631#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 20632#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF 20633#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 20634#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U 20635 20636/*Master Tri-state Enable for pin 26, active high*/ 20637#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 20638#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 20639#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 20640#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF 20641#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 20642#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U 20643 20644/*Master Tri-state Enable for pin 27, active high*/ 20645#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 20646#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 20647#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 20648#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF 20649#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 20650#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U 20651 20652/*Master Tri-state Enable for pin 28, active high*/ 20653#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 20654#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 20655#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 20656#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF 20657#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 20658#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U 20659 20660/*Master Tri-state Enable for pin 29, active high*/ 20661#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 20662#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 20663#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 20664#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF 20665#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 20666#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U 20667 20668/*Master Tri-state Enable for pin 30, active high*/ 20669#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 20670#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 20671#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 20672#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF 20673#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 20674#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U 20675 20676/*Master Tri-state Enable for pin 31, active high*/ 20677#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 20678#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 20679#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 20680#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF 20681#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 20682#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U 20683 20684/*Master Tri-state Enable for pin 32, active high*/ 20685#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 20686#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 20687#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 20688#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF 20689#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 20690#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U 20691 20692/*Master Tri-state Enable for pin 33, active high*/ 20693#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 20694#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 20695#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 20696#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF 20697#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 20698#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U 20699 20700/*Master Tri-state Enable for pin 34, active high*/ 20701#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 20702#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 20703#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 20704#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF 20705#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 20706#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U 20707 20708/*Master Tri-state Enable for pin 35, active high*/ 20709#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 20710#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 20711#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 20712#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF 20713#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 20714#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U 20715 20716/*Master Tri-state Enable for pin 36, active high*/ 20717#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 20718#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 20719#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 20720#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF 20721#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 20722#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U 20723 20724/*Master Tri-state Enable for pin 37, active high*/ 20725#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 20726#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 20727#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 20728#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF 20729#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 20730#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U 20731 20732/*Master Tri-state Enable for pin 38, active high*/ 20733#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 20734#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 20735#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 20736#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF 20737#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 20738#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U 20739 20740/*Master Tri-state Enable for pin 39, active high*/ 20741#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 20742#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 20743#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 20744#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF 20745#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 20746#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U 20747 20748/*Master Tri-state Enable for pin 40, active high*/ 20749#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 20750#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 20751#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 20752#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF 20753#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 20754#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U 20755 20756/*Master Tri-state Enable for pin 41, active high*/ 20757#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 20758#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 20759#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 20760#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF 20761#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 20762#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U 20763 20764/*Master Tri-state Enable for pin 42, active high*/ 20765#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 20766#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 20767#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 20768#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF 20769#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 20770#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U 20771 20772/*Master Tri-state Enable for pin 43, active high*/ 20773#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 20774#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 20775#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 20776#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF 20777#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 20778#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U 20779 20780/*Master Tri-state Enable for pin 44, active high*/ 20781#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 20782#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 20783#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 20784#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF 20785#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 20786#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U 20787 20788/*Master Tri-state Enable for pin 45, active high*/ 20789#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 20790#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 20791#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 20792#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF 20793#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 20794#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U 20795 20796/*Master Tri-state Enable for pin 46, active high*/ 20797#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 20798#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 20799#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 20800#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF 20801#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 20802#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U 20803 20804/*Master Tri-state Enable for pin 47, active high*/ 20805#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 20806#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 20807#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 20808#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF 20809#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 20810#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U 20811 20812/*Master Tri-state Enable for pin 48, active high*/ 20813#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 20814#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 20815#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 20816#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF 20817#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 20818#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U 20819 20820/*Master Tri-state Enable for pin 49, active high*/ 20821#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 20822#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 20823#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 20824#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF 20825#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 20826#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U 20827 20828/*Master Tri-state Enable for pin 50, active high*/ 20829#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 20830#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 20831#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 20832#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF 20833#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 20834#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U 20835 20836/*Master Tri-state Enable for pin 51, active high*/ 20837#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 20838#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 20839#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 20840#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF 20841#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 20842#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U 20843 20844/*Master Tri-state Enable for pin 52, active high*/ 20845#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 20846#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20847#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 20848#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF 20849#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 20850#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U 20851 20852/*Master Tri-state Enable for pin 53, active high*/ 20853#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 20854#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 20855#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 20856#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF 20857#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 20858#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U 20859 20860/*Master Tri-state Enable for pin 54, active high*/ 20861#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 20862#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 20863#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 20864#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF 20865#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 20866#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U 20867 20868/*Master Tri-state Enable for pin 55, active high*/ 20869#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 20870#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 20871#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 20872#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF 20873#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 20874#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U 20875 20876/*Master Tri-state Enable for pin 56, active high*/ 20877#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 20878#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 20879#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 20880#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF 20881#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 20882#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U 20883 20884/*Master Tri-state Enable for pin 57, active high*/ 20885#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 20886#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 20887#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 20888#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF 20889#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 20890#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U 20891 20892/*Master Tri-state Enable for pin 58, active high*/ 20893#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 20894#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 20895#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 20896#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF 20897#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 20898#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U 20899 20900/*Master Tri-state Enable for pin 59, active high*/ 20901#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 20902#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 20903#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 20904#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF 20905#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 20906#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U 20907 20908/*Master Tri-state Enable for pin 60, active high*/ 20909#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 20910#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 20911#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 20912#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF 20913#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 20914#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U 20915 20916/*Master Tri-state Enable for pin 61, active high*/ 20917#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 20918#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 20919#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 20920#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF 20921#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 20922#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U 20923 20924/*Master Tri-state Enable for pin 62, active high*/ 20925#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 20926#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 20927#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 20928#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF 20929#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 20930#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U 20931 20932/*Master Tri-state Enable for pin 63, active high*/ 20933#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 20934#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 20935#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 20936#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF 20937#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 20938#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U 20939 20940/*Master Tri-state Enable for pin 64, active high*/ 20941#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 20942#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 20943#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 20944#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF 20945#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 20946#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U 20947 20948/*Master Tri-state Enable for pin 65, active high*/ 20949#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 20950#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 20951#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 20952#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF 20953#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 20954#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U 20955 20956/*Master Tri-state Enable for pin 66, active high*/ 20957#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 20958#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 20959#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 20960#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF 20961#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 20962#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U 20963 20964/*Master Tri-state Enable for pin 67, active high*/ 20965#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 20966#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 20967#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 20968#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF 20969#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 20970#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U 20971 20972/*Master Tri-state Enable for pin 68, active high*/ 20973#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 20974#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 20975#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 20976#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF 20977#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 20978#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U 20979 20980/*Master Tri-state Enable for pin 69, active high*/ 20981#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 20982#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 20983#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 20984#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF 20985#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 20986#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U 20987 20988/*Master Tri-state Enable for pin 70, active high*/ 20989#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 20990#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 20991#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 20992#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF 20993#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 20994#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U 20995 20996/*Master Tri-state Enable for pin 71, active high*/ 20997#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 20998#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 20999#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 21000#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF
21001#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 21002#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U 21003 21004/*Master Tri-state Enable for pin 72, active high*/ 21005#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 21006#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 21007#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 21008#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF 21009#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 21010#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U 21011 21012/*Master Tri-state Enable for pin 73, active high*/ 21013#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 21014#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 21015#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 21016#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF 21017#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 21018#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U 21019 21020/*Master Tri-state Enable for pin 74, active high*/ 21021#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 21022#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 21023#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 21024#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF 21025#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 21026#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U 21027 21028/*Master Tri-state Enable for pin 75, active high*/ 21029#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 21030#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 21031#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 21032#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF 21033#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 21034#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U 21035 21036/*Master Tri-state Enable for pin 76, active high*/ 21037#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 21038#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 21039#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 21040#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF 21041#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 21042#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U 21043 21044/*Master Tri-state Enable for pin 77, active high*/ 21045#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 21046#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 21047#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 21048#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF 21049#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 21050#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U 21051 21052/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21053#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 21054#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 21055#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 21056#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 21057#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 21058#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U 21059 21060/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21061#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 21062#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 21063#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 21064#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 21065#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 21066#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U 21067 21068/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21069#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 21070#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 21071#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 21072#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 21073#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 21074#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U 21075 21076/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21077#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 21078#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 21079#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 21080#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 21081#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 21082#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U 21083 21084/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21085#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 21086#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 21087#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 21088#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 21089#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 21090#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U 21091 21092/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21093#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 21094#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 21095#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 21096#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 21097#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 21098#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U 21099 21100/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21101#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 21102#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 21103#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 21104#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 21105#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 21106#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U 21107 21108/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21109#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 21110#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 21111#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 21112#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 21113#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 21114#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U 21115 21116/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21117#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 21118#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 21119#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 21120#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 21121#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 21122#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U 21123 21124/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21125#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 21126#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 21127#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 21128#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 21129#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 21130#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U 21131 21132/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21133#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 21134#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 21135#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 21136#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 21137#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 21138#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U 21139 21140/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21141#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 21142#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 21143#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 21144#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 21145#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 21146#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U 21147 21148/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21149#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 21150#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 21151#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 21152#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 21153#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 21154#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U 21155 21156/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21157#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 21158#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 21159#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 21160#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 21161#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 21162#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U 21163 21164/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21165#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 21166#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 21167#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 21168#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 21169#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 21170#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U 21171 21172/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21173#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 21174#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 21175#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 21176#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 21177#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 21178#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U 21179 21180/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21181#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 21182#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 21183#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 21184#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 21185#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 21186#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U 21187 21188/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21189#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 21190#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 21191#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 21192#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 21193#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 21194#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U 21195 21196/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21197#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 21198#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 21199#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 21200#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 21201#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 21202#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U 21203 21204/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21205#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 21206#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 21207#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 21208#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 21209#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 21210#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U 21211 21212/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21213#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 21214#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 21215#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 21216#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 21217#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 21218#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U 21219 21220/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21221#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 21222#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21223#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 21224#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 21225#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 21226#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U 21227 21228/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21229#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 21230#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 21231#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 21232#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 21233#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 21234#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U 21235 21236/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21237#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 21238#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 21239#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 21240#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 21241#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 21242#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U 21243 21244/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21245#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 21246#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 21247#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 21248#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 21249#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 21250#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U 21251 21252/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21253#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 21254#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 21255#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 21256#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 21257#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 21258#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U 21259 21260/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21261#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 21262#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 21263#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 21264#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 21265#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 21266#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U 21267 21268/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21269#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 21270#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 21271#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 21272#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 21273#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 21274#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U 21275 21276/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21277#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 21278#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 21279#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 21280#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 21281#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 21282#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U 21283 21284/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21285#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 21286#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 21287#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 21288#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 21289#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 21290#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U 21291 21292/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21293#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 21294#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 21295#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 21296#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 21297#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 21298#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U 21299 21300/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21301#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 21302#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 21303#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 21304#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 21305#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 21306#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U 21307 21308/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21309#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 21310#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 21311#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 21312#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 21313#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 21314#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U 21315 21316/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21317#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 21318#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 21319#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 21320#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 21321#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 21322#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U 21323 21324/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21325#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 21326#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 21327#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 21328#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 21329#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 21330#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U 21331 21332/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21333#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 21334#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 21335#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 21336#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 21337#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 21338#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U 21339 21340/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21341#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 21342#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 21343#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 21344#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 21345#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 21346#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U 21347 21348/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21349#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 21350#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 21351#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 21352#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 21353#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 21354#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U 21355 21356/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21357#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 21358#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 21359#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 21360#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 21361#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 21362#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U 21363 21364/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21365#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 21366#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 21367#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 21368#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 21369#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 21370#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U 21371 21372/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21373#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 21374#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 21375#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 21376#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 21377#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 21378#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U 21379 21380/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21381#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 21382#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 21383#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 21384#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 21385#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 21386#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U 21387 21388/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21389#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 21390#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 21391#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 21392#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 21393#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 21394#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U 21395 21396/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21397#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 21398#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 21399#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 21400#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 21401#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 21402#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U 21403 21404/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21405#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 21406#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 21407#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 21408#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 21409#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 21410#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U 21411 21412/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21413#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 21414#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 21415#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 21416#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 21417#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 21418#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U 21419 21420/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21421#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 21422#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 21423#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 21424#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 21425#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 21426#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U 21427 21428/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21429#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 21430#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21431#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 21432#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 21433#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 21434#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U 21435 21436/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21437#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 21438#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 21439#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 21440#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 21441#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 21442#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U 21443 21444/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21445#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 21446#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 21447#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 21448#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 21449#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 21450#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U 21451 21452/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21453#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 21454#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 21455#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 21456#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 21457#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 21458#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U 21459 21460/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21461#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 21462#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 21463#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 21464#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 21465#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 21466#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U 21467 21468/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21469#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 21470#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 21471#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 21472#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 21473#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 21474#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U 21475 21476/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21477#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 21478#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 21479#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 21480#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 21481#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 21482#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U 21483 21484/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21485#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 21486#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 21487#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 21488#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 21489#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 21490#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U 21491 21492/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21493#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 21494#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 21495#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 21496#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 21497#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 21498#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U 21499 21500/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21501#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 21502#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 21503#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 21504#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 21505#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 21506#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U 21507 21508/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21509#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 21510#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 21511#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 21512#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 21513#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 21514#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U 21515 21516/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21517#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 21518#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 21519#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 21520#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 21521#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 21522#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U 21523 21524/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21525#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 21526#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 21527#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 21528#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 21529#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 21530#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U 21531 21532/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21533#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 21534#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 21535#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 21536#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 21537#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 21538#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U 21539 21540/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21541#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 21542#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 21543#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 21544#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 21545#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 21546#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U 21547 21548/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21549#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 21550#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 21551#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 21552#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 21553#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 21554#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U 21555 21556/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21557#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 21558#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 21559#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 21560#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 21561#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 21562#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U 21563 21564/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21565#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 21566#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 21567#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 21568#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 21569#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 21570#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U 21571 21572/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21573#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 21574#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 21575#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 21576#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 21577#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 21578#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U 21579 21580/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21581#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 21582#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 21583#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 21584#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 21585#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 21586#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U 21587 21588/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21589#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 21590#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 21591#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 21592#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 21593#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 21594#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U 21595 21596/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21597#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 21598#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 21599#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 21600#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 21601#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 21602#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U 21603 21604/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21605#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 21606#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 21607#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 21608#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 21609#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 21610#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U 21611 21612/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21613#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 21614#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 21615#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 21616#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 21617#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 21618#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U 21619 21620/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21621#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 21622#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 21623#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 21624#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 21625#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 21626#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U 21627 21628/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21629#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 21630#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 21631#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 21632#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 21633#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 21634#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U 21635 21636/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21637#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 21638#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21639#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 21640#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 21641#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 21642#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U 21643 21644/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21645#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 21646#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 21647#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 21648#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 21649#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 21650#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U 21651 21652/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21653#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 21654#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 21655#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 21656#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 21657#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 21658#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U 21659 21660/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21661#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 21662#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 21663#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 21664#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 21665#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 21666#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U 21667 21668/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21669#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 21670#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 21671#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 21672#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 21673#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 21674#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U 21675 21676/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21677#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 21678#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 21679#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 21680#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 21681#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 21682#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U 21683 21684/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21685#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 21686#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 21687#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 21688#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 21689#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 21690#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U 21691 21692/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21693#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 21694#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 21695#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 21696#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 21697#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 21698#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U 21699 21700/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21701#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 21702#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 21703#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 21704#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 21705#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 21706#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U 21707 21708/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21709#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 21710#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 21711#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 21712#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 21713#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 21714#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U 21715 21716/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21717#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 21718#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 21719#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 21720#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 21721#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 21722#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U 21723 21724/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21725#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 21726#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 21727#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 21728#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 21729#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 21730#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U 21731 21732/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21733#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 21734#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 21735#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 21736#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 21737#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 21738#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U 21739 21740/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21741#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 21742#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 21743#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 21744#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 21745#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 21746#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U 21747 21748/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21749#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 21750#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 21751#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 21752#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 21753#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 21754#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U 21755 21756/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21757#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 21758#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 21759#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 21760#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 21761#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 21762#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U 21763 21764/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21765#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 21766#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 21767#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 21768#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 21769#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 21770#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U 21771 21772/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21773#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 21774#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 21775#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 21776#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 21777#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 21778#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U 21779 21780/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21781#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 21782#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 21783#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 21784#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 21785#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 21786#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U 21787 21788/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21789#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 21790#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 21791#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 21792#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 21793#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 21794#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U 21795 21796/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21797#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 21798#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 21799#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 21800#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 21801#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 21802#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U 21803 21804/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21805#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 21806#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 21807#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 21808#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 21809#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 21810#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U 21811 21812/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21813#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 21814#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 21815#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 21816#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 21817#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 21818#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U 21819 21820/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21821#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 21822#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 21823#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 21824#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 21825#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 21826#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U 21827 21828/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21829#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 21830#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 21831#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 21832#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 21833#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 21834#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U 21835 21836/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21837#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 21838#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 21839#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 21840#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 21841#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 21842#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U 21843 21844/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21845#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 21846#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21847#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 21848#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 21849#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 21850#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U 21851 21852/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21853#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 21854#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 21855#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 21856#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 21857#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 21858#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U 21859 21860/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21861#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 21862#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 21863#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 21864#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 21865#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 21866#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U 21867 21868/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21869#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 21870#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 21871#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 21872#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 21873#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 21874#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U 21875 21876/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21877#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 21878#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 21879#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 21880#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 21881#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 21882#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U 21883 21884/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21885#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 21886#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 21887#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 21888#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 21889#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 21890#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U 21891 21892/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21893#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 21894#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 21895#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 21896#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 21897#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 21898#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U 21899 21900/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21901#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 21902#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 21903#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 21904#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 21905#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 21906#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U 21907 21908/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21909#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 21910#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 21911#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 21912#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 21913#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 21914#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U 21915 21916/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21917#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 21918#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 21919#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 21920#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 21921#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 21922#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U 21923 21924/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21925#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 21926#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 21927#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 21928#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 21929#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 21930#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U 21931 21932/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21933#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 21934#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 21935#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 21936#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 21937#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 21938#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U 21939 21940/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21941#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 21942#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 21943#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 21944#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 21945#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 21946#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U 21947 21948/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21949#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 21950#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 21951#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 21952#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 21953#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 21954#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U 21955 21956/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21957#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 21958#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21959#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 21960#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 21961#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 21962#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U 21963 21964/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21965#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 21966#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 21967#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 21968#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 21969#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 21970#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U 21971 21972/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21973#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 21974#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 21975#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 21976#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 21977#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 21978#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U 21979 21980/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21981#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 21982#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 21983#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 21984#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 21985#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 21986#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U 21987 21988/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21989#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 21990#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 21991#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 21992#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 21993#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 21994#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U 21995 21996/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 21997#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 21998#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 21999#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 22000#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22001#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 22002#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U 22003 22004/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22005#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 22006#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 22007#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 22008#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 22009#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 22010#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U 22011 22012/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22013#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 22014#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 22015#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 22016#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 22017#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 22018#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U 22019 22020/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22021#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 22022#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 22023#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 22024#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 22025#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 22026#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U 22027 22028/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22029#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 22030#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 22031#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 22032#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 22033#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 22034#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U 22035 22036/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22037#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 22038#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 22039#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 22040#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 22041#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 22042#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U 22043 22044/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22045#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 22046#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 22047#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 22048#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 22049#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 22050#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U 22051 22052/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22053#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 22054#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 22055#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 22056#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 22057#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 22058#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U 22059 22060/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22061#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 22062#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22063#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 22064#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 22065#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 22066#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U 22067 22068/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22069#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 22070#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 22071#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 22072#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 22073#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 22074#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U 22075 22076/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22077#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 22078#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 22079#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 22080#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 22081#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 22082#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U 22083 22084/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22085#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 22086#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 22087#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 22088#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 22089#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 22090#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U 22091 22092/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22093#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 22094#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 22095#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 22096#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 22097#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 22098#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U 22099 22100/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22101#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 22102#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 22103#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 22104#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 22105#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 22106#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U 22107 22108/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22109#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 22110#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 22111#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 22112#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 22113#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 22114#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U 22115 22116/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22117#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 22118#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 22119#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 22120#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 22121#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 22122#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U 22123 22124/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22125#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 22126#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 22127#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 22128#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 22129#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 22130#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U 22131 22132/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22133#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 22134#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 22135#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 22136#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 22137#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 22138#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U 22139 22140/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22141#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 22142#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 22143#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 22144#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 22145#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 22146#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U 22147 22148/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22149#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 22150#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 22151#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 22152#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 22153#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 22154#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U 22155 22156/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22157#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 22158#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 22159#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 22160#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 22161#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 22162#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U 22163 22164/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22165#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 22166#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 22167#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 22168#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 22169#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 22170#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U 22171 22172/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22173#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 22174#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 22175#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 22176#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 22177#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 22178#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U 22179 22180/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22181#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 22182#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 22183#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 22184#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 22185#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 22186#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U 22187 22188/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22189#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 22190#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 22191#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 22192#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 22193#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 22194#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U 22195 22196/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22197#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 22198#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 22199#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 22200#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 22201#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 22202#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U 22203 22204/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22205#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 22206#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 22207#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 22208#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 22209#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 22210#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U 22211 22212/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22213#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 22214#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 22215#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 22216#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 22217#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 22218#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U 22219 22220/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22221#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 22222#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 22223#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 22224#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 22225#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 22226#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U 22227 22228/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22229#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 22230#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 22231#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 22232#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 22233#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 22234#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U 22235 22236/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22237#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 22238#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 22239#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 22240#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 22241#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 22242#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U 22243 22244/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22245#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 22246#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 22247#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 22248#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 22249#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 22250#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U 22251 22252/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22253#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 22254#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 22255#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 22256#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 22257#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 22258#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U 22259 22260/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22261#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 22262#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 22263#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 22264#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 22265#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 22266#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U 22267 22268/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22269#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 22270#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22271#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 22272#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 22273#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 22274#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U 22275 22276/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22277#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 22278#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 22279#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 22280#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 22281#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 22282#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U 22283 22284/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22285#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 22286#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 22287#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 22288#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 22289#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 22290#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U 22291 22292/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ 22293#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 22294#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 22295#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 22296#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 22297#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 22298#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U 22299 22300/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22301#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 22302#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 22303#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 22304#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 22305#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 22306#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U 22307 22308/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22309#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 22310#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 22311#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 22312#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 22313#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 22314#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U 22315 22316/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22317#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 22318#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 22319#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 22320#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 22321#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 22322#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U 22323 22324/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22325#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 22326#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 22327#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 22328#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 22329#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 22330#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U 22331 22332/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22333#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 22334#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 22335#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 22336#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 22337#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 22338#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U 22339 22340/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22341#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 22342#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 22343#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 22344#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 22345#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 22346#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U 22347 22348/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22349#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 22350#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 22351#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 22352#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 22353#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 22354#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U 22355 22356/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22357#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 22358#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 22359#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 22360#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 22361#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 22362#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U 22363 22364/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22365#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 22366#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 22367#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 22368#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 22369#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 22370#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U 22371 22372/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22373#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 22374#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 22375#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 22376#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 22377#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 22378#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U 22379 22380/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22381#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 22382#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 22383#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 22384#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 22385#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 22386#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U 22387 22388/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22389#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 22390#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 22391#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 22392#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 22393#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 22394#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U 22395 22396/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22397#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 22398#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 22399#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 22400#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 22401#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 22402#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U 22403 22404/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22405#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 22406#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 22407#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 22408#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 22409#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 22410#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U 22411 22412/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22413#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 22414#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 22415#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 22416#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 22417#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 22418#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U 22419 22420/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22421#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 22422#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 22423#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 22424#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 22425#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 22426#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U 22427 22428/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22429#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 22430#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 22431#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 22432#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 22433#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 22434#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U 22435 22436/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22437#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 22438#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 22439#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 22440#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 22441#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 22442#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U 22443 22444/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22445#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 22446#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 22447#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 22448#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 22449#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 22450#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U 22451 22452/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22453#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 22454#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 22455#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 22456#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 22457#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 22458#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U 22459 22460/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22461#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 22462#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 22463#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 22464#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 22465#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 22466#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U 22467 22468/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22469#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 22470#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 22471#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 22472#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 22473#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 22474#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U 22475 22476/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22477#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 22478#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22479#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 22480#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 22481#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 22482#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U 22483 22484/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22485#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 22486#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 22487#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 22488#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 22489#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 22490#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U 22491 22492/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22493#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 22494#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 22495#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 22496#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 22497#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 22498#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U 22499 22500/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22501#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 22502#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 22503#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 22504#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 22505#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 22506#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U 22507 22508/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22509#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 22510#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 22511#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 22512#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 22513#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 22514#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U 22515 22516/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22517#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 22518#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 22519#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 22520#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 22521#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 22522#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U 22523 22524/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22525#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 22526#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 22527#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 22528#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 22529#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 22530#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U 22531 22532/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22533#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 22534#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 22535#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 22536#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 22537#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 22538#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U 22539 22540/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22541#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 22542#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 22543#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 22544#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 22545#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 22546#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U 22547 22548/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22549#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 22550#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 22551#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 22552#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 22553#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 22554#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U 22555 22556/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22557#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 22558#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 22559#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 22560#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 22561#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 22562#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U 22563 22564/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22565#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 22566#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 22567#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 22568#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 22569#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 22570#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U 22571 22572/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22573#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 22574#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 22575#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 22576#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 22577#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 22578#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U 22579 22580/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22581#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 22582#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 22583#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 22584#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 22585#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 22586#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U 22587 22588/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22589#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 22590#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 22591#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 22592#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 22593#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 22594#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U 22595 22596/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22597#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 22598#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 22599#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 22600#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 22601#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 22602#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U 22603 22604/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22605#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 22606#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 22607#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 22608#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 22609#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 22610#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U 22611 22612/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22613#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 22614#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 22615#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 22616#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 22617#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 22618#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U 22619 22620/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22621#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 22622#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 22623#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 22624#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 22625#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 22626#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U 22627 22628/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22629#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 22630#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 22631#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 22632#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 22633#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 22634#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U 22635 22636/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22637#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 22638#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 22639#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 22640#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 22641#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 22642#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U 22643 22644/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22645#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 22646#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 22647#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 22648#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 22649#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 22650#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U 22651 22652/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22653#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 22654#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 22655#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 22656#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 22657#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 22658#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U 22659 22660/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22661#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 22662#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 22663#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 22664#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 22665#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 22666#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U 22667 22668/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22669#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 22670#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 22671#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 22672#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 22673#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 22674#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U 22675 22676/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22677#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 22678#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 22679#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 22680#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 22681#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 22682#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U 22683 22684/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22685#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 22686#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22687#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 22688#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 22689#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 22690#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U 22691 22692/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22693#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 22694#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 22695#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 22696#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 22697#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 22698#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U 22699 22700/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22701#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 22702#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 22703#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 22704#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 22705#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 22706#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U 22707 22708/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22709#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 22710#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 22711#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 22712#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 22713#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 22714#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U 22715 22716/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22717#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 22718#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 22719#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 22720#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 22721#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 22722#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U 22723 22724/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22725#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 22726#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 22727#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 22728#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 22729#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 22730#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U 22731 22732/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22733#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 22734#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 22735#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 22736#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 22737#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 22738#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U 22739 22740/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22741#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 22742#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 22743#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 22744#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 22745#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 22746#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U 22747 22748/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22749#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 22750#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 22751#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 22752#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 22753#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 22754#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U 22755 22756/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22757#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 22758#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 22759#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 22760#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 22761#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 22762#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U 22763 22764/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22765#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 22766#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 22767#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 22768#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 22769#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 22770#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U 22771 22772/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22773#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 22774#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 22775#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 22776#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 22777#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 22778#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U 22779 22780/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22781#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 22782#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 22783#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 22784#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 22785#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 22786#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U 22787 22788/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22789#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 22790#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 22791#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 22792#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 22793#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 22794#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U 22795 22796/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22797#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 22798#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 22799#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 22800#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 22801#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 22802#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U 22803 22804/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22805#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 22806#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 22807#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 22808#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 22809#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 22810#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U 22811 22812/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22813#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 22814#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 22815#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 22816#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 22817#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 22818#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U 22819 22820/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22821#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 22822#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 22823#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 22824#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 22825#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 22826#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U 22827 22828/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22829#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 22830#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 22831#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 22832#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 22833#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 22834#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U 22835 22836/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22837#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 22838#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 22839#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 22840#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 22841#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 22842#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U 22843 22844/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22845#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 22846#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 22847#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 22848#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 22849#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 22850#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U 22851 22852/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22853#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 22854#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 22855#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 22856#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 22857#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 22858#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U 22859 22860/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22861#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 22862#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 22863#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 22864#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 22865#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 22866#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U 22867 22868/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22869#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 22870#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 22871#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 22872#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 22873#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 22874#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U 22875 22876/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22877#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 22878#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 22879#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 22880#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 22881#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 22882#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U 22883 22884/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22885#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 22886#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 22887#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 22888#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 22889#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 22890#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U 22891 22892/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22893#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 22894#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22895#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 22896#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 22897#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 22898#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U 22899 22900/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22901#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 22902#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 22903#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 22904#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 22905#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 22906#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U 22907 22908/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22909#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 22910#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 22911#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 22912#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 22913#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 22914#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U 22915 22916/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22917#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 22918#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 22919#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 22920#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 22921#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 22922#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U 22923 22924/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22925#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 22926#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 22927#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 22928#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 22929#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 22930#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U 22931 22932/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22933#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 22934#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 22935#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 22936#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 22937#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 22938#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U 22939 22940/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22941#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 22942#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 22943#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 22944#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 22945#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 22946#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U 22947 22948/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22949#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 22950#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 22951#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 22952#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 22953#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 22954#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U 22955 22956/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22957#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 22958#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 22959#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 22960#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 22961#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 22962#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U 22963 22964/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22965#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 22966#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 22967#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 22968#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 22969#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 22970#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U 22971 22972/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22973#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 22974#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 22975#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 22976#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 22977#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 22978#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U 22979 22980/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22981#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 22982#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 22983#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 22984#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 22985#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 22986#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U 22987 22988/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22989#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 22990#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 22991#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 22992#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 22993#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 22994#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U 22995 22996/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 22997#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 22998#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 22999#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 23000#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23001#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 23002#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U 23003 23004/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23005#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 23006#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 23007#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 23008#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 23009#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 23010#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U 23011 23012/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23013#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 23014#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 23015#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 23016#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 23017#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 23018#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U 23019 23020/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23021#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 23022#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 23023#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 23024#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 23025#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 23026#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U 23027 23028/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23029#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 23030#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 23031#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 23032#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 23033#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 23034#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U 23035 23036/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23037#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 23038#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 23039#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 23040#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 23041#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 23042#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U 23043 23044/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23045#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 23046#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 23047#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 23048#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 23049#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 23050#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U 23051 23052/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23053#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 23054#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 23055#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 23056#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 23057#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 23058#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U 23059 23060/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23061#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 23062#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 23063#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 23064#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 23065#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 23066#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U 23067 23068/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23069#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 23070#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 23071#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 23072#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 23073#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 23074#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U 23075 23076/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23077#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 23078#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 23079#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 23080#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 23081#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 23082#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U 23083 23084/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23085#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 23086#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 23087#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 23088#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 23089#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 23090#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U 23091 23092/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23093#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 23094#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 23095#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 23096#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 23097#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 23098#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U 23099 23100/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23101#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 23102#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 23103#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 23104#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 23105#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 23106#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U 23107 23108/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23109#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 23110#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23111#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 23112#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 23113#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 23114#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U 23115 23116/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23117#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 23118#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 23119#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 23120#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 23121#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 23122#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U 23123 23124/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23125#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 23126#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 23127#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 23128#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 23129#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 23130#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U 23131 23132/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23133#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 23134#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 23135#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 23136#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 23137#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 23138#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U 23139 23140/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23141#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 23142#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 23143#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 23144#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 23145#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 23146#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U 23147 23148/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23149#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 23150#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 23151#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 23152#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 23153#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 23154#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U 23155 23156/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23157#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 23158#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 23159#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 23160#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 23161#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 23162#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U 23163 23164/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23165#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 23166#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 23167#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 23168#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 23169#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 23170#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U 23171 23172/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23173#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 23174#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 23175#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 23176#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 23177#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 23178#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U 23179 23180/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23181#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 23182#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 23183#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 23184#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 23185#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 23186#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U 23187 23188/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23189#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 23190#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 23191#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 23192#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 23193#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 23194#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U 23195 23196/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23197#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 23198#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 23199#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 23200#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 23201#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 23202#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U 23203 23204/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23205#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 23206#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 23207#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 23208#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 23209#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 23210#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U 23211 23212/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23213#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 23214#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 23215#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 23216#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 23217#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 23218#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U 23219 23220/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23221#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 23222#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23223#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 23224#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 23225#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 23226#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U 23227 23228/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23229#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 23230#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 23231#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 23232#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 23233#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 23234#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U 23235 23236/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23237#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 23238#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 23239#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 23240#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 23241#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 23242#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U 23243 23244/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23245#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 23246#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 23247#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 23248#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 23249#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 23250#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U 23251 23252/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23253#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 23254#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 23255#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 23256#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 23257#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 23258#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U 23259 23260/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23261#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 23262#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 23263#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 23264#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 23265#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 23266#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U 23267 23268/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23269#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 23270#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 23271#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 23272#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 23273#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 23274#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U 23275 23276/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23277#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 23278#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 23279#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 23280#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 23281#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 23282#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U 23283 23284/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23285#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 23286#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 23287#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 23288#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 23289#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 23290#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U 23291 23292/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23293#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 23294#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 23295#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 23296#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 23297#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 23298#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U 23299 23300/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23301#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 23302#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 23303#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 23304#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 23305#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 23306#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U 23307 23308/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23309#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 23310#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 23311#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 23312#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 23313#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 23314#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U 23315 23316/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23317#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 23318#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23319#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 23320#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 23321#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 23322#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U 23323 23324/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23325#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 23326#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 23327#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 23328#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 23329#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 23330#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U 23331 23332/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23333#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 23334#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 23335#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 23336#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 23337#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 23338#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U 23339 23340/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23341#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 23342#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 23343#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 23344#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 23345#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 23346#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U 23347 23348/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23349#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 23350#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 23351#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 23352#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 23353#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 23354#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U 23355 23356/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23357#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 23358#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 23359#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 23360#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 23361#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 23362#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U 23363 23364/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23365#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 23366#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 23367#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 23368#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 23369#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 23370#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U 23371 23372/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23373#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 23374#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 23375#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 23376#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 23377#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 23378#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U 23379 23380/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23381#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 23382#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 23383#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 23384#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 23385#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 23386#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U 23387 23388/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23389#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 23390#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 23391#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 23392#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 23393#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 23394#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U 23395 23396/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23397#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 23398#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 23399#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 23400#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 23401#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 23402#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U 23403 23404/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23405#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 23406#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 23407#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 23408#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 23409#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 23410#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U 23411 23412/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23413#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 23414#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 23415#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 23416#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 23417#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 23418#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U 23419 23420/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23421#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 23422#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 23423#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 23424#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 23425#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 23426#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U 23427 23428/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23429#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 23430#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 23431#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 23432#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 23433#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 23434#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U 23435 23436/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23437#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 23438#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 23439#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 23440#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 23441#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 23442#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U 23443 23444/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23445#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 23446#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 23447#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 23448#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 23449#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 23450#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U 23451 23452/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23453#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 23454#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 23455#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 23456#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 23457#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 23458#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U 23459 23460/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23461#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 23462#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 23463#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 23464#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 23465#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 23466#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U 23467 23468/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23469#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 23470#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 23471#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 23472#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 23473#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 23474#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U 23475 23476/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23477#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 23478#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 23479#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 23480#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 23481#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 23482#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U 23483 23484/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23485#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 23486#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 23487#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 23488#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 23489#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 23490#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U 23491 23492/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23493#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 23494#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 23495#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 23496#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 23497#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 23498#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U 23499 23500/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23501#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 23502#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 23503#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 23504#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 23505#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 23506#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U 23507 23508/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23509#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 23510#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 23511#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 23512#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 23513#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 23514#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U 23515 23516/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23517#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 23518#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 23519#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 23520#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 23521#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 23522#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U 23523 23524/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23525#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 23526#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23527#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 23528#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 23529#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 23530#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U 23531 23532/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23533#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 23534#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 23535#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 23536#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 23537#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 23538#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U 23539 23540/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ 23541#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 23542#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 23543#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 23544#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 23545#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 23546#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U 23547 23548/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23549#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 23550#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 23551#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 23552#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 23553#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 23554#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U 23555 23556/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23557#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 23558#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 23559#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 23560#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 23561#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 23562#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U 23563 23564/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23565#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 23566#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 23567#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 23568#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 23569#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 23570#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U 23571 23572/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23573#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 23574#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 23575#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 23576#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 23577#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 23578#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U 23579 23580/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23581#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 23582#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 23583#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 23584#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 23585#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 23586#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U 23587 23588/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23589#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 23590#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 23591#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 23592#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 23593#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 23594#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U 23595 23596/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23597#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 23598#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 23599#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 23600#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 23601#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 23602#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U 23603 23604/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23605#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 23606#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 23607#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 23608#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 23609#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 23610#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U 23611 23612/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23613#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 23614#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 23615#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 23616#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 23617#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 23618#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U 23619 23620/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23621#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 23622#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 23623#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 23624#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 23625#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 23626#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U 23627 23628/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23629#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 23630#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 23631#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 23632#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 23633#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 23634#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U 23635 23636/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23637#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 23638#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 23639#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 23640#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 23641#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 23642#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U 23643 23644/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23645#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 23646#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 23647#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 23648#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 23649#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 23650#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U 23651 23652/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23653#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 23654#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 23655#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 23656#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 23657#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 23658#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U 23659 23660/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23661#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 23662#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 23663#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 23664#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 23665#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 23666#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U 23667 23668/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23669#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 23670#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 23671#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 23672#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 23673#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 23674#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U 23675 23676/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23677#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 23678#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 23679#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 23680#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 23681#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 23682#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U 23683 23684/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23685#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 23686#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 23687#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 23688#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 23689#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 23690#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U 23691 23692/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23693#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 23694#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 23695#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 23696#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 23697#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 23698#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U 23699 23700/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23701#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 23702#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 23703#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 23704#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 23705#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 23706#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U 23707 23708/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23709#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 23710#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 23711#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 23712#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 23713#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 23714#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U 23715 23716/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23717#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 23718#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 23719#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 23720#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 23721#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 23722#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U 23723 23724/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23725#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 23726#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 23727#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 23728#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 23729#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 23730#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U 23731 23732/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23733#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 23734#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23735#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 23736#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 23737#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 23738#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U 23739 23740/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23741#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 23742#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 23743#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 23744#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 23745#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 23746#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U 23747 23748/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23749#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 23750#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 23751#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 23752#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 23753#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 23754#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U 23755 23756/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23757#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 23758#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 23759#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 23760#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 23761#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 23762#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U 23763 23764/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23765#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 23766#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 23767#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 23768#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 23769#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 23770#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U 23771 23772/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23773#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 23774#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 23775#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 23776#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 23777#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 23778#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U 23779 23780/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23781#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 23782#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 23783#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 23784#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 23785#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 23786#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U 23787 23788/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23789#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 23790#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 23791#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 23792#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 23793#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 23794#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U 23795 23796/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23797#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 23798#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 23799#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 23800#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 23801#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 23802#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U 23803 23804/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23805#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 23806#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 23807#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 23808#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 23809#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 23810#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U 23811 23812/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23813#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 23814#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 23815#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 23816#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 23817#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 23818#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U 23819 23820/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23821#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 23822#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 23823#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 23824#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 23825#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 23826#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U 23827 23828/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23829#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 23830#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 23831#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 23832#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 23833#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 23834#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U 23835 23836/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23837#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 23838#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 23839#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 23840#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 23841#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 23842#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U 23843 23844/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23845#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 23846#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 23847#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 23848#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 23849#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 23850#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U 23851 23852/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23853#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 23854#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 23855#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 23856#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 23857#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 23858#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U 23859 23860/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23861#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 23862#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 23863#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 23864#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 23865#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 23866#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U 23867 23868/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23869#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 23870#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 23871#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 23872#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 23873#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 23874#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U 23875 23876/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23877#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 23878#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 23879#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 23880#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 23881#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 23882#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U 23883 23884/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23885#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 23886#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 23887#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 23888#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 23889#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 23890#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U 23891 23892/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23893#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 23894#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 23895#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 23896#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 23897#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 23898#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U 23899 23900/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23901#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 23902#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 23903#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 23904#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 23905#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 23906#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U 23907 23908/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23909#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 23910#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 23911#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 23912#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 23913#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 23914#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U 23915 23916/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23917#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 23918#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 23919#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 23920#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 23921#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 23922#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U 23923 23924/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23925#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 23926#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 23927#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 23928#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 23929#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 23930#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U 23931 23932/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23933#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 23934#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 23935#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 23936#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 23937#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 23938#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U 23939 23940/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23941#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 23942#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23943#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 23944#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 23945#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 23946#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U 23947 23948/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23949#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 23950#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 23951#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 23952#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 23953#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 23954#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U 23955 23956/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23957#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 23958#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 23959#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 23960#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 23961#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 23962#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U 23963 23964/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23965#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 23966#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 23967#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 23968#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 23969#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 23970#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U 23971 23972/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23973#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 23974#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 23975#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 23976#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 23977#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 23978#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U 23979 23980/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23981#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 23982#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 23983#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 23984#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 23985#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 23986#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U 23987 23988/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23989#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 23990#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 23991#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 23992#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 23993#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 23994#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U 23995 23996/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 23997#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 23998#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 23999#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 24000#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
24001#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 24002#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U 24003 24004/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24005#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 24006#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 24007#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 24008#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 24009#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 24010#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U 24011 24012/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24013#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 24014#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 24015#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 24016#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 24017#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 24018#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U 24019 24020/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24021#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 24022#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 24023#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 24024#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 24025#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 24026#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U 24027 24028/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24029#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 24030#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 24031#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 24032#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 24033#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 24034#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U 24035 24036/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24037#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 24038#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 24039#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 24040#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 24041#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 24042#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U 24043 24044/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24045#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 24046#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 24047#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 24048#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 24049#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 24050#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U 24051 24052/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24053#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 24054#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 24055#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 24056#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 24057#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 24058#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U 24059 24060/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24061#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 24062#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 24063#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 24064#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 24065#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 24066#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U 24067 24068/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24069#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 24070#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 24071#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 24072#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 24073#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 24074#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U 24075 24076/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24077#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 24078#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 24079#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 24080#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 24081#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 24082#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U 24083 24084/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24085#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 24086#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 24087#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 24088#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 24089#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 24090#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U 24091 24092/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24093#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 24094#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 24095#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 24096#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 24097#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 24098#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U 24099 24100/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24101#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 24102#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 24103#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 24104#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 24105#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 24106#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U 24107 24108/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24109#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 24110#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 24111#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 24112#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 24113#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 24114#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U 24115 24116/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24117#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 24118#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 24119#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 24120#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 24121#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 24122#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U 24123 24124/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24125#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 24126#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 24127#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 24128#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 24129#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 24130#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U 24131 24132/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24133#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 24134#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 24135#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 24136#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 24137#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 24138#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U 24139 24140/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24141#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 24142#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 24143#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 24144#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 24145#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 24146#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U 24147 24148/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24149#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 24150#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 24151#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 24152#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 24153#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 24154#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U 24155 24156/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24157#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 24158#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24159#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 24160#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 24161#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 24162#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U 24163 24164/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24165#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 24166#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 24167#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 24168#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 24169#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 24170#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U 24171 24172/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24173#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 24174#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 24175#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 24176#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 24177#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 24178#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U 24179 24180/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24181#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 24182#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 24183#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 24184#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 24185#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 24186#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U 24187 24188/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24189#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 24190#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 24191#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 24192#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 24193#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 24194#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U 24195 24196/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24197#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 24198#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 24199#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 24200#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 24201#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 24202#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U 24203 24204/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24205#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 24206#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 24207#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 24208#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 24209#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 24210#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U 24211 24212/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24213#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 24214#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 24215#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 24216#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 24217#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 24218#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U 24219 24220/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24221#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 24222#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 24223#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 24224#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 24225#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 24226#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U 24227 24228/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24229#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 24230#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 24231#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 24232#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 24233#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 24234#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U 24235 24236/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24237#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 24238#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 24239#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 24240#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 24241#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 24242#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U 24243 24244/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24245#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 24246#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 24247#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 24248#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 24249#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 24250#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U 24251 24252/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24253#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 24254#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 24255#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 24256#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 24257#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 24258#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U 24259 24260/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24261#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 24262#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 24263#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 24264#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 24265#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 24266#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U 24267 24268/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24269#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 24270#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 24271#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 24272#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 24273#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 24274#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U 24275 24276/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24277#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 24278#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 24279#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 24280#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 24281#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 24282#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U 24283 24284/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24285#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 24286#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 24287#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 24288#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 24289#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 24290#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U 24291 24292/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24293#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 24294#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 24295#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 24296#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 24297#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 24298#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U 24299 24300/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24301#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 24302#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 24303#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 24304#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 24305#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 24306#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U 24307 24308/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24309#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 24310#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 24311#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 24312#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 24313#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 24314#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U 24315 24316/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24317#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 24318#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 24319#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 24320#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 24321#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 24322#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U 24323 24324/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24325#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 24326#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 24327#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 24328#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 24329#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 24330#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U 24331 24332/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24333#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 24334#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 24335#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 24336#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 24337#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 24338#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U 24339 24340/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24341#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 24342#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 24343#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 24344#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 24345#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 24346#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U 24347 24348/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24349#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 24350#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 24351#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 24352#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 24353#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 24354#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U 24355 24356/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24357#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 24358#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 24359#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 24360#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 24361#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 24362#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U 24363 24364/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24365#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 24366#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24367#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 24368#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 24369#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 24370#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U 24371 24372/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24373#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 24374#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 24375#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 24376#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 24377#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 24378#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U 24379 24380/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24381#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 24382#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 24383#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 24384#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 24385#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 24386#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U 24387 24388/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24389#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 24390#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 24391#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 24392#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 24393#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 24394#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U 24395 24396/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24397#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 24398#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 24399#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 24400#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 24401#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 24402#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U 24403 24404/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24405#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 24406#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 24407#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 24408#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 24409#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 24410#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U 24411 24412/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24413#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 24414#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 24415#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 24416#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 24417#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 24418#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U 24419 24420/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24421#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 24422#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 24423#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 24424#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 24425#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 24426#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U 24427 24428/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24429#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 24430#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 24431#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 24432#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 24433#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 24434#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U 24435 24436/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24437#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 24438#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 24439#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 24440#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 24441#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 24442#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U 24443 24444/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24445#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 24446#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 24447#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 24448#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 24449#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 24450#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U 24451 24452/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24453#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 24454#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 24455#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 24456#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 24457#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 24458#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U 24459 24460/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24461#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 24462#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 24463#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 24464#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 24465#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 24466#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U 24467 24468/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24469#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 24470#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 24471#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 24472#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 24473#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 24474#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U 24475 24476/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24477#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 24478#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24479#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 24480#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 24481#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 24482#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U 24483 24484/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24485#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 24486#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 24487#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 24488#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 24489#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 24490#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U 24491 24492/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24493#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 24494#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 24495#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 24496#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 24497#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 24498#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U 24499 24500/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24501#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 24502#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 24503#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 24504#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 24505#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 24506#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U 24507 24508/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24509#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 24510#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 24511#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 24512#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 24513#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 24514#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U 24515 24516/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24517#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 24518#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 24519#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 24520#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 24521#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 24522#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U 24523 24524/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24525#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 24526#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 24527#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 24528#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 24529#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 24530#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U 24531 24532/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24533#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 24534#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 24535#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 24536#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 24537#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 24538#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U 24539 24540/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24541#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 24542#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 24543#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 24544#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 24545#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 24546#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U 24547 24548/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24549#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 24550#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 24551#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 24552#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 24553#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 24554#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U 24555 24556/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24557#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 24558#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 24559#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 24560#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 24561#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 24562#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U 24563 24564/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24565#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 24566#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 24567#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 24568#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 24569#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 24570#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U 24571 24572/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24573#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 24574#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24575#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 24576#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 24577#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 24578#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U 24579 24580/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24581#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 24582#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 24583#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 24584#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 24585#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 24586#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U 24587 24588/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24589#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 24590#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 24591#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 24592#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 24593#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 24594#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U 24595 24596/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24597#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 24598#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 24599#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 24600#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 24601#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 24602#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U 24603 24604/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24605#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 24606#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 24607#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 24608#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 24609#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 24610#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U 24611 24612/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24613#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 24614#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 24615#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 24616#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 24617#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 24618#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U 24619 24620/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24621#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 24622#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 24623#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 24624#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 24625#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 24626#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U 24627 24628/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24629#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 24630#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 24631#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 24632#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 24633#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 24634#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U 24635 24636/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24637#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 24638#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 24639#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 24640#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 24641#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 24642#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U 24643 24644/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24645#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 24646#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 24647#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 24648#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 24649#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 24650#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U 24651 24652/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24653#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 24654#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 24655#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 24656#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 24657#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 24658#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U 24659 24660/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24661#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 24662#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 24663#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 24664#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 24665#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 24666#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U 24667 24668/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24669#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 24670#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 24671#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 24672#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 24673#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 24674#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U 24675 24676/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24677#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 24678#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 24679#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 24680#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 24681#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 24682#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U 24683 24684/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24685#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 24686#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 24687#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 24688#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 24689#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 24690#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U 24691 24692/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24693#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 24694#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 24695#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 24696#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 24697#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 24698#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U 24699 24700/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24701#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 24702#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 24703#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 24704#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 24705#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 24706#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U 24707 24708/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24709#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 24710#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 24711#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 24712#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 24713#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 24714#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U 24715 24716/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24717#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 24718#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 24719#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 24720#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 24721#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 24722#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U 24723 24724/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24725#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 24726#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 24727#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 24728#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 24729#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 24730#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U 24731 24732/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24733#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 24734#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 24735#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 24736#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 24737#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 24738#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U 24739 24740/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24741#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 24742#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 24743#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 24744#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 24745#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 24746#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U 24747 24748/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24749#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 24750#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 24751#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 24752#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 24753#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 24754#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U 24755 24756/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24757#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 24758#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 24759#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 24760#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 24761#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 24762#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U 24763 24764/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24765#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 24766#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 24767#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 24768#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 24769#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 24770#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U 24771 24772/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24773#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 24774#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 24775#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 24776#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 24777#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 24778#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U 24779 24780/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24781#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 24782#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24783#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 24784#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 24785#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 24786#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U 24787 24788/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ 24789#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 24790#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 24791#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 24792#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 24793#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 24794#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U 24795 24796/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp 24797 ts to I2C 0 inputs.*/ 24798#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 24799#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 24800#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 24801#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 24802#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 24803#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U 24804 24805/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R 24806 .*/ 24807#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 24808#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 24809#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 24810#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 24811#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 24812#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U 24813 24814/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 24815 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/ 24816#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 24817#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 24818#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 24819#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 24820#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 24821#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U 24822 24823/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp 24824 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/ 24825#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 24826#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 24827#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 24828#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 24829#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 24830#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U 24831#undef CRL_APB_RST_LPD_IOU0_OFFSET 24832#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 24833#undef CRL_APB_RST_LPD_IOU2_OFFSET 24834#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24835#undef CRL_APB_RST_LPD_TOP_OFFSET 24836#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C 24837#undef CRF_APB_RST_FPD_TOP_OFFSET 24838#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 24839#undef CRL_APB_RST_LPD_IOU2_OFFSET 24840#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24841#undef CRL_APB_RST_LPD_IOU2_OFFSET 24842#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24843#undef CRL_APB_RST_LPD_IOU2_OFFSET 24844#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24845#undef CRL_APB_RST_LPD_IOU2_OFFSET 24846#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24847#undef CRL_APB_RST_LPD_IOU2_OFFSET 24848#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24849#undef CRL_APB_RST_LPD_IOU2_OFFSET 24850#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 24851#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 24852#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034 24853#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 24854#define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018 24855#undef UART0_CONTROL_REG0_OFFSET 24856#define UART0_CONTROL_REG0_OFFSET 0XFF000000 24857#undef UART0_MODE_REG0_OFFSET 24858#define UART0_MODE_REG0_OFFSET 0XFF000004 24859#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 24860#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034 24861#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 24862#define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018 24863#undef UART1_CONTROL_REG0_OFFSET 24864#define UART1_CONTROL_REG0_OFFSET 0XFF010000 24865#undef UART1_MODE_REG0_OFFSET 24866#define UART1_MODE_REG0_OFFSET 0XFF010004 24867#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 24868#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 24869#undef CSU_TAMPER_STATUS_OFFSET 24870#define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000 24871#undef APU_ACE_CTRL_OFFSET 24872#define APU_ACE_CTRL_OFFSET 0XFD5C0060 24873#undef RTC_CONTROL_OFFSET 24874#define RTC_CONTROL_OFFSET 0XFFA60040 24875 24876/*GEM 2 reset*/ 24877#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 24878#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 24879#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 24880#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 0x0000000F 24881#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2 24882#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 0x00000004U 24883 24884/*Block level reset*/ 24885#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL 24886#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 24887#undef CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK 24888#define CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL 0x0017FFFF 24889#define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 16 24890#define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK 0x00010000U 24891 24892/*USB 1 reset for control registers*/ 24893#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL 24894#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 24895#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK 24896#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL 0x00188FDF 24897#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 11 24898#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK 0x00000800U 24899 24900/*USB 1 sleep circuit reset*/ 24901#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL 24902#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 24903#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK 24904#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL 0x00188FDF 24905#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 9 24906#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK 0x00000200U 24907 24908/*USB 1 reset*/ 24909#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL 24910#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 24911#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK 24912#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL 0x00188FDF 24913#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 7 24914#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK 0x00000080U 24915 24916/*PCIE config reset*/ 24917#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 24918#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 24919#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 24920#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE 24921#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 24922#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U 24923 24924/*PCIE control block level reset*/ 24925#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 24926#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 24927#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 24928#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE 24929#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 24930#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U 24931 24932/*PCIE bridge block level reset (AXI interface)*/ 24933#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 24934#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 24935#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 24936#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE 24937#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 24938#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U 24939 24940/*Display Port block level reset (includes DPDMA)*/ 24941#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 24942#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 24943#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 24944#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE 24945#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 24946#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U 24947 24948/*FPD WDT reset*/ 24949#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 24950#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 24951#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 24952#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE 24953#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 24954#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U 24955 24956/*GDMA block level reset*/ 24957#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 24958#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 24959#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 24960#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE 24961#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 24962#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U 24963 24964/*Pixel Processor (submodule of GPU) block level reset*/ 24965#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 24966#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 24967#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 24968#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE 24969#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 24970#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U 24971 24972/*Pixel Processor (submodule of GPU) block level reset*/ 24973#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 24974#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 24975#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 24976#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE 24977#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 24978#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U 24979 24980/*GPU block level reset*/ 24981#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 24982#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 24983#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 24984#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE 24985#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 24986#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U 24987 24988/*GT block level reset*/ 24989#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 24990#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 24991#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK 24992#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE 24993#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 24994#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U 24995 24996/*Block level reset*/ 24997#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL 24998#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 24999#undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK 25000#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL 0x0017FFFF
25001#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 7 25002#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK 0x00000080U 25003 25004/*Block level reset*/ 25005#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 25006#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 25007#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 25008#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF 25009#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 25010#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U 25011 25012/*Block level reset*/ 25013#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 25014#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 25015#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 25016#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF 25017#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 25018#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U 25019 25020/*Block level reset*/ 25021#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 25022#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 25023#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 25024#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF 25025#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 25026#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U 25027 25028/*Block level reset*/ 25029#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL 25030#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 25031#undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK 25032#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL 0x0017FFFF 25033#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 3 25034#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK 0x00000008U 25035 25036/*Block level reset*/ 25037#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL 25038#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 25039#undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK 25040#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL 0x0017FFFF 25041#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 4 25042#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK 0x00000010U 25043 25044/*Block level reset*/ 25045#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 25046#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 25047#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 25048#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF 25049#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 25050#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U 25051 25052/*Block level reset*/ 25053#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 25054#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 25055#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 25056#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF 25057#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 25058#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U 25059 25060/*Block level reset*/ 25061#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 25062#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 25063#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 25064#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF 25065#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 25066#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U 25067 25068/*Block level reset*/ 25069#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 25070#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 25071#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 25072#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF 25073#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 25074#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U 25075 25076/*Block level reset*/ 25077#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 25078#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 25079#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 25080#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF 25081#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 25082#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U 25083 25084/*Block level reset*/ 25085#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 25086#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 25087#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 25088#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF 25089#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 25090#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U 25091 25092/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ 25093#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 25094#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 25095#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 25096#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F 25097#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 25098#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU 25099 25100/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ 25101#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 25102#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 25103#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 25104#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B 25105#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 25106#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU 25107 25108/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a 25109 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ 25110#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 25111#undef UART0_CONTROL_REG0_STPBRK_SHIFT 25112#undef UART0_CONTROL_REG0_STPBRK_MASK 25113#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 25114#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 25115#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U 25116 25117/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the 25118 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ 25119#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 25120#undef UART0_CONTROL_REG0_STTBRK_SHIFT 25121#undef UART0_CONTROL_REG0_STTBRK_MASK 25122#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 25123#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 25124#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U 25125 25126/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co 25127 pleted.*/ 25128#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 25129#undef UART0_CONTROL_REG0_RSTTO_SHIFT 25130#undef UART0_CONTROL_REG0_RSTTO_MASK 25131#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 25132#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 25133#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U 25134 25135/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ 25136#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 25137#undef UART0_CONTROL_REG0_TXDIS_SHIFT 25138#undef UART0_CONTROL_REG0_TXDIS_MASK 25139#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 25140#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 25141#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U 25142 25143/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ 25144#undef UART0_CONTROL_REG0_TXEN_DEFVAL 25145#undef UART0_CONTROL_REG0_TXEN_SHIFT 25146#undef UART0_CONTROL_REG0_TXEN_MASK 25147#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 25148#define UART0_CONTROL_REG0_TXEN_SHIFT 4 25149#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U 25150 25151/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ 25152#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 25153#undef UART0_CONTROL_REG0_RXDIS_SHIFT 25154#undef UART0_CONTROL_REG0_RXDIS_MASK 25155#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 25156#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 25157#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U 25158 25159/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ 25160#undef UART0_CONTROL_REG0_RXEN_DEFVAL 25161#undef UART0_CONTROL_REG0_RXEN_SHIFT 25162#undef UART0_CONTROL_REG0_RXEN_MASK 25163#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 25164#define UART0_CONTROL_REG0_RXEN_SHIFT 2 25165#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U 25166 25167/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi 25168 bit is self clearing once the reset has completed.*/ 25169#undef UART0_CONTROL_REG0_TXRES_DEFVAL 25170#undef UART0_CONTROL_REG0_TXRES_SHIFT 25171#undef UART0_CONTROL_REG0_TXRES_MASK 25172#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 25173#define UART0_CONTROL_REG0_TXRES_SHIFT 1 25174#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U 25175 25176/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit 25177 is self clearing once the reset has completed.*/ 25178#undef UART0_CONTROL_REG0_RXRES_DEFVAL 25179#undef UART0_CONTROL_REG0_RXRES_SHIFT 25180#undef UART0_CONTROL_REG0_RXRES_MASK 25181#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 25182#define UART0_CONTROL_REG0_RXRES_SHIFT 0 25183#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U 25184 25185/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ 25186#undef UART0_MODE_REG0_CHMODE_DEFVAL 25187#undef UART0_MODE_REG0_CHMODE_SHIFT 25188#undef UART0_MODE_REG0_CHMODE_MASK 25189#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 25190#define UART0_MODE_REG0_CHMODE_SHIFT 8 25191#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U 25192 25193/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 25194 stop bits 10: 2 stop bits 11: reserved*/ 25195#undef UART0_MODE_REG0_NBSTOP_DEFVAL 25196#undef UART0_MODE_REG0_NBSTOP_SHIFT 25197#undef UART0_MODE_REG0_NBSTOP_MASK 25198#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 25199#define UART0_MODE_REG0_NBSTOP_SHIFT 6 25200#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U 25201 25202/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 25203 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ 25204#undef UART0_MODE_REG0_PAR_DEFVAL 25205#undef UART0_MODE_REG0_PAR_SHIFT 25206#undef UART0_MODE_REG0_PAR_MASK 25207#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 25208#define UART0_MODE_REG0_PAR_SHIFT 3 25209#define UART0_MODE_REG0_PAR_MASK 0x00000038U 25210 25211/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ 25212#undef UART0_MODE_REG0_CHRL_DEFVAL 25213#undef UART0_MODE_REG0_CHRL_SHIFT 25214#undef UART0_MODE_REG0_CHRL_MASK 25215#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 25216#define UART0_MODE_REG0_CHRL_SHIFT 1 25217#define UART0_MODE_REG0_CHRL_MASK 0x00000006U 25218 25219/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock 25220 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ 25221#undef UART0_MODE_REG0_CLKS_DEFVAL 25222#undef UART0_MODE_REG0_CLKS_SHIFT 25223#undef UART0_MODE_REG0_CLKS_MASK 25224#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 25225#define UART0_MODE_REG0_CLKS_SHIFT 0 25226#define UART0_MODE_REG0_CLKS_MASK 0x00000001U 25227 25228/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ 25229#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 25230#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 25231#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 25232#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F 25233#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 25234#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU 25235 25236/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ 25237#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 25238#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 25239#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 25240#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B 25241#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 25242#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU 25243 25244/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a 25245 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ 25246#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 25247#undef UART1_CONTROL_REG0_STPBRK_SHIFT 25248#undef UART1_CONTROL_REG0_STPBRK_MASK 25249#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 25250#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 25251#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U 25252 25253/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the 25254 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ 25255#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 25256#undef UART1_CONTROL_REG0_STTBRK_SHIFT 25257#undef UART1_CONTROL_REG0_STTBRK_MASK 25258#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 25259#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 25260#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U 25261 25262/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co 25263 pleted.*/ 25264#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 25265#undef UART1_CONTROL_REG0_RSTTO_SHIFT 25266#undef UART1_CONTROL_REG0_RSTTO_MASK 25267#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 25268#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 25269#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U 25270 25271/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ 25272#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 25273#undef UART1_CONTROL_REG0_TXDIS_SHIFT 25274#undef UART1_CONTROL_REG0_TXDIS_MASK 25275#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 25276#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 25277#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U 25278 25279/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ 25280#undef UART1_CONTROL_REG0_TXEN_DEFVAL 25281#undef UART1_CONTROL_REG0_TXEN_SHIFT 25282#undef UART1_CONTROL_REG0_TXEN_MASK 25283#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 25284#define UART1_CONTROL_REG0_TXEN_SHIFT 4 25285#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U 25286 25287/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ 25288#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 25289#undef UART1_CONTROL_REG0_RXDIS_SHIFT 25290#undef UART1_CONTROL_REG0_RXDIS_MASK 25291#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 25292#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 25293#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U 25294 25295/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ 25296#undef UART1_CONTROL_REG0_RXEN_DEFVAL 25297#undef UART1_CONTROL_REG0_RXEN_SHIFT 25298#undef UART1_CONTROL_REG0_RXEN_MASK 25299#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 25300#define UART1_CONTROL_REG0_RXEN_SHIFT 2 25301#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U 25302 25303/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi 25304 bit is self clearing once the reset has completed.*/ 25305#undef UART1_CONTROL_REG0_TXRES_DEFVAL 25306#undef UART1_CONTROL_REG0_TXRES_SHIFT 25307#undef UART1_CONTROL_REG0_TXRES_MASK 25308#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 25309#define UART1_CONTROL_REG0_TXRES_SHIFT 1 25310#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U 25311 25312/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit 25313 is self clearing once the reset has completed.*/ 25314#undef UART1_CONTROL_REG0_RXRES_DEFVAL 25315#undef UART1_CONTROL_REG0_RXRES_SHIFT 25316#undef UART1_CONTROL_REG0_RXRES_MASK 25317#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 25318#define UART1_CONTROL_REG0_RXRES_SHIFT 0 25319#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U 25320 25321/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ 25322#undef UART1_MODE_REG0_CHMODE_DEFVAL 25323#undef UART1_MODE_REG0_CHMODE_SHIFT 25324#undef UART1_MODE_REG0_CHMODE_MASK 25325#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 25326#define UART1_MODE_REG0_CHMODE_SHIFT 8 25327#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U 25328 25329/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 25330 stop bits 10: 2 stop bits 11: reserved*/ 25331#undef UART1_MODE_REG0_NBSTOP_DEFVAL 25332#undef UART1_MODE_REG0_NBSTOP_SHIFT 25333#undef UART1_MODE_REG0_NBSTOP_MASK 25334#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 25335#define UART1_MODE_REG0_NBSTOP_SHIFT 6 25336#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U 25337 25338/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 25339 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ 25340#undef UART1_MODE_REG0_PAR_DEFVAL 25341#undef UART1_MODE_REG0_PAR_SHIFT 25342#undef UART1_MODE_REG0_PAR_MASK 25343#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 25344#define UART1_MODE_REG0_PAR_SHIFT 3 25345#define UART1_MODE_REG0_PAR_MASK 0x00000038U 25346 25347/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ 25348#undef UART1_MODE_REG0_CHRL_DEFVAL 25349#undef UART1_MODE_REG0_CHRL_SHIFT 25350#undef UART1_MODE_REG0_CHRL_MASK 25351#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 25352#define UART1_MODE_REG0_CHRL_SHIFT 1 25353#define UART1_MODE_REG0_CHRL_MASK 0x00000006U 25354 25355/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock 25356 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ 25357#undef UART1_MODE_REG0_CLKS_DEFVAL 25358#undef UART1_MODE_REG0_CLKS_SHIFT 25359#undef UART1_MODE_REG0_CLKS_MASK 25360#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 25361#define UART1_MODE_REG0_CLKS_SHIFT 0 25362#define UART1_MODE_REG0_CLKS_MASK 0x00000001U 25363 25364/*TrustZone Classification for ADMA*/ 25365#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 25366#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 25367#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 25368#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 25369#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 25370#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU 25371 25372/*CSU regsiter*/ 25373#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 25374#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 25375#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 25376#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 25377#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 25378#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U 25379 25380/*External MIO*/ 25381#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 25382#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 25383#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 25384#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 25385#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 25386#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U 25387 25388/*JTAG toggle detect*/ 25389#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 25390#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 25391#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 25392#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 25393#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 25394#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U 25395 25396/*PL SEU error*/ 25397#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 25398#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 25399#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 25400#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 25401#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 25402#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U 25403 25404/*AMS over temperature alarm for LPD*/ 25405#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 25406#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 25407#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 25408#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 25409#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 25410#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U 25411 25412/*AMS over temperature alarm for APU*/ 25413#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 25414#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 25415#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 25416#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 25417#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 25418#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U 25419 25420/*AMS voltage alarm for VCCPINT_FPD*/ 25421#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 25422#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 25423#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 25424#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 25425#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 25426#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U 25427 25428/*AMS voltage alarm for VCCPINT_LPD*/ 25429#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 25430#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 25431#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 25432#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 25433#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 25434#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U 25435 25436/*AMS voltage alarm for VCCPAUX*/ 25437#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 25438#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 25439#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 25440#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 25441#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 25442#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U 25443 25444/*AMS voltage alarm for DDRPHY*/ 25445#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 25446#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 25447#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 25448#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 25449#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 25450#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U 25451 25452/*AMS voltage alarm for PSIO bank 0/1/2*/ 25453#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 25454#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 25455#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 25456#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 25457#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 25458#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U 25459 25460/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/ 25461#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 25462#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 25463#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 25464#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 25465#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 25466#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U 25467 25468/*AMS voltaage alarm for GT*/ 25469#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 25470#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 25471#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 25472#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 25473#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 25474#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U 25475 25476/*Set ACE outgoing AWQOS value*/ 25477#undef APU_ACE_CTRL_AWQOS_DEFVAL 25478#undef APU_ACE_CTRL_AWQOS_SHIFT 25479#undef APU_ACE_CTRL_AWQOS_MASK 25480#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F 25481#define APU_ACE_CTRL_AWQOS_SHIFT 16 25482#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U 25483 25484/*Set ACE outgoing ARQOS value*/ 25485#undef APU_ACE_CTRL_ARQOS_DEFVAL 25486#undef APU_ACE_CTRL_ARQOS_SHIFT 25487#undef APU_ACE_CTRL_ARQOS_MASK 25488#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F 25489#define APU_ACE_CTRL_ARQOS_SHIFT 0 25490#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU 25491 25492/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 25493 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e 25494 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi 25495 g a 0 to this bit.*/ 25496#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL 25497#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT 25498#undef RTC_CONTROL_BATTERY_DISABLE_MASK 25499#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 25500#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 25501#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U 25502#undef SERDES_PLL_REF_SEL0_OFFSET 25503#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 25504#undef SERDES_PLL_REF_SEL1_OFFSET 25505#define SERDES_PLL_REF_SEL1_OFFSET 0XFD410004 25506#undef SERDES_PLL_REF_SEL2_OFFSET 25507#define SERDES_PLL_REF_SEL2_OFFSET 0XFD410008 25508#undef SERDES_PLL_REF_SEL3_OFFSET 25509#define SERDES_PLL_REF_SEL3_OFFSET 0XFD41000C 25510#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET 25511#define SERDES_L0_L0_REF_CLK_SEL_OFFSET 0XFD402860 25512#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET 25513#define SERDES_L0_L1_REF_CLK_SEL_OFFSET 0XFD402864 25514#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET 25515#define SERDES_L0_L2_REF_CLK_SEL_OFFSET 0XFD402868 25516#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET 25517#define SERDES_L0_L3_REF_CLK_SEL_OFFSET 0XFD40286C 25518#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 25519#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368 25520#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 25521#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C 25522#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 25523#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370 25524#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 25525#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 0XFD406374 25526#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 25527#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 0XFD406378 25528#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 25529#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40637C 25530#undef SERDES_ICM_CFG0_OFFSET 25531#define SERDES_ICM_CFG0_OFFSET 0XFD410010 25532#undef SERDES_L1_TXPMD_TM_45_OFFSET 25533#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4 25534#undef SERDES_L1_TX_ANA_TM_118_OFFSET 25535#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8 25536#undef SERDES_L1_TXPMD_TM_48_OFFSET 25537#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0 25538#undef SERDES_L1_TX_ANA_TM_18_OFFSET 25539#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048 25540 25541/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 25542 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 25543 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ 25544#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 25545#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 25546#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 25547#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D 25548#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 25549#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU 25550 25551/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 25552 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 25553 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ 25554#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 25555#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 25556#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 25557#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 25558#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 25559#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU 25560 25561/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 25562 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 25563 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ 25564#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 25565#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 25566#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 25567#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F 25568#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 25569#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU 25570 25571/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 25572 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 25573 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ 25574#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 25575#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 25576#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 25577#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E 25578#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 25579#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU 25580 25581/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/ 25582#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 25583#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 25584#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 25585#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 25586#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 25587#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U 25588 25589/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ 25590#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 25591#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 25592#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 25593#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 25594#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 25595#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U 25596 25597/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ 25598#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 25599#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 25600#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 25601#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 25602#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 25603#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U 25604 25605/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ 25606#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 25607#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 25608#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 25609#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 25610#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 25611#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U 25612 25613/*Spread Spectrum No of Steps [7:0]*/ 25614#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 25615#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 25616#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 25617#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 25618#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 25619#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU 25620 25621/*Spread Spectrum No of Steps [10:8]*/ 25622#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 25623#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 25624#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 25625#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 25626#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 25627#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U 25628 25629/*Step Size for Spread Spectrum [7:0]*/ 25630#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 25631#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 25632#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 25633#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 25634#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 25635#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU 25636 25637/*Step Size for Spread Spectrum [15:8]*/ 25638#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 25639#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 25640#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 25641#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 25642#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 25643#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU 25644 25645/*Step Size for Spread Spectrum [23:16]*/ 25646#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 25647#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 25648#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 25649#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 25650#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 25651#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU 25652 25653/*Step Size for Spread Spectrum [25:24]*/ 25654#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 25655#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 25656#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 25657#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 25658#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 25659#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U 25660 25661/*Enable/Disable test mode force on SS step size*/ 25662#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 25663#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 25664#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 25665#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 25666#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 25667#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U 25668 25669/*Enable/Disable test mode force on SS no of steps*/ 25670#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 25671#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 25672#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 25673#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 25674#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 25675#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U 25676 25677/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse 25678 , 7 - Unused*/ 25679#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 25680#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 25681#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK 25682#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 25683#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 25684#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U 25685 25686/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused 25687 7 - Unused*/ 25688#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 25689#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 25690#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK 25691#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 25692#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 25693#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U 25694 25695/*Enable/disable DP post2 path*/ 25696#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 25697#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 25698#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 25699#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 25700#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 25701#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U 25702 25703/*Override enable/disable of DP post2 path*/ 25704#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 25705#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 25706#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 25707#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 25708#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 25709#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U 25710 25711/*Override enable/disable of DP post1 path*/ 25712#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 25713#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 25714#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 25715#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 25716#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 25717#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U 25718 25719/*Enable/disable DP main path*/ 25720#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 25721#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 25722#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 25723#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 25724#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 25725#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U 25726 25727/*Override enable/disable of DP main path*/ 25728#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 25729#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 25730#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 25731#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 25732#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 25733#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U 25734 25735/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ 25736#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 25737#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 25738#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 25739#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 25740#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 25741#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U 25742 25743/*Margining factor value*/ 25744#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 25745#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 25746#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 25747#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 25748#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 25749#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU 25750 25751/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ 25752#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 25753#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 25754#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 25755#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 25756#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 25757#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU 25758#undef CRL_APB_RST_LPD_TOP_OFFSET 25759#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C 25760#undef USB3_0_FPD_POWER_PRSNT_OFFSET 25761#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 25762#undef CRL_APB_RST_LPD_TOP_OFFSET 25763#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C 25764#undef CRL_APB_RST_LPD_IOU0_OFFSET 25765#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 25766#undef CRF_APB_RST_FPD_TOP_OFFSET 25767#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 25768#undef CRF_APB_RST_FPD_TOP_OFFSET 25769#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 25770#undef DP_DP_PHY_RESET_OFFSET 25771#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 25772#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 25773#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 25774#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET 25775#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 25776#undef USB3_0_XHCI_GFLADJ_OFFSET 25777#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 25778#undef PCIE_ATTRIB_ATTR_25_OFFSET 25779#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 25780#undef PCIE_ATTRIB_ATTR_7_OFFSET 25781#define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C 25782#undef PCIE_ATTRIB_ATTR_8_OFFSET 25783#define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020 25784#undef PCIE_ATTRIB_ATTR_9_OFFSET 25785#define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024 25786#undef PCIE_ATTRIB_ATTR_10_OFFSET 25787#define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028 25788#undef PCIE_ATTRIB_ATTR_11_OFFSET 25789#define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C 25790#undef PCIE_ATTRIB_ATTR_12_OFFSET 25791#define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030 25792#undef PCIE_ATTRIB_ATTR_13_OFFSET 25793#define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034 25794#undef PCIE_ATTRIB_ATTR_14_OFFSET 25795#define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038 25796#undef PCIE_ATTRIB_ATTR_15_OFFSET 25797#define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C 25798#undef PCIE_ATTRIB_ATTR_16_OFFSET 25799#define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040 25800#undef PCIE_ATTRIB_ATTR_17_OFFSET 25801#define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044 25802#undef PCIE_ATTRIB_ATTR_18_OFFSET 25803#define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048 25804#undef PCIE_ATTRIB_ATTR_27_OFFSET 25805#define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C 25806#undef PCIE_ATTRIB_ATTR_50_OFFSET 25807#define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8 25808#undef PCIE_ATTRIB_ATTR_105_OFFSET 25809#define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4 25810#undef PCIE_ATTRIB_ATTR_106_OFFSET 25811#define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8 25812#undef PCIE_ATTRIB_ATTR_107_OFFSET 25813#define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC 25814#undef PCIE_ATTRIB_ATTR_108_OFFSET 25815#define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0 25816#undef PCIE_ATTRIB_ATTR_109_OFFSET 25817#define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4 25818#undef PCIE_ATTRIB_ATTR_34_OFFSET 25819#define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088 25820#undef PCIE_ATTRIB_ATTR_53_OFFSET 25821#define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4 25822#undef PCIE_ATTRIB_ATTR_41_OFFSET 25823#define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4 25824#undef PCIE_ATTRIB_ATTR_97_OFFSET 25825#define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184 25826#undef PCIE_ATTRIB_ATTR_100_OFFSET 25827#define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190 25828#undef PCIE_ATTRIB_ATTR_101_OFFSET 25829#define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194 25830#undef PCIE_ATTRIB_ID_OFFSET 25831#define PCIE_ATTRIB_ID_OFFSET 0XFD480200 25832#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET 25833#define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204 25834#undef PCIE_ATTRIB_REV_ID_OFFSET 25835#define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208 25836#undef PCIE_ATTRIB_ATTR_24_OFFSET 25837#define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060 25838#undef PCIE_ATTRIB_ATTR_25_OFFSET 25839#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 25840#undef AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_OFFSET 25841#define AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_OFFSET 0XFD0F0000 25842#undef PCIE_ATTRIB_ATTR_4_OFFSET 25843#define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010 25844#undef PCIE_ATTRIB_ATTR_89_OFFSET 25845#define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164 25846#undef PCIE_ATTRIB_ATTR_43_OFFSET 25847#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC 25848#undef PCIE_ATTRIB_ATTR_45_OFFSET 25849#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4 25850#undef PCIE_ATTRIB_CB_OFFSET 25851#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C 25852#undef PCIE_ATTRIB_ATTR_35_OFFSET 25853#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C 25854#undef PCIE_ATTRIB_ATTR_37_OFFSET 25855#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094 25856 25857/*USB 0 reset for control registers*/ 25858#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 25859#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 25860#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 25861#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF 25862#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 25863#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U 25864 25865/*This bit is used to choose between PIPE power present and 1'b1*/ 25866#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 25867#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 25868#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK 25869#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 25870#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 25871#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U 25872 25873/*USB 0 sleep circuit reset*/ 25874#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 25875#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 25876#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 25877#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF 25878#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 25879#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U 25880 25881/*USB 0 reset*/ 25882#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 25883#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 25884#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 25885#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF 25886#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 25887#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U 25888 25889/*GEM 2 reset*/ 25890#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 25891#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 25892#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 25893#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 0x0000000F 25894#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2 25895#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 0x00000004U 25896 25897/*PCIE config reset*/ 25898#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 25899#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 25900#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 25901#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE 25902#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 25903#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U 25904 25905/*PCIE control block level reset*/ 25906#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 25907#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 25908#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 25909#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE 25910#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 25911#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U 25912 25913/*PCIE bridge block level reset (AXI interface)*/ 25914#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 25915#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 25916#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 25917#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE 25918#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 25919#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U 25920 25921/*Display Port block level reset (includes DPDMA)*/ 25922#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 25923#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 25924#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 25925#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE 25926#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 25927#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U 25928 25929/*Set to '1' to hold the GT in reset. Clear to release.*/ 25930#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 25931#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 25932#undef DP_DP_PHY_RESET_GT_RESET_MASK 25933#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 25934#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 25935#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U 25936 25937/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 25938 ane0 Bits [3:2] - lane 1*/ 25939#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 25940#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 25941#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 25942#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 25943#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 25944#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU 25945 25946/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 25947 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S 25948 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level 25949 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit 25950 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 25951 alue. Note: This field is valid only in device mode.*/ 25952#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 25953#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 25954#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 25955#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 25956#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 25957#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U 25958 25959/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio 25960 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the 25961 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de 25962 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power 25963 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur 25964 ng hibernation. - This bit is valid only in device mode.*/ 25965#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 25966#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 25967#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 25968#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 25969#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 25970#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U 25971 25972/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen 25973 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre 25974 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 25975 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh 25976 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma 25977 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet 25978 d.*/ 25979#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 25980#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 25981#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 25982#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 25983#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 25984#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U 25985 25986/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P 25987 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 25988 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte 25989 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i 25990 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/ 25991#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 25992#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 25993#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 25994#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 25995#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 25996#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U 25997 25998/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co 25999 figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app 26000 ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
26001 r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s 26002 t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati 26003 g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi 26004 when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/ 26005#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 26006#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 26007#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 26008#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 26009#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 26010#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U 26011 26012/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 26013 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 26014 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U 26015 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/ 26016#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 26017#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 26018#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 26019#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 26020#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 26021#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U 26022 26023/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa 26024 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons 26025 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s 26026 lected through DWC_USB3_HSPHY_INTERFACE.*/ 26027#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 26028#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 26029#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 26030#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 26031#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 26032#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U 26033 26034/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a 26035 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 26036 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen 26037 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I 26038 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/ 26039#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 26040#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 26041#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 26042#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 26043#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 26044#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U 26045 26046/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by 26047 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 26048 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta 26049 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. 26050 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 26051 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH 26052 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One 26053 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/ 26054#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 26055#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 26056#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 26057#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 26058#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 26059#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U 26060 26061/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 26062 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP 26063 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF 26064 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p 26065 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d 26066 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc 26067 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = 26068 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P 26069 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/ 26070#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 26071#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 26072#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 26073#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 26074#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 26075#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U 26076 26077/*Status Read value of PLL Lock*/ 26078#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 26079#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 26080#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 26081#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 26082#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 26083#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U 26084#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 26085 26086/*Status Read value of PLL Lock*/ 26087#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 26088#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 26089#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 26090#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 26091#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 26092#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U 26093#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 26094 26095/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root 26096 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/ 26097#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 26098#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 26099#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 26100#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 26101#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 26102#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U 26103 26104/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def 26105 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = 26106 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a 26107 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 26108 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert 26109 re size in bytes.; EP=0x0004; RP=0x0000*/ 26110#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL 26111#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 26112#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 26113#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL 26114#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 26115#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU 26116 26117/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def 26118 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = 26119 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a 26120 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 26121 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert 26122 re size in bytes.; EP=0xFFF0; RP=0x0000*/ 26123#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL 26124#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 26125#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 26126#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL 26127#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 26128#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU 26129 26130/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 26131 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe 26132 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 26133 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 26134 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 26135 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b 26136 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ 26137#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL 26138#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 26139#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 26140#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL 26141#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 26142#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU 26143 26144/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 26145 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe 26146 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 26147 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 26148 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 26149 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b 26150 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ 26151#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL 26152#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 26153#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 26154#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL 26155#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 26156#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU 26157 26158/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b 26159 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri 26160 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin 26161 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi 26162 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe 26163 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 26164 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper 26165 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/ 26166#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL 26167#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 26168#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 26169#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL 26170#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 26171#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU 26172 26173/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b 26174 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri 26175 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin 26176 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi 26177 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe 26178 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 26179 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper 26180 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/ 26181#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL 26182#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 26183#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 26184#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL 26185#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 26186#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU 26187 26188/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b 26189 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri 26190 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas 26191 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b 26192 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s 26193 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; 26194 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 26195 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl 26196 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ 26197#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL 26198#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 26199#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 26200#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL 26201#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 26202#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU 26203 26204/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b 26205 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri 26206 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas 26207 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b 26208 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s 26209 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; 26210 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 26211 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl 26212 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/ 26213#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL 26214#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 26215#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 26216#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL 26217#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 26218#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU 26219 26220/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b 26221 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri 26222 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin 26223 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi 26224 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe 26225 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 26226 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper 26227 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/ 26228#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL 26229#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 26230#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 26231#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL 26232#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 26233#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU 26234 26235/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b 26236 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri 26237 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin 26238 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi 26239 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe 26240 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 26241 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper 26242 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/ 26243#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL 26244#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 26245#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 26246#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL 26247#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 26248#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU 26249 26250/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b 26251 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri 26252 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable 26253 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 26254 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B 26255 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 26256 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 26257 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u 26258 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ 26259#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL 26260#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 26261#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 26262#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL 26263#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 26264#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU 26265 26266/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b 26267 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri 26268 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable 26269 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 26270 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B 26271 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 26272 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 26273 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u 26274 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ 26275#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL 26276#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 26277#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 26278#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL 26279#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 26280#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU 26281 26282/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred 26283 to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/ 26284#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 26285#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 26286#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 26287#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 26288#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 26289#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U 26290 26291/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 26292 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 26293 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/ 26294#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 26295#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 26296#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 26297#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 26298#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 26299#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U 26300 26301/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 26302 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw 26303 tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r 26304 gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/ 26305#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 26306#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 26307#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 26308#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 26309#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 26310#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U 26311 26312/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab 26313 lity.; EP=0x009C; RP=0x0000*/ 26314#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 26315#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 26316#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 26317#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 26318#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 26319#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U 26320 26321/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l 26322 ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/ 26323#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL 26324#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 26325#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 26326#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL 26327#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 26328#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU 26329 26330/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 26331 osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/ 26332#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 26333#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 26334#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 26335#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 26336#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 26337#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU 26338 26339/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da 26340 a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and 26341 completion header credits must be <= 80; EP=0x0004; RP=0x000C*/ 26342#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 26343#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 26344#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 26345#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 26346#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 26347#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U 26348 26349/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 26350 redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support 26351 d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be 26352 less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/ 26353#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL 26354#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 26355#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 26356#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL 26357#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 26358#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU 26359 26360/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 26361 han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/ 26362#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL 26363#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 26364#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 26365#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL 26366#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 26367#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU 26368 26369/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 26370 0*/ 26371#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 26372#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 26373#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 26374#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 26375#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 26376#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U 26377 26378/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/ 26379#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 26380#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 26381#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 26382#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 26383#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 26384#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U 26385 26386/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER 26387 cap structure; EP=0x0003; RP=0x0003*/ 26388#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 26389#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 26390#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 26391#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 26392#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 26393#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U 26394 26395/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n 26396 mber of brams configured for transmit; EP=0x001C; RP=0x001C*/ 26397#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 26398#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 26399#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 26400#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 26401#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 26402#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U 26403 26404/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post 26405 d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/ 26406#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 26407#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 26408#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 26409#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 26410#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 26411#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU 26412 26413/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit 26414 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/ 26415#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 26416#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 26417#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 26418#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 26419#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 26420#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU 26421 26422/*Indicates mapping for legacy interrupt messages. Valid values are 1 INTA, 2 INTB, 3 INTC, 4 INTD. Zero indicates no legacy in 26423 errupt messages used.; EP=0x0001; RP=0x0001*/ 26424#undef PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_DEFVAL 26425#undef PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_SHIFT 26426#undef PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_MASK 26427#define PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_DEFVAL 0x00000100 26428#define PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_SHIFT 8 26429#define PCIE_ATTRIB_ATTR_34_ATTR_INTERRUPT_PIN_MASK 0x0000FF00U 26430 26431/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil 26432 ty.; EP=0x0048; RP=0x0060*/ 26433#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 26434#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 26435#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 26436#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 26437#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 26438#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU 26439 26440/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor 26441 to Cap structure; EP=0x0000; RP=0x0000*/ 26442#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 26443#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 26444#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 26445#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 26446#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 26447#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U 26448 26449/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 26450 he management port.; EP=0x0001; RP=0x0000*/ 26451#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 26452#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 26453#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 26454#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 26455#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 26456#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U 26457 26458/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi 26459 ity.; EP=0x0060; RP=0x0000*/ 26460#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 26461#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 26462#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 26463#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 26464#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 26465#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU 26466 26467/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 26468 he management port.; EP=0x0001; RP=0x0000*/ 26469#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 26470#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 26471#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 26472#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 26473#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 26474#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U 26475 26476/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/ 26477#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 26478#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 26479#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 26480#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 26481#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 26482#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU 26483 26484/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 26485 4; RP=0x0004*/ 26486#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 26487#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 26488#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 26489#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 26490#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 26491#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U 26492 26493/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/ 26494#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 26495#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 26496#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 26497#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 26498#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 26499#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U 26500 26501/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 26502 LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, 26503 Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; 26504 EP=0x0000; RP=0x07FF*/ 26505#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 26506#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 26507#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 26508#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 26509#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 26510#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U 26511 26512/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/ 26513#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 26514#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 26515#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 26516#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 26517#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 26518#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U 26519 26520/*Device ID for the the PCIe Cap Structure Device ID field*/ 26521#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 26522#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 26523#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 26524#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 26525#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 26526#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU 26527 26528/*Vendor ID for the PCIe Cap Structure Vendor ID field*/ 26529#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 26530#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 26531#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 26532#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 26533#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 26534#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U 26535 26536/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/ 26537#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 26538#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 26539#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 26540#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 26541#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 26542#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU 26543 26544/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/ 26545#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 26546#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 26547#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 26548#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 26549#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 26550#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U 26551 26552/*Revision ID for the the PCIe Cap Structure*/ 26553#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL 26554#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 26555#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 26556#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL 26557#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 26558#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU 26559 26560/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 26561 8000; RP=0x8000*/ 26562#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL 26563#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 26564#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 26565#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL 26566#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 26567#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU 26568 26569/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 26570 0005; RP=0x0006*/ 26571#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 26572#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 26573#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 26574#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 26575#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 26576#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU 26577 26578/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/ 26579#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 26580#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 26581#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 26582#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 26583#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 26584#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U 26585 26586/*Determines which PCI Express Base Address Region (BAR) is used to access DMA and Bridge Registers from PCI Express. If a rece 26587 ved PCI Express read/write requests' BAR hit information is equal to cfg_dma_reg_bar, then the transaction is terminated by t 26588 e internal DMA/Bridge Register implementation, otherwise the transaction is forwarded to the AXI Master Interface. cfg_dma_re 26589 _bar is only for received PCI Express read and write requests and has no impact on received AXI Slave Interface requests.*/ 26590#undef AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_DEFVAL 26591#undef AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_SHIFT 26592#undef AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_MASK 26593#define AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_DEFVAL 0x00010000 26594#define AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_SHIFT 0 26595#define AXIPCIE_MAIN_BRIDGE_CORE_CFG_PCIE_RX0_CFG_DMA_REG_BAR_MASK 0x00000007U 26596 26597/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 26598 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess 26599 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ 26600#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 26601#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 26602#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 26603#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 26604#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 26605#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U 26606 26607/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 26608 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess 26609 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ 26610#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 26611#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 26612#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 26613#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 26614#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 26615#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U 26616 26617/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP 26618 0x0140; RP=0x0140*/ 26619#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 26620#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 26621#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 26622#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 26623#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 26624#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU 26625 26626/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o 26627 the management port.; EP=0x0001; RP=0x0000*/ 26628#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 26629#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 26630#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 26631#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 26632#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 26633#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U 26634 26635/*MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled.; EP=0x00 26636 0; RP=0x0000*/ 26637#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_DEFVAL 26638#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_SHIFT 26639#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_MASK 26640#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_DEFVAL 0x00000100 26641#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_SHIFT 9 26642#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_PBA_BIR_MASK 0x00000E00U 26643 26644/*MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0 26645 00*/ 26646#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_DEFVAL 26647#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_SHIFT 26648#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_MASK 26649#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_DEFVAL 0x00008000 26650#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_SHIFT 0 26651#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_TABLE_BIR_MASK 0x00000007U 26652 26653/*DT837748 Enable*/ 26654#undef PCIE_ATTRIB_CB_CB1_DEFVAL 26655#undef PCIE_ATTRIB_CB_CB1_SHIFT 26656#undef PCIE_ATTRIB_CB_CB1_MASK 26657#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 26658#define PCIE_ATTRIB_CB_CB1_SHIFT 1 26659#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U 26660 26661/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc 26662 ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/ 26663#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 26664#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 26665#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 26666#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD 26667#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 26668#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U 26669 26670/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r 26671 gister.; EP=0x0001; RP=0x0001*/ 26672#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 26673#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 26674#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 26675#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF 26676#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 26677#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U 26678#undef CRL_APB_RST_LPD_TOP_OFFSET 26679#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C 26680#undef CRL_APB_RST_LPD_IOU0_OFFSET 26681#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 26682#undef CRF_APB_RST_FPD_TOP_OFFSET 26683#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 26684#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 26685#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 26686#undef DP_DP_PHY_RESET_OFFSET 26687#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 26688#undef CRF_APB_RST_FPD_TOP_OFFSET 26689#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 26690 26691/*USB 0 reset for control registers*/ 26692#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 26693#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 26694#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 26695#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF 26696#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 26697#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U 26698 26699/*USB 0 sleep circuit reset*/ 26700#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 26701#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 26702#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 26703#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF 26704#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 26705#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U 26706 26707/*USB 0 reset*/ 26708#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 26709#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 26710#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 26711#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF 26712#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 26713#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U 26714 26715/*GEM 2 reset*/ 26716#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 26717#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 26718#undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 26719#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 0x0000000F 26720#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2 26721#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 0x00000004U 26722 26723/*PCIE config reset*/ 26724#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 26725#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 26726#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 26727#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE 26728#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 26729#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U 26730 26731/*PCIE control block level reset*/ 26732#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 26733#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 26734#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 26735#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE 26736#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 26737#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U 26738 26739/*PCIE bridge block level reset (AXI interface)*/ 26740#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 26741#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 26742#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 26743#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE 26744#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 26745#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U 26746 26747/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 26748 ane0 Bits [3:2] - lane 1*/ 26749#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 26750#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 26751#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 26752#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 26753#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 26754#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU 26755 26756/*Set to '1' to hold the GT in reset. Clear to release.*/ 26757#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 26758#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 26759#undef DP_DP_PHY_RESET_GT_RESET_MASK 26760#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 26761#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 26762#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U 26763 26764/*Display Port block level reset (includes DPDMA)*/ 26765#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 26766#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 26767#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 26768#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE 26769#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 26770#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U 26771#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 26772#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 26773#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 26774#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 26775 26776/*Power-up Request Interrupt Enable for PL*/ 26777#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 26778#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 26779#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 26780#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 26781#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 26782#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U 26783 26784/*Power-up Request Trigger for PL*/ 26785#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 26786#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 26787#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 26788#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 26789#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 26790#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U 26791 26792/*Power-up Request Status for PL*/ 26793#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 26794#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 26795#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 26796#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 26797#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 26798#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U 26799#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 26800#undef GPIO_MASK_DATA_5_MSW_OFFSET 26801#define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C 26802#undef GPIO_DIRM_5_OFFSET 26803#define GPIO_DIRM_5_OFFSET 0XFF0A0344 26804#undef GPIO_OEN_5_OFFSET 26805#define GPIO_OEN_5_OFFSET 0XFF0A0348 26806#undef GPIO_DATA_5_OFFSET 26807#define GPIO_DATA_5_OFFSET 0XFF0A0054 26808#undef GPIO_DATA_5_OFFSET 26809#define GPIO_DATA_5_OFFSET 0XFF0A0054 26810#undef GPIO_DATA_5_OFFSET 26811#define GPIO_DATA_5_OFFSET 0XFF0A0054 26812 26813/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/ 26814#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 26815#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 26816#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 26817#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 26818#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 26819#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U 26820 26821/*Operation is the same as DIRM_0[DIRECTION_0]*/ 26822#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL 26823#undef GPIO_DIRM_5_DIRECTION_5_SHIFT 26824#undef GPIO_DIRM_5_DIRECTION_5_MASK 26825#define GPIO_DIRM_5_DIRECTION_5_DEFVAL 26826#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 26827#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU 26828 26829/*Operation is the same as OEN_0[OP_ENABLE_0]*/ 26830#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL 26831#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT 26832#undef GPIO_OEN_5_OP_ENABLE_5_MASK 26833#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL 26834#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 26835#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU 26836 26837/*Output Data*/ 26838#undef GPIO_DATA_5_DATA_5_DEFVAL 26839#undef GPIO_DATA_5_DATA_5_SHIFT 26840#undef GPIO_DATA_5_DATA_5_MASK 26841#define GPIO_DATA_5_DATA_5_DEFVAL 26842#define GPIO_DATA_5_DATA_5_SHIFT 0 26843#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU 26844 26845/*Output Data*/ 26846#undef GPIO_DATA_5_DATA_5_DEFVAL 26847#undef GPIO_DATA_5_DATA_5_SHIFT 26848#undef GPIO_DATA_5_DATA_5_MASK 26849#define GPIO_DATA_5_DATA_5_DEFVAL 26850#define GPIO_DATA_5_DATA_5_SHIFT 0 26851#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU 26852 26853/*Output Data*/ 26854#undef GPIO_DATA_5_DATA_5_DEFVAL 26855#undef GPIO_DATA_5_DATA_5_SHIFT 26856#undef GPIO_DATA_5_DATA_5_MASK 26857#define GPIO_DATA_5_DATA_5_DEFVAL 26858#define GPIO_DATA_5_DATA_5_SHIFT 0 26859#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU 26860#ifdef __cplusplus 26861extern "C" { 26862#endif 26863 int psu_init (); 26864 unsigned long psu_ps_pl_isolation_removal_data(); 26865 unsigned long psu_ps_pl_reset_config_data(); 26866#ifdef __cplusplus 26867} 26868#endif 26869