uboot/drivers/block/pata_bfin.c
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   1/*
   2 * Driver for Blackfin on-chip ATAPI controller.
   3 *
   4 * Enter bugs at http://blackfin.uclinux.org/
   5 *
   6 * Copyright (c) 2008 Analog Devices Inc.
   7 *
   8 * Licensed under the GPL-2 or later.
   9 */
  10
  11#include <common.h>
  12#include <command.h>
  13#include <config.h>
  14#include <asm/byteorder.h>
  15#include <asm/clock.h>
  16#include <asm/io.h>
  17#include <linux/errno.h>
  18#include <asm/portmux.h>
  19#include <asm/mach-common/bits/pata.h>
  20#include <ata.h>
  21#include <sata.h>
  22#include <libata.h>
  23#include "pata_bfin.h"
  24
  25static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
  26
  27/**
  28 * PIO Mode - Frequency compatibility
  29 */
  30/* mode: 0         1         2         3         4 */
  31static const u32 pio_fsclk[] =
  32{ 33333333, 33333333, 33333333, 33333333, 33333333 };
  33
  34/**
  35 * MDMA Mode - Frequency compatibility
  36 */
  37/*               mode:      0         1         2        */
  38static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
  39
  40/**
  41 * UDMA Mode - Frequency compatibility
  42 *
  43 * UDMA5 - 100 MB/s   - SCLK  = 133 MHz
  44 * UDMA4 - 66 MB/s    - SCLK >=  80 MHz
  45 * UDMA3 - 44.4 MB/s  - SCLK >=  50 MHz
  46 * UDMA2 - 33 MB/s    - SCLK >=  40 MHz
  47 */
  48/* mode: 0         1         2         3         4          5 */
  49static const u32 udma_fsclk[] =
  50{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
  51
  52/**
  53 * Register transfer timing table
  54 */
  55/*               mode:       0    1    2    3    4    */
  56/* Cycle Time                     */
  57static const u32 reg_t0min[]   = { 600, 383, 330, 180, 120 };
  58/* DIOR/DIOW to end cycle         */
  59static const u32 reg_t2min[]   = { 290, 290, 290, 70,  25  };
  60/* DIOR/DIOW asserted pulse width */
  61static const u32 reg_teocmin[] = { 290, 290, 290, 80,  70  };
  62
  63/**
  64 * PIO timing table
  65 */
  66/*               mode:       0    1    2    3    4    */
  67/* Cycle Time                     */
  68static const u32 pio_t0min[]   = { 600, 383, 240, 180, 120 };
  69/* Address valid to DIOR/DIORW    */
  70static const u32 pio_t1min[]   = { 70,  50,  30,  30,  25  };
  71/* DIOR/DIOW to end cycle         */
  72static const u32 pio_t2min[]   = { 165, 125, 100, 80,  70  };
  73/* DIOR/DIOW asserted pulse width */
  74static const u32 pio_teocmin[] = { 165, 125, 100, 70,  25  };
  75/* DIOW data hold                 */
  76static const u32 pio_t4min[]   = { 30,  20,  15,  10,  10  };
  77
  78/* ******************************************************************
  79 * Multiword DMA timing table
  80 * ******************************************************************
  81 */
  82/*               mode:       0   1    2        */
  83/* Cycle Time                     */
  84static const u32 mdma_t0min[]  = { 480, 150, 120 };
  85/* DIOR/DIOW asserted pulse width */
  86static const u32 mdma_tdmin[]  = { 215, 80,  70  };
  87/* DMACK to read data released    */
  88static const u32 mdma_thmin[]  = { 20,  15,  10  };
  89/* DIOR/DIOW to DMACK hold        */
  90static const u32 mdma_tjmin[]  = { 20,  5,   5   };
  91/* DIOR negated pulse width       */
  92static const u32 mdma_tkrmin[] = { 50,  50,  25  };
  93/* DIOR negated pulse width       */
  94static const u32 mdma_tkwmin[] = { 215, 50,  25  };
  95/* CS[1:0] valid to DIOR/DIOW     */
  96static const u32 mdma_tmmin[]  = { 50,  30,  25  };
  97/* DMACK to read data released    */
  98static const u32 mdma_tzmax[]  = { 20,  25,  25  };
  99
 100/**
 101 * Ultra DMA timing table
 102 */
 103/*               mode:         0    1    2    3    4    5       */
 104static const u32 udma_tcycmin[]  = { 112, 73,  54,  39,  25,  17 };
 105static const u32 udma_tdvsmin[]  = { 70,  48,  31,  20,  7,   5  };
 106static const u32 udma_tenvmax[]  = { 70,  70,  70,  55,  55,  50 };
 107static const u32 udma_trpmin[]   = { 160, 125, 100, 100, 100, 85 };
 108static const u32 udma_tmin[]     = { 5,   5,   5,   5,   3,   3  };
 109
 110
 111static const u32 udma_tmlimin = 20;
 112static const u32 udma_tzahmin = 20;
 113static const u32 udma_tenvmin = 20;
 114static const u32 udma_tackmin = 20;
 115static const u32 udma_tssmin = 50;
 116
 117static void msleep(int count)
 118{
 119        int i;
 120
 121        for (i = 0; i < count; i++)
 122                udelay(1000);
 123}
 124
 125/**
 126 *
 127 *      Function:       num_clocks_min
 128 *
 129 *      Description:
 130 *      calculate number of SCLK cycles to meet minimum timing
 131 */
 132static unsigned short num_clocks_min(unsigned long tmin,
 133                                unsigned long fsclk)
 134{
 135        unsigned long tmp ;
 136        unsigned short result;
 137
 138        tmp = tmin * (fsclk/1000/1000) / 1000;
 139        result = (unsigned short)tmp;
 140        if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
 141                result++;
 142
 143        return result;
 144}
 145
 146/**
 147 *      bfin_set_piomode - Initialize host controller PATA PIO timings
 148 *      @ap: Port whose timings we are configuring
 149 *      @pio_mode: mode
 150 *
 151 *      Set PIO mode for device.
 152 *
 153 *      LOCKING:
 154 *      None (inherited from caller).
 155 */
 156
 157static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
 158{
 159        int mode = pio_mode - XFER_PIO_0;
 160        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 161        unsigned int fsclk = get_sclk();
 162        unsigned short teoc_reg, t2_reg, teoc_pio;
 163        unsigned short t4_reg, t2_pio, t1_reg;
 164        unsigned short n0, n6, t6min = 5;
 165
 166        /* the most restrictive timing value is t6 and tc, the DIOW - data hold
 167        * If one SCLK pulse is longer than this minimum value then register
 168        * transfers cannot be supported at this frequency.
 169        */
 170        n6 = num_clocks_min(t6min, fsclk);
 171        if (mode >= 0 && mode <= 4 && n6 >= 1) {
 172                debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
 173                /* calculate the timing values for register transfers. */
 174                while (mode > 0 && pio_fsclk[mode] > fsclk)
 175                        mode--;
 176
 177                /* DIOR/DIOW to end cycle time */
 178                t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
 179                /* DIOR/DIOW asserted pulse width */
 180                teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
 181                /* Cycle Time */
 182                n0  = num_clocks_min(reg_t0min[mode], fsclk);
 183
 184                /* increase t2 until we meed the minimum cycle length */
 185                if (t2_reg + teoc_reg < n0)
 186                        t2_reg = n0 - teoc_reg;
 187
 188                /* calculate the timing values for pio transfers. */
 189
 190                /* DIOR/DIOW to end cycle time */
 191                t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
 192                /* DIOR/DIOW asserted pulse width */
 193                teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
 194                /* Cycle Time */
 195                n0  = num_clocks_min(pio_t0min[mode], fsclk);
 196
 197                /* increase t2 until we meed the minimum cycle length */
 198                if (t2_pio + teoc_pio < n0)
 199                        t2_pio = n0 - teoc_pio;
 200
 201                /* Address valid to DIOR/DIORW */
 202                t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
 203
 204                /* DIOW data hold */
 205                t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
 206
 207                ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
 208                ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
 209                ATAPI_SET_PIO_TIM_1(base, teoc_pio);
 210                if (mode > 2) {
 211                        ATAPI_SET_CONTROL(base,
 212                                ATAPI_GET_CONTROL(base) | IORDY_EN);
 213                } else {
 214                        ATAPI_SET_CONTROL(base,
 215                                ATAPI_GET_CONTROL(base) & ~IORDY_EN);
 216                }
 217
 218                /* Disable host ATAPI PIO interrupts */
 219                ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
 220                        & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
 221                SSYNC();
 222        }
 223}
 224
 225/**
 226 *
 227 *    Function:       wait_complete
 228 *
 229 *    Description:    Waits the interrupt from device
 230 *
 231 */
 232static inline void wait_complete(void __iomem *base, unsigned short mask)
 233{
 234        unsigned short status;
 235        unsigned int i = 0;
 236
 237        for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
 238                status = ATAPI_GET_INT_STATUS(base) & mask;
 239                if (status)
 240                        break;
 241        }
 242
 243        ATAPI_SET_INT_STATUS(base, mask);
 244}
 245
 246/**
 247 *
 248 *    Function:       write_atapi_register
 249 *
 250 *    Description:    Writes to ATA Device Resgister
 251 *
 252 */
 253
 254static void write_atapi_register(void __iomem *base,
 255                unsigned long ata_reg, unsigned short value)
 256{
 257        /* Program the ATA_DEV_TXBUF register with write data (to be
 258         * written into the device).
 259         */
 260        ATAPI_SET_DEV_TXBUF(base, value);
 261
 262        /* Program the ATA_DEV_ADDR register with address of the
 263         * device register (0x01 to 0x0F).
 264         */
 265        ATAPI_SET_DEV_ADDR(base, ata_reg);
 266
 267        /* Program the ATA_CTRL register with dir set to write (1)
 268         */
 269        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
 270
 271        /* ensure PIO DMA is not set */
 272        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
 273
 274        /* and start the transfer */
 275        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
 276
 277        /* Wait for the interrupt to indicate the end of the transfer.
 278         * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
 279         */
 280        wait_complete(base, PIO_DONE_INT);
 281}
 282
 283/**
 284 *
 285 *      Function:       read_atapi_register
 286 *
 287 *Description:    Reads from ATA Device Resgister
 288 *
 289 */
 290
 291static unsigned short read_atapi_register(void __iomem *base,
 292                unsigned long ata_reg)
 293{
 294        /* Program the ATA_DEV_ADDR register with address of the
 295         * device register (0x01 to 0x0F).
 296         */
 297        ATAPI_SET_DEV_ADDR(base, ata_reg);
 298
 299        /* Program the ATA_CTRL register with dir set to read (0) and
 300         */
 301        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
 302
 303        /* ensure PIO DMA is not set */
 304        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
 305
 306        /* and start the transfer */
 307        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
 308
 309        /* Wait for the interrupt to indicate the end of the transfer.
 310         * (PIO_DONE interrupt is set and it doesn't seem to matter
 311         * that we don't clear it)
 312         */
 313        wait_complete(base, PIO_DONE_INT);
 314
 315        /* Read the ATA_DEV_RXBUF register with write data (to be
 316         * written into the device).
 317         */
 318        return ATAPI_GET_DEV_RXBUF(base);
 319}
 320
 321/**
 322 *
 323 *    Function:       write_atapi_register_data
 324 *
 325 *    Description:    Writes to ATA Device Resgister
 326 *
 327 */
 328
 329static void write_atapi_data(void __iomem *base,
 330                int len, unsigned short *buf)
 331{
 332        int i;
 333
 334        /* Set transfer length to 1 */
 335        ATAPI_SET_XFER_LEN(base, 1);
 336
 337        /* Program the ATA_DEV_ADDR register with address of the
 338         * ATA_REG_DATA
 339         */
 340        ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
 341
 342        /* Program the ATA_CTRL register with dir set to write (1)
 343         */
 344        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
 345
 346        /* ensure PIO DMA is not set */
 347        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
 348
 349        for (i = 0; i < len; i++) {
 350                /* Program the ATA_DEV_TXBUF register with write data (to be
 351                 * written into the device).
 352                 */
 353                ATAPI_SET_DEV_TXBUF(base, buf[i]);
 354
 355                /* and start the transfer */
 356                ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
 357
 358                /* Wait for the interrupt to indicate the end of the transfer.
 359                 * (We need to wait on and clear rhe ATA_DEV_INT
 360                 * interrupt status)
 361                 */
 362                wait_complete(base, PIO_DONE_INT);
 363        }
 364}
 365
 366/**
 367 *
 368 *      Function:       read_atapi_register_data
 369 *
 370 *      Description:    Reads from ATA Device Resgister
 371 *
 372 */
 373
 374static void read_atapi_data(void __iomem *base,
 375                int len, unsigned short *buf)
 376{
 377        int i;
 378
 379        /* Set transfer length to 1 */
 380        ATAPI_SET_XFER_LEN(base, 1);
 381
 382        /* Program the ATA_DEV_ADDR register with address of the
 383         * ATA_REG_DATA
 384         */
 385        ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
 386
 387        /* Program the ATA_CTRL register with dir set to read (0) and
 388         */
 389        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
 390
 391        /* ensure PIO DMA is not set */
 392        ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
 393
 394        for (i = 0; i < len; i++) {
 395                /* and start the transfer */
 396                ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
 397
 398                /* Wait for the interrupt to indicate the end of the transfer.
 399                 * (PIO_DONE interrupt is set and it doesn't seem to matter
 400                 * that we don't clear it)
 401                 */
 402                wait_complete(base, PIO_DONE_INT);
 403
 404                /* Read the ATA_DEV_RXBUF register with write data (to be
 405                 * written into the device).
 406                 */
 407                buf[i] = ATAPI_GET_DEV_RXBUF(base);
 408        }
 409}
 410
 411/**
 412 *      bfin_check_status - Read device status reg & clear interrupt
 413 *      @ap: port where the device is
 414 *
 415 *      Note: Original code is ata_check_status().
 416 */
 417
 418static u8 bfin_check_status(struct ata_port *ap)
 419{
 420        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 421        return read_atapi_register(base, ATA_REG_STATUS);
 422}
 423
 424/**
 425 *      bfin_check_altstatus - Read device alternate status reg
 426 *      @ap: port where the device is
 427 */
 428
 429static u8 bfin_check_altstatus(struct ata_port *ap)
 430{
 431        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 432        return read_atapi_register(base, ATA_REG_ALTSTATUS);
 433}
 434
 435/**
 436 *      bfin_ata_busy_wait - Wait for a port status register
 437 *      @ap: Port to wait for.
 438 *      @bits: bits that must be clear
 439 *      @max: number of 10uS waits to perform
 440 *
 441 *      Waits up to max*10 microseconds for the selected bits in the port's
 442 *      status register to be cleared.
 443 *      Returns final value of status register.
 444 *
 445 *      LOCKING:
 446 *      Inherited from caller.
 447 */
 448static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
 449                                unsigned int max, u8 usealtstatus)
 450{
 451        u8 status;
 452
 453        do {
 454                udelay(10);
 455                if (usealtstatus)
 456                        status = bfin_check_altstatus(ap);
 457                else
 458                        status = bfin_check_status(ap);
 459                max--;
 460        } while (status != 0xff && (status & bits) && (max > 0));
 461
 462        return status;
 463}
 464
 465/**
 466 *      bfin_ata_busy_sleep - sleep until BSY clears, or timeout
 467 *      @ap: port containing status register to be polled
 468 *      @tmout_pat: impatience timeout in msecs
 469 *      @tmout: overall timeout in msecs
 470 *
 471 *      Sleep until ATA Status register bit BSY clears,
 472 *      or a timeout occurs.
 473 *
 474 *      RETURNS:
 475 *      0 on success, -errno otherwise.
 476 */
 477static int bfin_ata_busy_sleep(struct ata_port *ap,
 478                       long tmout_pat, unsigned long tmout)
 479{
 480        u8 status;
 481
 482        status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
 483        while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
 484                msleep(50);
 485                tmout_pat -= 50;
 486                status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
 487        }
 488
 489        if (status != 0xff && (status & ATA_BUSY))
 490                printf("port is slow to respond, please be patient "
 491                                "(Status 0x%x)\n", status);
 492
 493        while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
 494                msleep(50);
 495                tmout_pat -= 50;
 496                status = bfin_check_status(ap);
 497        }
 498
 499        if (status == 0xff)
 500                return -ENODEV;
 501
 502        if (status & ATA_BUSY) {
 503                printf("port failed to respond "
 504                                "(%lu secs, Status 0x%x)\n",
 505                                DIV_ROUND_UP(tmout, 1000), status);
 506                return -EBUSY;
 507        }
 508
 509        return 0;
 510}
 511
 512/**
 513 *      bfin_dev_select - Select device 0/1 on ATA bus
 514 *      @ap: ATA channel to manipulate
 515 *      @device: ATA device (numbered from zero) to select
 516 *
 517 *      Note: Original code is ata_sff_dev_select().
 518 */
 519
 520static void bfin_dev_select(struct ata_port *ap, unsigned int device)
 521{
 522        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 523        u8 tmp;
 524
 525
 526        if (device == 0)
 527                tmp = ATA_DEVICE_OBS;
 528        else
 529                tmp = ATA_DEVICE_OBS | ATA_DEV1;
 530
 531        write_atapi_register(base, ATA_REG_DEVICE, tmp);
 532        udelay(1);
 533}
 534
 535/**
 536 *      bfin_devchk - PATA device presence detection
 537 *      @ap: ATA channel to examine
 538 *      @device: Device to examine (starting at zero)
 539 *
 540 *      Note: Original code is ata_devchk().
 541 */
 542
 543static unsigned int bfin_devchk(struct ata_port *ap,
 544                                unsigned int device)
 545{
 546        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 547        u8 nsect, lbal;
 548
 549        bfin_dev_select(ap, device);
 550
 551        write_atapi_register(base, ATA_REG_NSECT, 0x55);
 552        write_atapi_register(base, ATA_REG_LBAL, 0xaa);
 553
 554        write_atapi_register(base, ATA_REG_NSECT, 0xaa);
 555        write_atapi_register(base, ATA_REG_LBAL, 0x55);
 556
 557        write_atapi_register(base, ATA_REG_NSECT, 0x55);
 558        write_atapi_register(base, ATA_REG_LBAL, 0xaa);
 559
 560        nsect = read_atapi_register(base, ATA_REG_NSECT);
 561        lbal = read_atapi_register(base, ATA_REG_LBAL);
 562
 563        if ((nsect == 0x55) && (lbal == 0xaa))
 564                return 1;       /* we found a device */
 565
 566        return 0;               /* nothing found */
 567}
 568
 569/**
 570 *      bfin_bus_post_reset - PATA device post reset
 571 *
 572 *      Note: Original code is ata_bus_post_reset().
 573 */
 574
 575static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
 576{
 577        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 578        unsigned int dev0 = devmask & (1 << 0);
 579        unsigned int dev1 = devmask & (1 << 1);
 580        long deadline;
 581
 582        /* if device 0 was found in ata_devchk, wait for its
 583         * BSY bit to clear
 584         */
 585        if (dev0)
 586                bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
 587
 588        /* if device 1 was found in ata_devchk, wait for
 589         * register access, then wait for BSY to clear
 590         */
 591        deadline = ATA_TMOUT_BOOT;
 592        while (dev1) {
 593                u8 nsect, lbal;
 594
 595                bfin_dev_select(ap, 1);
 596                nsect = read_atapi_register(base, ATA_REG_NSECT);
 597                lbal = read_atapi_register(base, ATA_REG_LBAL);
 598                if ((nsect == 1) && (lbal == 1))
 599                        break;
 600                if (deadline <= 0) {
 601                        dev1 = 0;
 602                        break;
 603                }
 604                msleep(50);     /* give drive a breather */
 605                deadline -= 50;
 606        }
 607        if (dev1)
 608                bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
 609
 610        /* is all this really necessary? */
 611        bfin_dev_select(ap, 0);
 612        if (dev1)
 613                bfin_dev_select(ap, 1);
 614        if (dev0)
 615                bfin_dev_select(ap, 0);
 616}
 617
 618/**
 619 *      bfin_bus_softreset - PATA device software reset
 620 *
 621 *      Note: Original code is ata_bus_softreset().
 622 */
 623
 624static unsigned int bfin_bus_softreset(struct ata_port *ap,
 625                                       unsigned int devmask)
 626{
 627        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 628
 629        /* software reset.  causes dev0 to be selected */
 630        write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
 631        udelay(20);
 632        write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
 633        udelay(20);
 634        write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
 635
 636        /* spec mandates ">= 2ms" before checking status.
 637         * We wait 150ms, because that was the magic delay used for
 638         * ATAPI devices in Hale Landis's ATADRVR, for the period of time
 639         * between when the ATA command register is written, and then
 640         * status is checked.  Because waiting for "a while" before
 641         * checking status is fine, post SRST, we perform this magic
 642         * delay here as well.
 643         *
 644         * Old drivers/ide uses the 2mS rule and then waits for ready
 645         */
 646        msleep(150);
 647
 648        /* Before we perform post reset processing we want to see if
 649         * the bus shows 0xFF because the odd clown forgets the D7
 650         * pulldown resistor.
 651         */
 652        if (bfin_check_status(ap) == 0xFF)
 653                return 0;
 654
 655        bfin_bus_post_reset(ap, devmask);
 656
 657        return 0;
 658}
 659
 660/**
 661 *      bfin_softreset - reset host port via ATA SRST
 662 *      @ap: port to reset
 663 *
 664 *      Note: Original code is ata_sff_softreset().
 665 */
 666
 667static int bfin_softreset(struct ata_port *ap)
 668{
 669        unsigned int err_mask;
 670
 671        ap->dev_mask = 0;
 672
 673        /* determine if device 0/1 are present.
 674         * only one device is supported on one port by now.
 675        */
 676        if (bfin_devchk(ap, 0))
 677                ap->dev_mask |= (1 << 0);
 678        else if (bfin_devchk(ap, 1))
 679                ap->dev_mask |= (1 << 1);
 680        else
 681                return -ENODEV;
 682
 683        /* select device 0 again */
 684        bfin_dev_select(ap, 0);
 685
 686        /* issue bus reset */
 687        err_mask = bfin_bus_softreset(ap, ap->dev_mask);
 688        if (err_mask) {
 689                printf("SRST failed (err_mask=0x%x)\n",
 690                                err_mask);
 691                ap->dev_mask = 0;
 692                return -EIO;
 693        }
 694
 695        return 0;
 696}
 697
 698/**
 699 *      bfin_irq_clear - Clear ATAPI interrupt.
 700 *      @ap: Port associated with this ATA transaction.
 701 *
 702 *      Note: Original code is ata_sff_irq_clear().
 703 */
 704
 705static void bfin_irq_clear(struct ata_port *ap)
 706{
 707        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 708
 709        ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
 710                | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
 711                | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
 712}
 713
 714static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
 715{
 716        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 717
 718        do {
 719                if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
 720                | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
 721                | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
 722                        break;
 723                }
 724                udelay(1000);
 725                max--;
 726        } while ((max > 0));
 727
 728        return max == 0;
 729}
 730
 731/**
 732 *      bfin_ata_reset_port - initialize BFIN ATAPI port.
 733 */
 734
 735static int bfin_ata_reset_port(struct ata_port *ap)
 736{
 737        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 738        int count;
 739        unsigned short status;
 740
 741        /* Disable all ATAPI interrupts */
 742        ATAPI_SET_INT_MASK(base, 0);
 743        SSYNC();
 744
 745        /* Assert the RESET signal 25us*/
 746        ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
 747        udelay(30);
 748
 749        /* Negate the RESET signal for 2ms*/
 750        ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
 751        msleep(2);
 752
 753        /* Wait on Busy flag to clear */
 754        count = 10000000;
 755        do {
 756                status = read_atapi_register(base, ATA_REG_STATUS);
 757        } while (--count && (status & ATA_BUSY));
 758
 759        /* Enable only ATAPI Device interrupt */
 760        ATAPI_SET_INT_MASK(base, 1);
 761        SSYNC();
 762
 763        return !count;
 764}
 765
 766/**
 767 *
 768 *      Function:       bfin_config_atapi_gpio
 769 *
 770 *      Description:    Configures the ATAPI pins for use
 771 *
 772 */
 773static int bfin_config_atapi_gpio(struct ata_port *ap)
 774{
 775        const unsigned short pins[] = {
 776                P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
 777                P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
 778                P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
 779                P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
 780                P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
 781                P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
 782                P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
 783        };
 784
 785        peripheral_request_list(pins, "pata_bfin");
 786
 787        return 0;
 788}
 789
 790/**
 791 *      bfin_atapi_probe        -       attach a bfin atapi interface
 792 *      @pdev: platform device
 793 *
 794 *      Register a bfin atapi interface.
 795 *
 796 *
 797 *      Platform devices are expected to contain 2 resources per port:
 798 *
 799 *              - I/O Base (IORESOURCE_IO)
 800 *              - IRQ      (IORESOURCE_IRQ)
 801 *
 802 */
 803static int bfin_ata_probe_port(struct ata_port *ap)
 804{
 805        if (bfin_config_atapi_gpio(ap)) {
 806                printf("Requesting Peripherals faild\n");
 807                return -EFAULT;
 808        }
 809
 810        if (bfin_ata_reset_port(ap)) {
 811                printf("Fail to reset ATAPI device\n");
 812                return -EFAULT;
 813        }
 814
 815        if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
 816                bfin_set_piomode(ap, ap->ata_mode);
 817        else {
 818                printf("Given ATA data transfer mode is not supported.\n");
 819                return -EFAULT;
 820        }
 821
 822        return 0;
 823}
 824
 825#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 826
 827static void bfin_ata_identify(struct ata_port *ap, int dev)
 828{
 829        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 830        u8 status = 0;
 831        static u16 iobuf[ATA_SECTOR_WORDS];
 832        u64 n_sectors = 0;
 833        hd_driveid_t *iop = (hd_driveid_t *)iobuf;
 834
 835        memset(iobuf, 0, sizeof(iobuf));
 836
 837        if (!(ap->dev_mask & (1 << dev)))
 838                return;
 839
 840        debug("port=%d dev=%d\n", ap->port_no, dev);
 841
 842        bfin_dev_select(ap, dev);
 843
 844        status = 0;
 845        /* Device Identify Command */
 846        write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
 847        bfin_check_altstatus(ap);
 848        udelay(10);
 849
 850        status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
 851        if (status & ATA_ERR) {
 852                printf("\ndevice not responding\n");
 853                ap->dev_mask &= ~(1 << dev);
 854                return;
 855        }
 856
 857        read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
 858
 859        ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
 860
 861        /* we require LBA and DMA support (bits 8 & 9 of word 49) */
 862        if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
 863                printf("ata%u: no dma/lba\n", ap->port_no);
 864
 865#ifdef DEBUG
 866        ata_dump_id(iobuf);
 867#endif
 868
 869        n_sectors = ata_id_n_sectors(iobuf);
 870
 871        if (n_sectors == 0) {
 872                ap->dev_mask &= ~(1 << dev);
 873                return;
 874        }
 875
 876        ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
 877                         ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
 878        ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
 879                         ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
 880        ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
 881                         ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
 882
 883        if ((iop->config & 0x0080) == 0x0080)
 884                sata_dev_desc[ap->port_no].removable = 1;
 885        else
 886                sata_dev_desc[ap->port_no].removable = 0;
 887
 888        sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
 889        debug("lba=0x%lx\n", sata_dev_desc[ap->port_no].lba);
 890
 891#ifdef CONFIG_LBA48
 892        if (iop->command_set_2 & 0x0400)
 893                sata_dev_desc[ap->port_no].lba48 = 1;
 894        else
 895                sata_dev_desc[ap->port_no].lba48 = 0;
 896#endif
 897
 898        /* assuming HD */
 899        sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
 900        sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
 901        sata_dev_desc[ap->port_no].log2blksz =
 902                LOG2(sata_dev_desc[ap->port_no].blksz);
 903        sata_dev_desc[ap->port_no].lun = 0;     /* just to fill something in... */
 904
 905        printf("PATA device#%d %s is found on ata port#%d.\n",
 906                ap->port_no%PATA_DEV_NUM_PER_PORT,
 907                sata_dev_desc[ap->port_no].vendor,
 908                ap->port_no/PATA_DEV_NUM_PER_PORT);
 909}
 910
 911static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
 912{
 913        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
 914        u8 status = 0;
 915
 916        if (!(ap->dev_mask & (1 << dev)))
 917                return;
 918
 919        bfin_dev_select(ap, dev);
 920
 921        write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
 922        write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
 923        write_atapi_register(base, ATA_REG_LBAL, 0);
 924        write_atapi_register(base, ATA_REG_LBAM, 0);
 925        write_atapi_register(base, ATA_REG_LBAH, 0);
 926
 927        write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
 928        write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
 929
 930        udelay(50);
 931        msleep(150);
 932
 933        status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
 934        if ((status & (ATA_BUSY | ATA_ERR))) {
 935                printf("Error  : status 0x%02x\n", status);
 936                ap->dev_mask &= ~(1 << dev);
 937        }
 938}
 939
 940int scan_sata(int dev)
 941{
 942        /* dev is the index of each ata device in the system. one PATA port
 943         * contains 2 devices. one element in scan_done array indicates one
 944         * PATA port. device connected to one PATA port is selected by
 945         * bfin_dev_select() before access.
 946         */
 947        struct ata_port *ap = &port[dev];
 948        static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
 949
 950        if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
 951                return 0;
 952
 953        /* Check for attached device */
 954        if (!bfin_ata_probe_port(ap)) {
 955                if (bfin_softreset(ap)) {
 956                        /* soft reset failed, try a hard one */
 957                        bfin_ata_reset_port(ap);
 958                        if (bfin_softreset(ap))
 959                                scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
 960                } else {
 961                        scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
 962                }
 963        }
 964        if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
 965                /* Probe device and set xfer mode */
 966                bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
 967                bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
 968                part_init(&sata_dev_desc[dev]);
 969                return 0;
 970        }
 971
 972        printf("PATA device#%d is not present on ATA port#%d.\n",
 973                ap->port_no%PATA_DEV_NUM_PER_PORT,
 974                ap->port_no/PATA_DEV_NUM_PER_PORT);
 975
 976        return -1;
 977}
 978
 979int init_sata(int dev)
 980{
 981        struct ata_port *ap = &port[dev];
 982        static u8 init_done;
 983        int res = 1;
 984
 985        if (init_done)
 986                return res;
 987
 988        init_done = 1;
 989
 990        switch (dev/PATA_DEV_NUM_PER_PORT) {
 991        case 0:
 992                ap->ioaddr.ctl_addr = ATAPI_CONTROL;
 993                ap->ata_mode = CONFIG_BFIN_ATA_MODE;
 994                break;
 995        default:
 996                printf("Tried to scan unknown port %d.\n", dev);
 997                return res;
 998        }
 999
1000        if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
1001                ap->ata_mode = XFER_PIO_4;
1002                printf("DMA mode is not supported. Set to PIO mode 4.\n");
1003        }
1004
1005        ap->port_no = dev;
1006        ap->ctl_reg = 0x8;      /*Default value of control reg */
1007
1008        res = 0;
1009        return res;
1010}
1011
1012int reset_sata(int dev)
1013{
1014        return 0;
1015}
1016
1017/* Read up to 255 sectors
1018 *
1019 * Returns sectors read
1020*/
1021static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
1022                        uchar lba48)
1023{
1024        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1025        u8 sr = 0;
1026        u8 status;
1027        u16 err = 0;
1028
1029        if (!(bfin_check_status(ap) & ATA_DRDY)) {
1030                printf("Device ata%d not ready\n", ap->port_no);
1031                return 0;
1032        }
1033
1034        /* Set up transfer */
1035#ifdef CONFIG_LBA48
1036        if (lba48) {
1037                /* write high bits */
1038                write_atapi_register(base, ATA_REG_NSECT, 0);
1039                write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
1040                write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
1041                write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
1042        }
1043#endif
1044        write_atapi_register(base, ATA_REG_NSECT, blkcnt);
1045        write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1046        write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1047        write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1048
1049#ifdef CONFIG_LBA48
1050        if (lba48) {
1051                write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1052                write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
1053        } else
1054#endif
1055        {
1056                write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
1057                write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
1058        }
1059        status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
1060
1061        if (status & (ATA_BUSY | ATA_ERR)) {
1062                printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
1063                err = read_atapi_register(base, ATA_REG_ERR);
1064                printf("Error reg = 0x%x\n", err);
1065                return sr;
1066        }
1067
1068        while (blkcnt--) {
1069                if (bfin_wait_for_irq(ap, 500)) {
1070                        printf("ata%u irq failed\n", ap->port_no);
1071                        return sr;
1072                }
1073
1074                status = bfin_check_status(ap);
1075                if (status & ATA_ERR) {
1076                        err = read_atapi_register(base, ATA_REG_ERR);
1077                        printf("ata%u error %d\n", ap->port_no, err);
1078                        return sr;
1079                }
1080                bfin_irq_clear(ap);
1081
1082                /* Read one sector */
1083                read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1084                buffer += ATA_SECTOR_WORDS;
1085                sr++;
1086        }
1087
1088        return sr;
1089}
1090
1091ulong sata_read(int dev, ulong block, lbaint_t blkcnt, void *buff)
1092{
1093        struct ata_port *ap = &port[dev];
1094        ulong n = 0, sread;
1095        u16 *buffer = (u16 *) buff;
1096        u8 status = 0;
1097        u64 blknr = (u64) block;
1098        unsigned char lba48 = 0;
1099
1100#ifdef CONFIG_LBA48
1101        if (blknr > 0xfffffff) {
1102                if (!sata_dev_desc[dev].lba48) {
1103                        printf("Drive doesn't support 48-bit addressing\n");
1104                        return 0;
1105                }
1106                /* more than 28 bits used, use 48bit mode */
1107                lba48 = 1;
1108        }
1109#endif
1110        bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1111
1112        while (blkcnt > 0) {
1113
1114                if (blkcnt > 255)
1115                        sread = 255;
1116                else
1117                        sread = blkcnt;
1118
1119                status = do_one_read(ap, blknr, sread, buffer, lba48);
1120                if (status != sread) {
1121                        printf("Read failed\n");
1122                        return n;
1123                }
1124
1125                blkcnt -= sread;
1126                blknr += sread;
1127                n += sread;
1128                buffer += sread * ATA_SECTOR_WORDS;
1129        }
1130        return n;
1131}
1132
1133ulong sata_write(int dev, ulong block, lbaint_t blkcnt, const void *buff)
1134{
1135        struct ata_port *ap = &port[dev];
1136        void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1137        ulong n = 0;
1138        u16 *buffer = (u16 *) buff;
1139        unsigned char status = 0;
1140        u64 blknr = (u64) block;
1141#ifdef CONFIG_LBA48
1142        unsigned char lba48 = 0;
1143
1144        if (blknr > 0xfffffff) {
1145                if (!sata_dev_desc[dev].lba48) {
1146                        printf("Drive doesn't support 48-bit addressing\n");
1147                        return 0;
1148                }
1149                /* more than 28 bits used, use 48bit mode */
1150                lba48 = 1;
1151        }
1152#endif
1153
1154        bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1155
1156        while (blkcnt-- > 0) {
1157                status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1158                if (status & ATA_BUSY) {
1159                        printf("ata%u failed to respond\n", ap->port_no);
1160                        return n;
1161                }
1162#ifdef CONFIG_LBA48
1163                if (lba48) {
1164                        /* write high bits */
1165                        write_atapi_register(base, ATA_REG_NSECT, 0);
1166                        write_atapi_register(base, ATA_REG_LBAL,
1167                                (blknr >> 24) & 0xFF);
1168                        write_atapi_register(base, ATA_REG_LBAM,
1169                                (blknr >> 32) & 0xFF);
1170                        write_atapi_register(base, ATA_REG_LBAH,
1171                                (blknr >> 40) & 0xFF);
1172                }
1173#endif
1174                write_atapi_register(base, ATA_REG_NSECT, 1);
1175                write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1176                write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1177                write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1178#ifdef CONFIG_LBA48
1179                if (lba48) {
1180                        write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1181                        write_atapi_register(base, ATA_REG_CMD,
1182                                ATA_CMD_PIO_WRITE_EXT);
1183                } else
1184#endif
1185                {
1186                        write_atapi_register(base, ATA_REG_DEVICE,
1187                                ATA_LBA | ((blknr >> 24) & 0xF));
1188                        write_atapi_register(base, ATA_REG_CMD,
1189                                ATA_CMD_PIO_WRITE);
1190                }
1191
1192                /*may take up to 5 sec */
1193                status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1194                if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
1195                        printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
1196                                ap->port_no, (ulong) blknr, status);
1197                        return n;
1198                }
1199
1200                write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1201                bfin_check_altstatus(ap);
1202                udelay(1);
1203
1204                ++n;
1205                ++blknr;
1206                buffer += ATA_SECTOR_WORDS;
1207        }
1208        return n;
1209}
1210