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11#include <common.h>
12#include <errno.h>
13#include <malloc.h>
14#include <mmc.h>
15#include <sdhci.h>
16#include <wait_bit.h>
17
18#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
19void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
20#else
21void *aligned_buffer;
22#endif
23
24static void sdhci_reset(struct sdhci_host *host, u8 mask)
25{
26 unsigned long timeout;
27
28
29 timeout = 100;
30 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
31 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
32 if (timeout == 0) {
33 printf("%s: Reset 0x%x never completed.\n",
34 __func__, (int)mask);
35 return;
36 }
37 timeout--;
38 udelay(1000);
39 }
40}
41
42static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
43{
44 int i;
45 if (cmd->resp_type & MMC_RSP_136) {
46
47 for (i = 0; i < 4; i++) {
48 cmd->response[i] = sdhci_readl(host,
49 SDHCI_RESPONSE + (3-i)*4) << 8;
50 if (i != 3)
51 cmd->response[i] |= sdhci_readb(host,
52 SDHCI_RESPONSE + (3-i)*4-1);
53 }
54 } else {
55 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
56 }
57}
58
59static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
60{
61 int i;
62 char *offs;
63 for (i = 0; i < data->blocksize; i += 4) {
64 offs = data->dest + i;
65 if (data->flags == MMC_DATA_READ)
66 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
67 else
68 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
69 }
70}
71
72static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
73 unsigned int start_addr)
74{
75 unsigned int stat, rdy, mask, timeout, block = 0;
76#ifdef CONFIG_MMC_SDHCI_SDMA
77 unsigned char ctrl;
78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
79 ctrl &= ~SDHCI_CTRL_DMA_MASK;
80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
81#endif
82
83 timeout = 1000000;
84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
86 do {
87 stat = sdhci_readl(host, SDHCI_INT_STATUS);
88 if (stat & SDHCI_INT_ERROR) {
89 printf("%s: Error detected in status(0x%X)!\n",
90 __func__, stat);
91 return -EIO;
92 }
93 if (stat & rdy) {
94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
95 continue;
96 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
97 sdhci_transfer_pio(host, data);
98 data->dest += data->blocksize;
99 if (++block >= data->blocks)
100 break;
101 }
102#ifdef CONFIG_MMC_SDHCI_SDMA
103 if (stat & SDHCI_INT_DMA_END) {
104 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
105 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
106 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
107 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
108 }
109#endif
110 if (timeout-- > 0)
111 udelay(10);
112 else {
113 printf("%s: Transfer data timeout\n", __func__);
114 return -ETIMEDOUT;
115 }
116 } while (!(stat & SDHCI_INT_DATA_END));
117 return 0;
118}
119
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121
122
123
124
125
126
127#define SDHCI_CMD_MAX_TIMEOUT 3200
128#define SDHCI_CMD_DEFAULT_TIMEOUT 100
129#define SDHCI_READ_STATUS_TIMEOUT 1000
130
131#ifdef CONFIG_DM_MMC_OPS
132static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
133 struct mmc_data *data)
134{
135 struct mmc *mmc = mmc_get_mmc_dev(dev);
136
137#else
138static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
139 struct mmc_data *data)
140{
141#endif
142 struct sdhci_host *host = mmc->priv;
143 unsigned int stat = 0;
144 int ret = 0;
145 int trans_bytes = 0, is_aligned = 1;
146 u32 mask, flags, mode;
147 unsigned int time = 0, start_addr = 0;
148 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
149 unsigned start = get_timer(0);
150
151
152 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
153
154 if (((host->last_cmd == MMC_CMD_WRITE_MULTIPLE_BLOCK) ||
155 (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)) &&
156 (host->quirks & SDHCI_QUIRK_USE_ACMD12) &&
157 (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION))
158 return 0;
159
160 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
161 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
162
163
164
165 if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) ||
166 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
167 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
168 mask &= ~SDHCI_DATA_INHIBIT;
169
170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
171 if (time >= cmd_timeout) {
172 printf("%s: MMC: %d busy ", __func__, mmc_dev);
173 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
174 cmd_timeout += cmd_timeout;
175 printf("timeout increasing to: %u ms.\n",
176 cmd_timeout);
177 } else {
178 puts("timeout.\n");
179 return -ECOMM;
180 }
181 }
182 time++;
183 udelay(1000);
184 }
185
186 mask = SDHCI_INT_RESPONSE;
187
188
189 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
190 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
191 mask = SDHCI_INT_DATA_AVAIL;
192
193 if (!(cmd->resp_type & MMC_RSP_PRESENT))
194 flags = SDHCI_CMD_RESP_NONE;
195 else if (cmd->resp_type & MMC_RSP_136)
196 flags = SDHCI_CMD_RESP_LONG;
197 else if (cmd->resp_type & MMC_RSP_BUSY) {
198 flags = SDHCI_CMD_RESP_SHORT_BUSY;
199 if (data)
200 mask |= SDHCI_INT_DATA_END;
201 } else
202 flags = SDHCI_CMD_RESP_SHORT;
203
204 if (cmd->resp_type & MMC_RSP_CRC)
205 flags |= SDHCI_CMD_CRC;
206 if (cmd->resp_type & MMC_RSP_OPCODE)
207 flags |= SDHCI_CMD_INDEX;
208 if (data || (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
209 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
210 flags |= SDHCI_CMD_DATA;
211
212 host->last_cmd = cmd->cmdidx;
213
214
215 if (data != 0) {
216 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
217 mode = SDHCI_TRNS_BLK_CNT_EN;
218 trans_bytes = data->blocks * data->blocksize;
219 if (data->blocks > 1)
220 mode |= SDHCI_TRNS_MULTI;
221
222 if (((cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK) ||
223 (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)) &&
224 (host->quirks & SDHCI_QUIRK_USE_ACMD12))
225 mode |= SDHCI_TRNS_ACMD12;
226
227 if (data->flags == MMC_DATA_READ)
228 mode |= SDHCI_TRNS_READ;
229
230#ifdef CONFIG_MMC_SDHCI_SDMA
231 if (data->flags == MMC_DATA_READ)
232 start_addr = (unsigned long)data->dest;
233 else
234 start_addr = (unsigned long)data->src;
235 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
236 (start_addr & 0x7) != 0x0) {
237 is_aligned = 0;
238 start_addr = (unsigned long)aligned_buffer;
239 if (data->flags != MMC_DATA_READ)
240 memcpy(aligned_buffer, data->src, trans_bytes);
241 }
242
243#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
244
245
246
247
248 is_aligned = 0;
249 start_addr = (unsigned long)aligned_buffer;
250 if (data->flags != MMC_DATA_READ)
251 memcpy(aligned_buffer, data->src, trans_bytes);
252#endif
253
254 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
255 mode |= SDHCI_TRNS_DMA;
256#endif
257 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
258 data->blocksize),
259 SDHCI_BLOCK_SIZE);
260 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
261 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
262 } else if (cmd->resp_type & MMC_RSP_BUSY) {
263 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
264 }
265
266 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
267#ifdef CONFIG_MMC_SDHCI_SDMA
268 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
269 flush_cache(start_addr, trans_bytes);
270#endif
271 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
272 start = get_timer(0);
273 do {
274 stat = sdhci_readl(host, SDHCI_INT_STATUS);
275 if (stat & SDHCI_INT_ERROR)
276 break;
277
278 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
279 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
280 return 0;
281 } else {
282 printf("%s: Timeout for status update!\n",
283 __func__);
284 return -ETIMEDOUT;
285 }
286 }
287 } while ((stat & mask) != mask);
288
289 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
290 sdhci_cmd_done(host, cmd);
291 sdhci_writel(host, mask, SDHCI_INT_STATUS);
292 } else
293 ret = -1;
294
295 if (!ret && data)
296 ret = sdhci_transfer_data(host, data, start_addr);
297
298 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
299 udelay(1000);
300
301 stat = sdhci_readl(host, SDHCI_INT_STATUS);
302 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
303 if (!ret) {
304 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
305 !is_aligned && (data->flags == MMC_DATA_READ))
306 memcpy(data->dest, aligned_buffer, trans_bytes);
307 return 0;
308 }
309
310 sdhci_reset(host, SDHCI_RESET_CMD);
311 sdhci_reset(host, SDHCI_RESET_DATA);
312 if (stat & SDHCI_INT_TIMEOUT)
313 return -ETIMEDOUT;
314 else
315 return -ECOMM;
316}
317#ifdef CONFIG_DM_MMC_OPS
318static int sdhci_execute_tuning(struct udevice *dev, u8 opcode)
319{
320 struct mmc *mmc = mmc_get_mmc_dev(dev);
321#else
322static int sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
323{
324#endif
325 struct mmc_cmd cmd;
326 struct mmc_data data;
327 u32 ctrl;
328 int err;
329 u8 tuning_loop_counter = 40;
330 struct sdhci_host *host = mmc->priv;
331
332 debug("%s\n", __func__);
333
334 if (host->platform_execute_tuning) {
335 err = host->platform_execute_tuning(mmc, opcode);
336 if (err)
337 return err;
338 return 0;
339 }
340
341 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
342 ctrl |= SDHCI_CTRL_EXEC_TUNING;
343 sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
344
345 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
346 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
347
348 do {
349 cmd.cmdidx = opcode;
350 cmd.resp_type = MMC_RSP_R1;
351 cmd.cmdarg = 0;
352
353 data.blocksize = 64;
354 data.blocks = 1;
355 data.flags = MMC_DATA_READ;
356
357 if (tuning_loop_counter == 0)
358 break;
359
360 tuning_loop_counter--;
361
362 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
363 mmc->bus_width == 8) {
364 data.blocksize = 128;
365 }
366
367 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
368 data.blocksize),
369 SDHCI_BLOCK_SIZE);
370 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
371 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
372
373 sdhci_send_command(dev, &cmd, &data);
374 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
375
376 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
377 udelay(1);
378
379 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
380
381 if (tuning_loop_counter < 0) {
382 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
383 sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
384 }
385
386 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
387 debug("%s:Tuning failed\n", __func__);
388 return -1;
389 }
390
391
392 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
393 SDHCI_INT_ENABLE);
394
395 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
396
397 return 0;
398}
399
400static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
401{
402 struct sdhci_host *host = mmc->priv;
403 unsigned int div, clk = 0, timeout, reg;
404
405
406 timeout = 200;
407 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
408 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
409 if (timeout == 0) {
410 printf("%s: Timeout to wait cmd & data inhibit\n",
411 __func__);
412 return -EBUSY;
413 }
414
415 timeout--;
416 udelay(100);
417 }
418
419 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
420 reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
421 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
422
423 if (clock == 0)
424 return 0;
425
426 if (host->set_delay)
427 host->set_delay(host);
428
429 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
430
431
432
433
434 if (host->clk_mul) {
435 for (div = 1; div <= 1024; div++) {
436 if ((mmc->cfg->f_max * host->clk_mul / div)
437 <= clock)
438 break;
439 }
440
441
442
443
444
445 clk = SDHCI_PROG_CLOCK_MODE;
446 div--;
447 } else {
448
449 if (mmc->cfg->f_max <= clock) {
450 div = 1;
451 } else {
452 for (div = 2;
453 div < SDHCI_MAX_DIV_SPEC_300;
454 div += 2) {
455 if ((mmc->cfg->f_max / div) <= clock)
456 break;
457 }
458 }
459 div >>= 1;
460 }
461 } else {
462
463 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
464 if ((mmc->cfg->f_max / div) <= clock)
465 break;
466 }
467 div >>= 1;
468 }
469
470 if (host->set_clock)
471 host->set_clock(host->index, div);
472
473 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
474 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
475 << SDHCI_DIVIDER_HI_SHIFT;
476 clk |= SDHCI_CLOCK_INT_EN;
477 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
478
479
480 timeout = 20;
481 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
482 & SDHCI_CLOCK_INT_STABLE)) {
483 if (timeout == 0) {
484 printf("%s: Internal clock never stabilised.\n",
485 __func__);
486 return -EBUSY;
487 }
488 timeout--;
489 udelay(1000);
490 }
491
492 clk |= SDHCI_CLOCK_CARD_EN;
493 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
494 return 0;
495}
496
497#ifdef CONFIG_DM_MMC_OPS
498static int sdhci_set_voltage(struct udevice *dev)
499{
500 struct mmc *mmc = mmc_get_mmc_dev(dev);
501#else
502static int sdhci_set_voltage(struct mmc *mmc)
503{
504#endif
505 struct sdhci_host *host = mmc->priv;
506 u32 reg;
507 int err;
508
509 debug("%s\n", __func__);
510
511 reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
512
513 err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
514 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT),
515 false, 20, false);
516 if (err < 0)
517 return err;
518
519 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
520 reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
521 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
522
523
524 udelay(5000);
525
526 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
527 reg |= SDHCI_18V_SIGNAL;
528 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
529
530 sdhci_set_clock(mmc, mmc->cfg->f_min);
531
532 reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
533
534 err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
535 (SDHCI_CMD_BUSY | SDHCI_DATA_BUSY),
536 true, 20, false);
537 if (err < 0)
538 return err;
539
540 return 0;
541}
542
543#ifdef CONFIG_DM_MMC_OPS
544static int sdhci_set_uhs(struct udevice *dev)
545{
546 struct mmc *mmc = mmc_get_mmc_dev(dev);
547#else
548static int sdhci_set_uhs(struct mmc *mmc)
549{
550#endif
551 struct sdhci_host *host = mmc->priv;
552 u32 reg;
553
554 debug("%s\n", __func__);
555 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
556 reg &= ~SDHCI_CTRL2_MODE_MASK;
557 reg |= mmc->uhsmode;
558 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
559
560 return 0;
561}
562
563static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
564{
565 u8 pwr = 0;
566
567 if (power != (unsigned short)-1) {
568 switch (1 << power) {
569 case MMC_VDD_165_195:
570 pwr = SDHCI_POWER_180;
571 break;
572 case MMC_VDD_29_30:
573 case MMC_VDD_30_31:
574 pwr = SDHCI_POWER_300;
575 break;
576 case MMC_VDD_32_33:
577 case MMC_VDD_33_34:
578 pwr = SDHCI_POWER_330;
579 break;
580 }
581 }
582
583 if (pwr == 0) {
584 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
585 return;
586 }
587
588 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
589 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
590
591 pwr |= SDHCI_POWER_ON;
592
593 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
594}
595
596#ifdef CONFIG_DM_MMC_OPS
597static int sdhci_set_ios(struct udevice *dev)
598{
599 struct mmc *mmc = mmc_get_mmc_dev(dev);
600#else
601static void sdhci_set_ios(struct mmc *mmc)
602{
603#endif
604 u32 ctrl;
605 struct sdhci_host *host = mmc->priv;
606
607 if (host->set_control_reg)
608 host->set_control_reg(host);
609
610 if (mmc->clock != host->clock)
611 sdhci_set_clock(mmc, mmc->clock);
612
613
614 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
615 if (mmc->bus_width == 8) {
616 ctrl &= ~SDHCI_CTRL_4BITBUS;
617 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
618 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
619 ctrl |= SDHCI_CTRL_8BITBUS;
620 } else {
621 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
622 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
623 ctrl &= ~SDHCI_CTRL_8BITBUS;
624 if (mmc->bus_width == 4)
625 ctrl |= SDHCI_CTRL_4BITBUS;
626 else
627 ctrl &= ~SDHCI_CTRL_4BITBUS;
628 }
629
630 if (mmc->clock > 26000000)
631 ctrl |= SDHCI_CTRL_HISPD;
632 else
633 ctrl &= ~SDHCI_CTRL_HISPD;
634
635 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
636 ctrl &= ~SDHCI_CTRL_HISPD;
637
638 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
639#ifdef CONFIG_DM_MMC_OPS
640 return 0;
641#endif
642}
643
644static int sdhci_init(struct mmc *mmc)
645{
646 struct sdhci_host *host = mmc->priv;
647
648 sdhci_reset(host, SDHCI_RESET_ALL);
649
650 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
651 aligned_buffer = memalign(8, 512*1024);
652 if (!aligned_buffer) {
653 printf("%s: Aligned buffer alloc failed!!!\n",
654 __func__);
655 return -ENOMEM;
656 }
657 }
658
659 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
660
661 if (host->quirks & SDHCI_QUIRK_NO_CD) {
662#if defined(CONFIG_PIC32_SDHCI)
663
664
665
666 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
667#else
668 unsigned int status;
669
670 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
671 SDHCI_HOST_CONTROL);
672
673 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
674 while ((!(status & SDHCI_CARD_PRESENT)) ||
675 (!(status & SDHCI_CARD_STATE_STABLE)) ||
676 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
677 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
678#endif
679 }
680
681
682 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
683 SDHCI_INT_ENABLE);
684
685 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
686
687 return 0;
688}
689
690#ifdef CONFIG_DM_MMC_OPS
691int sdhci_probe(struct udevice *dev)
692{
693 struct mmc *mmc = mmc_get_mmc_dev(dev);
694
695 return sdhci_init(mmc);
696}
697
698const struct dm_mmc_ops sdhci_ops = {
699 .send_cmd = sdhci_send_command,
700 .set_ios = sdhci_set_ios,
701 .set_voltage = sdhci_set_voltage,
702 .set_uhs = sdhci_set_uhs,
703 .execute_tuning = sdhci_execute_tuning,
704};
705#else
706static const struct mmc_ops sdhci_ops = {
707 .send_cmd = sdhci_send_command,
708 .set_ios = sdhci_set_ios,
709 .init = sdhci_init,
710 .set_voltage = sdhci_set_voltage,
711 .set_uhs = sdhci_set_uhs,
712 .execute_tuning = sdhci_execute_tuning,
713};
714#endif
715
716int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
717 u32 max_clk, u32 min_clk)
718{
719 u32 caps;
720 u32 caps_1 = 0;
721
722 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
723
724#ifdef CONFIG_MMC_SDHCI_SDMA
725 if (!(caps & SDHCI_CAN_DO_SDMA)) {
726 printf("%s: Your controller doesn't support SDMA!!\n",
727 __func__);
728 return -EINVAL;
729 }
730#endif
731 if (host->quirks & SDHCI_QUIRK_REG32_RW)
732 host->version =
733 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
734 else
735 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
736
737 cfg->name = host->name;
738#ifndef CONFIG_DM_MMC_OPS
739 cfg->ops = &sdhci_ops;
740#endif
741 if (max_clk)
742 cfg->f_max = max_clk;
743 else {
744 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
745 cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
746 SDHCI_CLOCK_BASE_SHIFT;
747 else
748 cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
749 SDHCI_CLOCK_BASE_SHIFT;
750 cfg->f_max *= 1000000;
751 }
752 if (cfg->f_max == 0) {
753 printf("%s: Hardware doesn't specify base clock frequency\n",
754 __func__);
755 return -EINVAL;
756 }
757 if (min_clk)
758 cfg->f_min = min_clk;
759 else {
760 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
761 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
762 else
763 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
764 }
765 cfg->voltages = 0;
766 if (caps & SDHCI_CAN_VDD_330)
767 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
768 if (caps & SDHCI_CAN_VDD_300)
769 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
770 if (caps & SDHCI_CAN_VDD_180)
771 cfg->voltages |= MMC_VDD_165_195;
772
773 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
774 cfg->voltages |= host->voltages;
775
776 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
777 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
778 if (caps & SDHCI_CAN_DO_8BIT)
779 cfg->host_caps |= MMC_MODE_8BIT;
780 }
781
782 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
783 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
784
785 if (!(cfg->voltages & MMC_VDD_165_195) ||
786 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
787 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
788 SDHCI_SUPPORT_DDR50);
789
790 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
791 SDHCI_SUPPORT_DDR50))
792 cfg->host_caps |= MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25;
793
794 if (caps_1 & SDHCI_SUPPORT_SDR104) {
795 cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
796
797
798
799
800 cfg->host_caps |= MMC_MODE_HS200;
801 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
802 cfg->host_caps |= MMC_MODE_UHS_SDR50;
803 }
804
805 if (caps_1 & SDHCI_SUPPORT_DDR50)
806 cfg->host_caps |= MMC_MODE_UHS_DDR50;
807
808 if (caps_1 & SDHCI_USE_SDR50_TUNING)
809 cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
810
811 if (host->host_caps)
812 cfg->host_caps |= host->host_caps;
813
814 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
815
816
817
818
819
820 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
821 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
822 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
823 SDHCI_CLOCK_MUL_SHIFT;
824 }
825
826 return 0;
827}
828
829#ifdef CONFIG_BLK
830int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
831{
832 return mmc_bind(dev, mmc, cfg);
833}
834#else
835int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
836{
837 int ret;
838
839 ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
840 if (ret)
841 return ret;
842
843 host->mmc = mmc_create(&host->cfg, host);
844 if (host->mmc == NULL) {
845 printf("%s: mmc create fail!\n", __func__);
846 return -ENOMEM;
847 }
848
849 return 0;
850}
851#endif
852
