LXR uboot/drivers/net/davinci

   1/*
   2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
   3 *
   4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5 *
   6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
   7 * follows:
   8 *
   9 * ----------------------------------------------------------------------------
  10 *
  11 * dm644x_emac.c
  12 *
  13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  14 *
  15 * Copyright (C) 2005 Texas Instruments.
  16 *
  17 * ----------------------------------------------------------------------------
  18 *
  19 * SPDX-License-Identifier:     GPL-2.0+
  20 *
  21 * Modifications:
  22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  23 * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  24 */
  25#include <common.h>
  26#include <command.h>
  27#include <net.h>
  28#include <miiphy.h>
  29#include <malloc.h>
  30#include <netdev.h>
  31#include <linux/compiler.h>
  32#include <asm/arch/emac_defs.h>
  33#include <asm/io.h>
  34#include "davinci_emac.h"
  35
  36unsigned int    emac_dbg = 0;
  37#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  38
  39#ifdef EMAC_HW_RAM_ADDR
  40static inline unsigned long BD_TO_HW(unsigned long x)
  41{
  42        if (x == 0)
  43                return 0;
  44
  45        return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
  46}
  47
  48static inline unsigned long HW_TO_BD(unsigned long x)
  49{
  50        if (x == 0)
  51                return 0;
  52
  53        return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
  54}
  55#else
  56#define BD_TO_HW(x)     (x)
  57#define HW_TO_BD(x)     (x)
  58#endif
  59
  60#ifdef DAVINCI_EMAC_GIG_ENABLE
  61#define emac_gigabit_enable(phy_addr)   davinci_eth_gigabit_enable(phy_addr)
  62#else
  63#define emac_gigabit_enable(phy_addr)   /* no gigabit to enable */
  64#endif
  65
  66#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  67#define CONFIG_SYS_EMAC_TI_CLKDIV       ((EMAC_MDIO_BUS_FREQ / \
  68                EMAC_MDIO_CLOCK_FREQ) - 1)
  69#endif
  70
  71static void davinci_eth_mdio_enable(void);
  72
  73static int gen_init_phy(int phy_addr);
  74static int gen_is_phy_connected(int phy_addr);
  75static int gen_get_link_speed(int phy_addr);
  76static int gen_auto_negotiate(int phy_addr);
  77
  78void eth_mdio_enable(void)
  79{
  80        davinci_eth_mdio_enable();
  81}
  82
  83/* EMAC Addresses */
  84static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  85static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  86static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  87
  88/* EMAC descriptors */
  89static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  90static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  91static volatile emac_desc       *emac_rx_active_head = 0;
  92static volatile emac_desc       *emac_rx_active_tail = 0;
  93static int                      emac_rx_queue_active = 0;
  94
  95/* Receive packet buffers */
  96static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
  97                                __aligned(ARCH_DMA_MINALIGN);
  98
  99#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 100#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT       3
 101#endif
 102
 103/* PHY address for a discovered PHY (0xff - not found) */
 104static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 105
 106/* number of PHY found active */
 107static u_int8_t num_phy;
 108
 109phy_t                           phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 110
 111static int davinci_eth_set_mac_addr(struct eth_device *dev)
 112{
 113        unsigned long           mac_hi;
 114        unsigned long           mac_lo;
 115
 116        /*
 117         * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
 118         * receive)
 119         *  Using channel 0 only - other channels are disabled
 120         *  */
 121        writel(0, &adap_emac->MACINDEX);
 122        mac_hi = (dev->enetaddr[3] << 24) |
 123                 (dev->enetaddr[2] << 16) |
 124                 (dev->enetaddr[1] << 8)  |
 125                 (dev->enetaddr[0]);
 126        mac_lo = (dev->enetaddr[5] << 8) |
 127                 (dev->enetaddr[4]);
 128
 129        writel(mac_hi, &adap_emac->MACADDRHI);
 130#if defined(DAVINCI_EMAC_VERSION2)
 131        writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
 132               &adap_emac->MACADDRLO);
 133#else
 134        writel(mac_lo, &adap_emac->MACADDRLO);
 135#endif
 136
 137        writel(0, &adap_emac->MACHASH1);
 138        writel(0, &adap_emac->MACHASH2);
 139
 140        /* Set source MAC address - REQUIRED */
 141        writel(mac_hi, &adap_emac->MACSRCADDRHI);
 142        writel(mac_lo, &adap_emac->MACSRCADDRLO);
 143
 144
 145        return 0;
 146}
 147
 148static void davinci_eth_mdio_enable(void)
 149{
 150        u_int32_t       clkdiv;
 151
 152        clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 153
 154        writel((clkdiv & 0xff) |
 155               MDIO_CONTROL_ENABLE |
 156               MDIO_CONTROL_FAULT |
 157               MDIO_CONTROL_FAULT_ENABLE,
 158               &adap_mdio->CONTROL);
 159
 160        while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
 161                ;
 162}
 163
 164/*
 165 * Tries to find an active connected PHY. Returns 1 if address if found.
 166 * If no active PHY (or more than one PHY) found returns 0.
 167 * Sets active_phy_addr variable.
 168 */
 169static int davinci_eth_phy_detect(void)
 170{
 171        u_int32_t       phy_act_state;
 172        int             i;
 173        int             j;
 174        unsigned int    count = 0;
 175
 176        for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
 177                active_phy_addr[i] = 0xff;
 178
 179        udelay(1000);
 180        phy_act_state = readl(&adap_mdio->ALIVE);
 181
 182        if (phy_act_state == 0)
 183                return 0;               /* No active PHYs */
 184
 185        debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
 186
 187        for (i = 0, j = 0; i < 32; i++)
 188                if (phy_act_state & (1 << i)) {
 189                        count++;
 190                        if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
 191                                active_phy_addr[j++] = i;
 192                        } else {
 193                                printf("%s: to many PHYs detected.\n",
 194                                        __func__);
 195                                count = 0;
 196                                break;
 197                        }
 198                }
 199
 200        num_phy = count;
 201
 202        return count;
 203}
 204
 205
 206/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
 207int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
 208{
 209        int     tmp;
 210
 211        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 212                ;
 213
 214        writel(MDIO_USERACCESS0_GO |
 215               MDIO_USERACCESS0_WRITE_READ |
 216               ((reg_num & 0x1f) << 21) |
 217               ((phy_addr & 0x1f) << 16),
 218               &adap_mdio->USERACCESS0);
 219
 220        /* Wait for command to complete */
 221        while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
 222                ;
 223
 224        if (tmp & MDIO_USERACCESS0_ACK) {
 225                *data = tmp & 0xffff;
 226                return 1;
 227        }
 228
 229        return 0;
 230}
 231
 232/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
 233int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 234{
 235
 236        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 237                ;
 238
 239        writel(MDIO_USERACCESS0_GO |
 240               MDIO_USERACCESS0_WRITE_WRITE |
 241               ((reg_num & 0x1f) << 21) |
 242               ((phy_addr & 0x1f) << 16) |
 243               (data & 0xffff),
 244               &adap_mdio->USERACCESS0);
 245
 246        /* Wait for command to complete */
 247        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 248                ;
 249
 250        return 1;
 251}
 252
 253/* PHY functions for a generic PHY */
 254static int gen_init_phy(int phy_addr)
 255{
 256        int     ret = 1;
 257
 258        if (gen_get_link_speed(phy_addr)) {
 259                /* Try another time */
 260                ret = gen_get_link_speed(phy_addr);
 261        }
 262
 263        return(ret);
 264}
 265
 266static int gen_is_phy_connected(int phy_addr)
 267{
 268        u_int16_t       dummy;
 269
 270        return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
 271}
 272
 273static int get_active_phy(void)
 274{
 275        int i;
 276
 277        for (i = 0; i < num_phy; i++)
 278                if (phy[i].get_link_speed(active_phy_addr[i]))
 279                        return i;
 280
 281        return -1;      /* Return error if no link */
 282}
 283
 284static int gen_get_link_speed(int phy_addr)
 285{
 286        u_int16_t       tmp;
 287
 288        if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
 289                        (tmp & 0x04)) {
 290#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 291                defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 292                davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
 293
 294                /* Speed doesn't matter, there is no setting for it in EMAC. */
 295                if (tmp & (LPA_100FULL | LPA_10FULL)) {
 296                        /* set EMAC for Full Duplex  */
 297                        writel(EMAC_MACCONTROL_MIIEN_ENABLE |
 298                                        EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
 299                                        &adap_emac->MACCONTROL);
 300                } else {
 301                        /*set EMAC for Half Duplex  */
 302                        writel(EMAC_MACCONTROL_MIIEN_ENABLE,
 303                                        &adap_emac->MACCONTROL);
 304                }
 305
 306                if (tmp & (LPA_100FULL | LPA_100HALF))
 307                        writel(readl(&adap_emac->MACCONTROL) |
 308                                        EMAC_MACCONTROL_RMIISPEED_100,
 309                                         &adap_emac->MACCONTROL);
 310                else
 311                        writel(readl(&adap_emac->MACCONTROL) &
 312                                        ~EMAC_MACCONTROL_RMIISPEED_100,
 313                                         &adap_emac->MACCONTROL);
 314#endif
 315                return(1);
 316        }
 317
 318        return(0);
 319}
 320
 321static int gen_auto_negotiate(int phy_addr)
 322{
 323        u_int16_t       tmp;
 324        u_int16_t       val;
 325        unsigned long   cntr = 0;
 326
 327        if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 328                return 0;
 329
 330        val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
 331                                                BMCR_SPEED100;
 332        davinci_eth_phy_write(phy_addr, MII_BMCR, val);
 333
 334        if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
 335                return 0;
 336
 337        val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
 338                                                        ADVERTISE_10HALF);
 339        davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
 340
 341        if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 342                return(0);
 343
 344        /* Restart Auto_negotiation  */
 345        tmp |= BMCR_ANRESTART;
 346        davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
 347
 348        /*check AutoNegotiate complete */
 349        do {
 350                udelay(40000);
 351                if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 352                        return 0;
 353
 354                if (tmp & BMSR_ANEGCOMPLETE)
 355                        break;
 356
 357                cntr++;
 358        } while (cntr < 200);
 359
 360        if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 361                return(0);
 362
 363        if (!(tmp & BMSR_ANEGCOMPLETE))
 364                return(0);
 365
 366        return(gen_get_link_speed(phy_addr));
 367}
 368/* End of generic PHY functions */
 369
 370
 371#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 372static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
 373                                int reg)
 374{
 375        unsigned short value = 0;
 376        int retval = davinci_eth_phy_read(addr, reg, &value);
 377
 378        return retval ? value : -EIO;
 379}
 380
 381static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
 382                                 int reg, u16 value)
 383{
 384        return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
 385}
 386#endif
 387
 388static void  __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
 389{
 390        u_int16_t data;
 391
 392        if (davinci_eth_phy_read(phy_addr, 0, &data)) {
 393                if (data & (1 << 6)) { /* speed selection MSB */
 394                        /*
 395                         * Check if link detected is giga-bit
 396                         * If Gigabit mode detected, enable gigbit in MAC
 397                         */
 398                        writel(readl(&adap_emac->MACCONTROL) |
 399                                EMAC_MACCONTROL_GIGFORCE |
 400                                EMAC_MACCONTROL_GIGABIT_ENABLE,
 401                                &adap_emac->MACCONTROL);
 402                }
 403        }
 404}
 405
 406/* Eth device open */
 407static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 408{
 409        dv_reg_p                addr;
 410        u_int32_t               clkdiv, cnt;
 411        volatile emac_desc      *rx_desc;
 412        int                     index;
 413
 414        debug_emac("+ emac_open\n");
 415
 416        /* Reset EMAC module and disable interrupts in wrapper */
 417        writel(1, &adap_emac->SOFTRESET);
 418        while (readl(&adap_emac->SOFTRESET) != 0)
 419                ;
 420#if defined(DAVINCI_EMAC_VERSION2)
 421        writel(1, &adap_ewrap->softrst);
 422        while (readl(&adap_ewrap->softrst) != 0)
 423                ;
 424#else
 425        writel(0, &adap_ewrap->EWCTL);
 426        for (cnt = 0; cnt < 5; cnt++) {
 427                clkdiv = readl(&adap_ewrap->EWCTL);
 428        }
 429#endif
 430
 431#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 432        defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 433        adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 434        adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 435        adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 436#endif
 437        rx_desc = emac_rx_desc;
 438
 439        writel(1, &adap_emac->TXCONTROL);
 440        writel(1, &adap_emac->RXCONTROL);
 441
 442        davinci_eth_set_mac_addr(dev);
 443
 444        /* Set DMA 8 TX / 8 RX Head pointers to 0 */
 445        addr = &adap_emac->TX0HDP;
 446        for (cnt = 0; cnt < 8; cnt++)
 447                writel(0, addr++);
 448
 449        addr = &adap_emac->RX0HDP;
 450        for (cnt = 0; cnt < 8; cnt++)
 451                writel(0, addr++);
 452
 453        /* Clear Statistics (do this before setting MacControl register) */
 454        addr = &adap_emac->RXGOODFRAMES;
 455        for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
 456                writel(0, addr++);
 457
 458        /* No multicast addressing */
 459        writel(0, &adap_emac->MACHASH1);
 460        writel(0, &adap_emac->MACHASH2);
 461
 462        /* Create RX queue and set receive process in place */
 463        emac_rx_active_head = emac_rx_desc;
 464        for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
 465                rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
 466                rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
 467                rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 468                rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 469                rx_desc++;
 470        }
 471
 472        /* Finalize the rx desc list */
 473        rx_desc--;
 474        rx_desc->next = 0;
 475        emac_rx_active_tail = rx_desc;
 476        emac_rx_queue_active = 1;
 477
 478        /* Enable TX/RX */
 479        writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
 480        writel(0, &adap_emac->RXBUFFEROFFSET);
 481
 482        /*
 483         * No fancy configs - Use this for promiscous debug
 484         *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
 485         */
 486        writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
 487
 488        /* Enable ch 0 only */
 489        writel(1, &adap_emac->RXUNICASTSET);
 490
 491        /* Enable MII interface and Full duplex mode */
 492#if defined(CONFIG_SOC_DA8XX) || \
 493        (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
 494        writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 495                EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
 496                EMAC_MACCONTROL_RMIISPEED_100),
 497               &adap_emac->MACCONTROL);
 498#else
 499        writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 500                EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
 501               &adap_emac->MACCONTROL);
 502#endif
 503
 504        /* Init MDIO & get link state */
 505        clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 506        writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 507               &adap_mdio->CONTROL);
 508
 509        /* We need to wait for MDIO to start */
 510        udelay(1000);
 511
 512        index = get_active_phy();
 513        if (index == -1)
 514                return(0);
 515
 516        emac_gigabit_enable(active_phy_addr[index]);
 517
 518        /* Start receive process */
 519        writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
 520
 521        debug_emac("- emac_open\n");
 522
 523        return(1);
 524}
 525
 526/* EMAC Channel Teardown */
 527static void davinci_eth_ch_teardown(int ch)
 528{
 529        dv_reg          dly = 0xff;
 530        dv_reg          cnt;
 531
 532        debug_emac("+ emac_ch_teardown\n");
 533
 534        if (ch == EMAC_CH_TX) {
 535                /* Init TX channel teardown */
 536                writel(0, &adap_emac->TXTEARDOWN);
 537                do {
 538                        /*
 539                         * Wait here for Tx teardown completion interrupt to
 540                         * occur. Note: A task delay can be called here to pend
 541                         * rather than occupying CPU cycles - anyway it has
 542                         * been found that teardown takes very few cpu cycles
 543                         * and does not affect functionality
 544                         */
 545                        dly--;
 546                        udelay(1);
 547                        if (dly == 0)
 548                                break;
 549                        cnt = readl(&adap_emac->TX0CP);
 550                } while (cnt != 0xfffffffc);
 551                writel(cnt, &adap_emac->TX0CP);
 552                writel(0, &adap_emac->TX0HDP);
 553        } else {
 554                /* Init RX channel teardown */
 555                writel(0, &adap_emac->RXTEARDOWN);
 556                do {
 557                        /*
 558                         * Wait here for Rx teardown completion interrupt to
 559                         * occur. Note: A task delay can be called here to pend
 560                         * rather than occupying CPU cycles - anyway it has
 561                         * been found that teardown takes very few cpu cycles
 562                         * and does not affect functionality
 563                         */
 564                        dly--;
 565                        udelay(1);
 566                        if (dly == 0)
 567                                break;
 568                        cnt = readl(&adap_emac->RX0CP);
 569                } while (cnt != 0xfffffffc);
 570                writel(cnt, &adap_emac->RX0CP);
 571                writel(0, &adap_emac->RX0HDP);
 572        }
 573
 574        debug_emac("- emac_ch_teardown\n");
 575}
 576
 577/* Eth device close */
 578static void davinci_eth_close(struct eth_device *dev)
 579{
 580        debug_emac("+ emac_close\n");
 581
 582        davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
 583        if (readl(&adap_emac->RXCONTROL) & 1)
 584                davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
 585
 586        /* Reset EMAC module and disable interrupts in wrapper */
 587        writel(1, &adap_emac->SOFTRESET);
 588#if defined(DAVINCI_EMAC_VERSION2)
 589        writel(1, &adap_ewrap->softrst);
 590#else
 591        writel(0, &adap_ewrap->EWCTL);
 592#endif
 593
 594#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 595        defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 596        adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 597        adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 598        adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 599#endif
 600        debug_emac("- emac_close\n");
 601}
 602
 603static int tx_send_loop = 0;
 604
 605/*
 606 * This function sends a single packet on the network and returns
 607 * positive number (number of bytes transmitted) or negative for error
 608 */
 609static int davinci_eth_send_packet (struct eth_device *dev,
 610                                        void *packet, int length)
 611{
 612        int ret_status = -1;
 613        int index;
 614        tx_send_loop = 0;
 615
 616        index = get_active_phy();
 617        if (index == -1) {
 618                printf(" WARN: emac_send_packet: No link\n");
 619                return (ret_status);
 620        }
 621
 622        emac_gigabit_enable(active_phy_addr[index]);
 623
 624        /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
 625        if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
 626                length = EMAC_MIN_ETHERNET_PKT_SIZE;
 627        }
 628
 629        /* Populate the TX descriptor */
 630        emac_tx_desc->next = 0;
 631        emac_tx_desc->buffer = (u_int8_t *) packet;
 632        emac_tx_desc->buff_off_len = (length & 0xffff);
 633        emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
 634                                      EMAC_CPPI_SOP_BIT |
 635                                      EMAC_CPPI_OWNERSHIP_BIT |
 636                                      EMAC_CPPI_EOP_BIT);
 637
 638        flush_dcache_range((unsigned long)packet,
 639                           (unsigned long)packet + ALIGN(length, PKTALIGN));
 640
 641        /* Send the packet */
 642        writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
 643
 644        /* Wait for packet to complete or link down */
 645        while (1) {
 646                if (!phy[index].get_link_speed(active_phy_addr[index])) {
 647                        davinci_eth_ch_teardown (EMAC_CH_TX);
 648                        return (ret_status);
 649                }
 650
 651                emac_gigabit_enable(active_phy_addr[index]);
 652
 653                if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
 654                        ret_status = length;
 655                        break;
 656                }
 657                tx_send_loop++;
 658        }
 659
 660        return (ret_status);
 661}
 662
 663/*
 664 * This function handles receipt of a packet from the network
 665 */
 666static int davinci_eth_rcv_packet (struct eth_device *dev)
 667{
 668        volatile emac_desc *rx_curr_desc;
 669        volatile emac_desc *curr_desc;
 670        volatile emac_desc *tail_desc;
 671        int status, ret = -1;
 672
 673        rx_curr_desc = emac_rx_active_head;
 674        if (!rx_curr_desc)
 675                return 0;
 676        status = rx_curr_desc->pkt_flag_len;
 677        if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
 678                if (status & EMAC_CPPI_RX_ERROR_FRAME) {
 679                        /* Error in packet - discard it and requeue desc */
 680                        printf ("WARN: emac_rcv_pkt: Error in packet\n");
 681                } else {
 682                        unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
 683                        unsigned short len =
 684                                rx_curr_desc->buff_off_len & 0xffff;
 685
 686                        invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
 687                        net_process_received_packet(rx_curr_desc->buffer, len);
 688                        ret = len;
 689                }
 690
 691                /* Ack received packet descriptor */
 692                writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
 693                curr_desc = rx_curr_desc;
 694                emac_rx_active_head =
 695                        (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
 696
 697                if (status & EMAC_CPPI_EOQ_BIT) {
 698                        if (emac_rx_active_head) {
 699                                writel(BD_TO_HW((ulong)emac_rx_active_head),
 700                                       &adap_emac->RX0HDP);
 701                        } else {
 702                                emac_rx_queue_active = 0;
 703                                printf ("INFO:emac_rcv_packet: RX Queue not active\n");
 704                        }
 705                }
 706
 707                /* Recycle RX descriptor */
 708                rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 709                rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 710                rx_curr_desc->next = 0;
 711
 712                if (emac_rx_active_head == 0) {
 713                        printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
 714                        emac_rx_active_head = curr_desc;
 715                        emac_rx_active_tail = curr_desc;
 716                        if (emac_rx_queue_active != 0) {
 717                                writel(BD_TO_HW((ulong)emac_rx_active_head),
 718                                       &adap_emac->RX0HDP);
 719                                printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
 720                                emac_rx_queue_active = 1;
 721                        }
 722                } else {
 723                        tail_desc = emac_rx_active_tail;
 724                        emac_rx_active_tail = curr_desc;
 725                        tail_desc->next = BD_TO_HW((ulong) curr_desc);
 726                        status = tail_desc->pkt_flag_len;
 727                        if (status & EMAC_CPPI_EOQ_BIT) {
 728                                writel(BD_TO_HW((ulong)curr_desc),
 729                                       &adap_emac->RX0HDP);
 730                                status &= ~EMAC_CPPI_EOQ_BIT;
 731                                tail_desc->pkt_flag_len = status;
 732                        }
 733                }
 734                return (ret);
 735        }
 736        return (0);
 737}
 738
 739/*
 740 * This function initializes the emac hardware. It does NOT initialize
 741 * EMAC modules power or pin multiplexors, that is done by board_init()
 742 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
 743 */
 744int davinci_emac_initialize(void)
 745{
 746        u_int32_t       phy_id;
 747        u_int16_t       tmp;
 748        int             i;
 749        int             ret;
 750        struct eth_device *dev;
 751
 752        dev = malloc(sizeof *dev);
 753
 754        if (dev == NULL)
 755                return -1;
 756
 757        memset(dev, 0, sizeof *dev);
 758        strcpy(dev->name, "DaVinci-EMAC");
 759
 760        dev->iobase = 0;
 761        dev->init = davinci_eth_open;
 762        dev->halt = davinci_eth_close;
 763        dev->send = davinci_eth_send_packet;
 764        dev->recv = davinci_eth_rcv_packet;
 765        dev->write_hwaddr = davinci_eth_set_mac_addr;
 766
 767        eth_register(dev);
 768
 769        davinci_eth_mdio_enable();
 770
 771        /* let the EMAC detect the PHYs */
 772        udelay(5000);
 773
 774        for (i = 0; i < 256; i++) {
 775                if (readl(&adap_mdio->ALIVE))
 776                        break;
 777                udelay(1000);
 778        }
 779
 780        if (i >= 256) {
 781                printf("No ETH PHY detected!!!\n");
 782                return(0);
 783        }
 784
 785        /* Find if PHY(s) is/are connected */
 786        ret = davinci_eth_phy_detect();
 787        if (!ret)
 788                return(0);
 789        else
 790                debug_emac(" %d ETH PHY detected\n", ret);
 791
 792        /* Get PHY ID and initialize phy_ops for a detected PHY */
 793        for (i = 0; i < num_phy; i++) {
 794                if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
 795                                                        &tmp)) {
 796                        active_phy_addr[i] = 0xff;
 797                        continue;
 798                }
 799
 800                phy_id = (tmp << 16) & 0xffff0000;
 801
 802                if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
 803                                                        &tmp)) {
 804                        active_phy_addr[i] = 0xff;
 805                        continue;
 806                }
 807
 808                phy_id |= tmp & 0x0000ffff;
 809
 810                switch (phy_id) {
 811#ifdef PHY_KSZ8873
 812                case PHY_KSZ8873:
 813                        sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
 814                                                active_phy_addr[i]);
 815                        phy[i].init = ksz8873_init_phy;
 816                        phy[i].is_phy_connected = ksz8873_is_phy_connected;
 817                        phy[i].get_link_speed = ksz8873_get_link_speed;
 818                        phy[i].auto_negotiate = ksz8873_auto_negotiate;
 819                        break;
 820#endif
 821#ifdef PHY_LXT972
 822                case PHY_LXT972:
 823                        sprintf(phy[i].name, "LXT972 @ 0x%02x",
 824                                                active_phy_addr[i]);
 825                        phy[i].init = lxt972_init_phy;
 826                        phy[i].is_phy_connected = lxt972_is_phy_connected;
 827                        phy[i].get_link_speed = lxt972_get_link_speed;
 828                        phy[i].auto_negotiate = lxt972_auto_negotiate;
 829                        break;
 830#endif
 831#ifdef PHY_DP83848
 832                case PHY_DP83848:
 833                        sprintf(phy[i].name, "DP83848 @ 0x%02x",
 834                                                active_phy_addr[i]);
 835                        phy[i].init = dp83848_init_phy;
 836                        phy[i].is_phy_connected = dp83848_is_phy_connected;
 837                        phy[i].get_link_speed = dp83848_get_link_speed;
 838                        phy[i].auto_negotiate = dp83848_auto_negotiate;
 839                        break;
 840#endif
 841#ifdef PHY_ET1011C
 842                case PHY_ET1011C:
 843                        sprintf(phy[i].name, "ET1011C @ 0x%02x",
 844                                                active_phy_addr[i]);
 845                        phy[i].init = gen_init_phy;
 846                        phy[i].is_phy_connected = gen_is_phy_connected;
 847                        phy[i].get_link_speed = et1011c_get_link_speed;
 848                        phy[i].auto_negotiate = gen_auto_negotiate;
 849                        break;
 850#endif
 851                default:
 852                        sprintf(phy[i].name, "GENERIC @ 0x%02x",
 853                                                active_phy_addr[i]);
 854                        phy[i].init = gen_init_phy;
 855                        phy[i].is_phy_connected = gen_is_phy_connected;
 856                        phy[i].get_link_speed = gen_get_link_speed;
 857                        phy[i].auto_negotiate = gen_auto_negotiate;
 858                }
 859
 860                debug("Ethernet PHY: %s\n", phy[i].name);
 861
 862                int retval;
 863                struct mii_dev *mdiodev = mdio_alloc();
 864                if (!mdiodev)
 865                        return -ENOMEM;
 866                strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
 867                mdiodev->read = davinci_mii_phy_read;
 868                mdiodev->write = davinci_mii_phy_write;
 869
 870                retval = mdio_register(mdiodev);
 871                if (retval < 0)
 872                        return retval;
 873        }
 874
 875#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 876                defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
 877                        !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
 878        for (i = 0; i < num_phy; i++) {
 879                if (phy[i].is_phy_connected(i))
 880                        phy[i].auto_negotiate(i);
 881        }
 882#endif
 883        return(1);
 884}
 885