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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16
17
18
19#define CONFIG_E300 1
20#define CONFIG_MPC834x 1
21#define CONFIG_MPC8349 1
22#define CONFIG_MPC8349EMDS 1
23
24#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
26#define CONFIG_PCI_66M
27#ifdef CONFIG_PCI_66M
28#define CONFIG_83XX_CLKIN 66000000
29#else
30#define CONFIG_83XX_CLKIN 33000000
31#endif
32
33#ifdef CONFIG_PCISLAVE
34#define CONFIG_83XX_PCICLK 66666666
35#endif
36
37#ifndef CONFIG_SYS_CLK_FREQ
38#ifdef CONFIG_PCI_66M
39#define CONFIG_SYS_CLK_FREQ 66000000
40#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
41#else
42#define CONFIG_SYS_CLK_FREQ 33000000
43#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
44#endif
45#endif
46
47#define CONFIG_BOARD_EARLY_INIT_F
48
49#define CONFIG_SYS_IMMR 0xE0000000
50
51#undef CONFIG_SYS_DRAM_TEST
52#define CONFIG_SYS_MEMTEST_START 0x00000000
53#define CONFIG_SYS_MEMTEST_END 0x00100000
54
55
56
57
58#define CONFIG_DDR_ECC
59#define CONFIG_DDR_ECC_CMD
60#define CONFIG_SPD_EEPROM
61
62
63
64
65
66#define CONFIG_SYS_SPD_BUS_NUM 0
67#define SPD_EEPROM_ADDRESS1 0x52
68#define SPD_EEPROM_ADDRESS2 0x51
69#define CONFIG_DIMM_SLOTS_PER_CTLR 2
70#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
71#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
72#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73
74
75
76
77
78
79
80
81
82
83
84#undef CONFIG_DDR_32BIT
85
86#define CONFIG_SYS_DDR_BASE 0x00000000
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
88#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
89#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
90 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
91#undef CONFIG_DDR_2T_TIMING
92
93
94
95
96#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
97
98#if defined(CONFIG_SPD_EEPROM)
99
100
101
102#define SPD_EEPROM_ADDRESS 0x51
103#else
104
105
106
107#define CONFIG_SYS_DDR_SIZE 256
108#if defined(CONFIG_DDR_II)
109#define CONFIG_SYS_DDRCDR 0x80080001
110#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
111#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
112#define CONFIG_SYS_DDR_TIMING_0 0x00220802
113#define CONFIG_SYS_DDR_TIMING_1 0x38357322
114#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
115#define CONFIG_SYS_DDR_TIMING_3 0x00000000
116#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
117#define CONFIG_SYS_DDR_MODE 0x47d00432
118#define CONFIG_SYS_DDR_MODE2 0x8000c000
119#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
120#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
121#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
122#else
123#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
124 | CSCONFIG_ROW_BIT_13 \
125 | CSCONFIG_COL_BIT_10)
126#define CONFIG_SYS_DDR_TIMING_1 0x36332321
127#define CONFIG_SYS_DDR_TIMING_2 0x00000800
128#define CONFIG_SYS_DDR_CONTROL 0xc2000000
129#define CONFIG_SYS_DDR_INTERVAL 0x04060100
130
131#if defined(CONFIG_DDR_32BIT)
132
133
134#define CONFIG_SYS_DDR_MODE 0x00000023
135#else
136
137
138#define CONFIG_SYS_DDR_MODE 0x00000022
139#endif
140#endif
141#endif
142
143
144
145
146#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
147#define CONFIG_SYS_LBC_SDRAM_SIZE 64
148
149
150
151
152#define CONFIG_SYS_FLASH_CFI
153#define CONFIG_FLASH_CFI_DRIVER
154#define CONFIG_SYS_FLASH_BASE 0xFE000000
155#define CONFIG_SYS_FLASH_SIZE 32
156#define CONFIG_SYS_FLASH_PROTECTION 1
157
158
159#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
160 | BR_PS_16 \
161 | BR_MS_GPCM \
162 | BR_V)
163#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
164 | OR_UPM_XAM \
165 | OR_GPCM_CSNT \
166 | OR_GPCM_ACS_DIV2 \
167 | OR_GPCM_XACS \
168 | OR_GPCM_SCY_15 \
169 | OR_GPCM_TRLX_SET \
170 | OR_GPCM_EHTR_SET \
171 | OR_GPCM_EAD)
172
173
174#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
175#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
176
177#define CONFIG_SYS_MAX_FLASH_BANKS 1
178#define CONFIG_SYS_MAX_FLASH_SECT 256
179
180#undef CONFIG_SYS_FLASH_CHECKSUM
181#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
182#define CONFIG_SYS_FLASH_WRITE_TOUT 500
183
184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
185
186#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
187#define CONFIG_SYS_RAMBOOT
188#else
189#undef CONFIG_SYS_RAMBOOT
190#endif
191
192
193
194
195#define CONFIG_SYS_BCSR 0xE2400000
196
197#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
198#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
199#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
200 | BR_PS_8 \
201 | BR_MS_GPCM \
202 | BR_V)
203
204#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
205 | OR_GPCM_XAM \
206 | OR_GPCM_CSNT \
207 | OR_GPCM_SCY_15 \
208 | OR_GPCM_TRLX_CLEAR \
209 | OR_GPCM_EHTR_CLEAR)
210
211
212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
214#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
215
216#define CONFIG_SYS_GBL_DATA_OFFSET \
217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
219
220#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
221#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
222
223
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225
226
227
228
229#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
230#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
231#define CONFIG_SYS_LBC_LBCR 0x00000000
232
233
234
235
236
237#undef CONFIG_SYS_LB_SDRAM
238
239#ifdef CONFIG_SYS_LB_SDRAM
240
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254
255
256#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
257 | BR_PS_32 \
258 | BR_MS_SDRAM \
259 | BR_V)
260
261#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
262#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
263
264
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276
277
278#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
279 | OR_SDRAM_XAM \
280 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
281 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
282 | OR_SDRAM_EAD)
283
284
285
286#define CONFIG_SYS_LBC_LSRT 0x32000000
287
288#define CONFIG_SYS_LBC_MRTPR 0x20000000
289
290#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
291 | LSDMR_BSMA1516 \
292 | LSDMR_RFCR8 \
293 | LSDMR_PRETOACT6 \
294 | LSDMR_ACTTORW3 \
295 | LSDMR_BL8 \
296 | LSDMR_WRC3 \
297 | LSDMR_CL3)
298
299
300
301
302#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
303#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
304#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
305#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
306#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
307#endif
308
309
310
311
312#define CONFIG_CONS_INDEX 1
313#define CONFIG_SYS_NS16550_SERIAL
314#define CONFIG_SYS_NS16550_REG_SIZE 1
315#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
316
317#define CONFIG_SYS_BAUDRATE_TABLE \
318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
319
320#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
321#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
322
323#define CONFIG_CMDLINE_EDITING 1
324#define CONFIG_AUTO_COMPLETE
325
326
327#define CONFIG_SYS_I2C
328#define CONFIG_SYS_I2C_FSL
329#define CONFIG_SYS_FSL_I2C_SPEED 400000
330#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
331#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
332#define CONFIG_SYS_FSL_I2C2_SPEED 400000
333#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
334#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
335#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
336
337
338#define CONFIG_MPC8XXX_SPI
339#undef CONFIG_SOFT_SPI
340
341
342#define CONFIG_SYS_GPIO1_PRELIM
343#define CONFIG_SYS_GPIO1_DIR 0xC0000000
344#define CONFIG_SYS_GPIO1_DAT 0xC0000000
345
346
347#define CONFIG_SYS_TSEC1_OFFSET 0x24000
348#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
349#define CONFIG_SYS_TSEC2_OFFSET 0x25000
350#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
351
352
353#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1
354
355
356
357
358
359#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
360#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
361#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
362#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
363#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
364#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
365#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
366#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
367#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
368
369#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
370#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
371#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
372#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
373#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
374#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
375#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
376#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
377#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
378
379#if defined(CONFIG_PCI)
380
381#define PCI_ONE_PCI1
382#if defined(PCI_64BIT)
383#undef PCI_ALL_PCI1
384#undef PCI_TWO_PCI1
385#undef PCI_ONE_PCI1
386#endif
387
388#define CONFIG_83XX_PCI_STREAMING
389
390#undef CONFIG_EEPRO100
391#undef CONFIG_TULIP
392
393#if !defined(CONFIG_PCI_PNP)
394 #define PCI_ENET0_IOADDR 0xFIXME
395 #define PCI_ENET0_MEMADDR 0xFIXME
396 #define PCI_IDSEL_NUMBER 0x0c
397#endif
398
399#undef CONFIG_PCI_SCAN_SHOW
400#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
401
402#endif
403
404
405
406
407#define CONFIG_TSEC_ENET
408
409#if defined(CONFIG_TSEC_ENET)
410
411#define CONFIG_GMII 1
412#define CONFIG_TSEC1 1
413#define CONFIG_TSEC1_NAME "TSEC0"
414#define CONFIG_TSEC2 1
415#define CONFIG_TSEC2_NAME "TSEC1"
416#define TSEC1_PHY_ADDR 0
417#define TSEC2_PHY_ADDR 1
418#define TSEC1_PHYIDX 0
419#define TSEC2_PHYIDX 0
420#define TSEC1_FLAGS TSEC_GIGABIT
421#define TSEC2_FLAGS TSEC_GIGABIT
422
423
424#define CONFIG_ETHPRIME "TSEC0"
425
426#endif
427
428
429
430
431#define CONFIG_RTC_DS1374
432#define CONFIG_SYS_I2C_RTC_ADDR 0x68
433
434
435
436
437#ifndef CONFIG_SYS_RAMBOOT
438 #define CONFIG_ENV_IS_IN_FLASH 1
439 #define CONFIG_ENV_ADDR \
440 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
441 #define CONFIG_ENV_SECT_SIZE 0x20000
442 #define CONFIG_ENV_SIZE 0x2000
443
444
445#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
446#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
447
448#else
449 #define CONFIG_SYS_NO_FLASH 1
450 #define CONFIG_ENV_IS_NOWHERE 1
451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
452 #define CONFIG_ENV_SIZE 0x2000
453#endif
454
455#define CONFIG_LOADS_ECHO 1
456#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
457
458
459
460
461#define CONFIG_BOOTP_BOOTFILESIZE
462#define CONFIG_BOOTP_BOOTPATH
463#define CONFIG_BOOTP_GATEWAY
464#define CONFIG_BOOTP_HOSTNAME
465
466
467
468
469#define CONFIG_CMD_DATE
470
471#if defined(CONFIG_PCI)
472 #define CONFIG_CMD_PCI
473#endif
474
475#undef CONFIG_WATCHDOG
476
477
478
479
480#define CONFIG_SYS_LONGHELP
481#define CONFIG_SYS_LOAD_ADDR 0x2000000
482
483#if defined(CONFIG_CMD_KGDB)
484 #define CONFIG_SYS_CBSIZE 1024
485#else
486 #define CONFIG_SYS_CBSIZE 256
487#endif
488
489
490#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
491#define CONFIG_SYS_MAXARGS 16
492
493#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
494
495
496
497
498
499
500
501#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
502#define CONFIG_SYS_BOOTM_LEN (64 << 20)
503
504#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
505
506#if 1
507#define CONFIG_SYS_HRCW_LOW (\
508 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
509 HRCWL_DDR_TO_SCB_CLK_1X1 |\
510 HRCWL_CSB_TO_CLKIN |\
511 HRCWL_VCO_1X2 |\
512 HRCWL_CORE_TO_CSB_2X1)
513#elif 0
514#define CONFIG_SYS_HRCW_LOW (\
515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
516 HRCWL_DDR_TO_SCB_CLK_1X1 |\
517 HRCWL_CSB_TO_CLKIN |\
518 HRCWL_VCO_1X4 |\
519 HRCWL_CORE_TO_CSB_3X1)
520#elif 0
521#define CONFIG_SYS_HRCW_LOW (\
522 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
523 HRCWL_DDR_TO_SCB_CLK_1X1 |\
524 HRCWL_CSB_TO_CLKIN |\
525 HRCWL_VCO_1X4 |\
526 HRCWL_CORE_TO_CSB_2X1)
527#elif 0
528#define CONFIG_SYS_HRCW_LOW (\
529 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
530 HRCWL_DDR_TO_SCB_CLK_1X1 |\
531 HRCWL_CSB_TO_CLKIN |\
532 HRCWL_VCO_1X4 |\
533 HRCWL_CORE_TO_CSB_1X1)
534#elif 0
535#define CONFIG_SYS_HRCW_LOW (\
536 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
537 HRCWL_DDR_TO_SCB_CLK_1X1 |\
538 HRCWL_CSB_TO_CLKIN |\
539 HRCWL_VCO_1X4 |\
540 HRCWL_CORE_TO_CSB_1X1)
541#endif
542
543#ifdef CONFIG_PCISLAVE
544#define CONFIG_SYS_HRCW_HIGH (\
545 HRCWH_PCI_AGENT |\
546 HRCWH_64_BIT_PCI |\
547 HRCWH_PCI1_ARBITER_DISABLE |\
548 HRCWH_PCI2_ARBITER_DISABLE |\
549 HRCWH_CORE_ENABLE |\
550 HRCWH_FROM_0X00000100 |\
551 HRCWH_BOOTSEQ_DISABLE |\
552 HRCWH_SW_WATCHDOG_DISABLE |\
553 HRCWH_ROM_LOC_LOCAL_16BIT |\
554 HRCWH_TSEC1M_IN_GMII |\
555 HRCWH_TSEC2M_IN_GMII)
556#else
557#if defined(PCI_64BIT)
558#define CONFIG_SYS_HRCW_HIGH (\
559 HRCWH_PCI_HOST |\
560 HRCWH_64_BIT_PCI |\
561 HRCWH_PCI1_ARBITER_ENABLE |\
562 HRCWH_PCI2_ARBITER_DISABLE |\
563 HRCWH_CORE_ENABLE |\
564 HRCWH_FROM_0X00000100 |\
565 HRCWH_BOOTSEQ_DISABLE |\
566 HRCWH_SW_WATCHDOG_DISABLE |\
567 HRCWH_ROM_LOC_LOCAL_16BIT |\
568 HRCWH_TSEC1M_IN_GMII |\
569 HRCWH_TSEC2M_IN_GMII)
570#else
571#define CONFIG_SYS_HRCW_HIGH (\
572 HRCWH_PCI_HOST |\
573 HRCWH_32_BIT_PCI |\
574 HRCWH_PCI1_ARBITER_ENABLE |\
575 HRCWH_PCI2_ARBITER_ENABLE |\
576 HRCWH_CORE_ENABLE |\
577 HRCWH_FROM_0X00000100 |\
578 HRCWH_BOOTSEQ_DISABLE |\
579 HRCWH_SW_WATCHDOG_DISABLE |\
580 HRCWH_ROM_LOC_LOCAL_16BIT |\
581 HRCWH_TSEC1M_IN_GMII |\
582 HRCWH_TSEC2M_IN_GMII)
583#endif
584#endif
585
586
587
588
589#define CONFIG_SYS_ACR_PIPE_DEP 3
590#define CONFIG_SYS_ACR_RPTCNT 3
591#define CONFIG_SYS_SPCR_TSEC1EP 3
592#define CONFIG_SYS_SPCR_TSEC2EP 3
593#define CONFIG_SYS_SCCR_TSEC1CM 1
594#define CONFIG_SYS_SCCR_TSEC2CM 1
595
596
597#define CONFIG_SYS_SICRH 0
598#define CONFIG_SYS_SICRL SICRL_LDP_A
599
600#define CONFIG_SYS_HID0_INIT 0x000000000
601#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
602 | HID0_ENABLE_INSTRUCTION_CACHE)
603
604
605
606
607
608
609#define CONFIG_SYS_HID2 HID2_HBE
610#define CONFIG_HIGH_BATS 1
611
612
613#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
614 | BATL_PP_RW \
615 | BATL_MEMCOHERENCE)
616#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
617 | BATU_BL_256M \
618 | BATU_VS \
619 | BATU_VP)
620
621
622#ifdef CONFIG_PCI
623#define CONFIG_PCI_INDIRECT_BRIDGE
624#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
625 | BATL_PP_RW \
626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
631#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
632 | BATL_PP_RW \
633 | BATL_CACHEINHIBIT \
634 | BATL_GUARDEDSTORAGE)
635#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
636 | BATU_BL_256M \
637 | BATU_VS \
638 | BATU_VP)
639#else
640#define CONFIG_SYS_IBAT1L (0)
641#define CONFIG_SYS_IBAT1U (0)
642#define CONFIG_SYS_IBAT2L (0)
643#define CONFIG_SYS_IBAT2U (0)
644#endif
645
646#ifdef CONFIG_MPC83XX_PCI2
647#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
648 | BATL_PP_RW \
649 | BATL_MEMCOHERENCE)
650#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
651 | BATU_BL_256M \
652 | BATU_VS \
653 | BATU_VP)
654#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
655 | BATL_PP_RW \
656 | BATL_CACHEINHIBIT \
657 | BATL_GUARDEDSTORAGE)
658#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
659 | BATU_BL_256M \
660 | BATU_VS \
661 | BATU_VP)
662#else
663#define CONFIG_SYS_IBAT3L (0)
664#define CONFIG_SYS_IBAT3U (0)
665#define CONFIG_SYS_IBAT4L (0)
666#define CONFIG_SYS_IBAT4U (0)
667#endif
668
669
670#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
671 | BATL_PP_RW \
672 | BATL_CACHEINHIBIT \
673 | BATL_GUARDEDSTORAGE)
674#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
675 | BATU_BL_256M \
676 | BATU_VS \
677 | BATU_VP)
678
679
680#define CONFIG_SYS_IBAT6L (0xF0000000 \
681 | BATL_PP_RW \
682 | BATL_MEMCOHERENCE \
683 | BATL_GUARDEDSTORAGE)
684#define CONFIG_SYS_IBAT6U (0xF0000000 \
685 | BATU_BL_256M \
686 | BATU_VS \
687 | BATU_VP)
688
689#define CONFIG_SYS_IBAT7L (0)
690#define CONFIG_SYS_IBAT7U (0)
691
692#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
693#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
694#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
695#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
696#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
697#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
698#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
699#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
700#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
701#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
702#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
703#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
704#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
705#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
706#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
707#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
708
709#if defined(CONFIG_CMD_KGDB)
710#define CONFIG_KGDB_BAUDRATE 230400
711#endif
712
713
714
715
716#define CONFIG_ENV_OVERWRITE
717
718#if defined(CONFIG_TSEC_ENET)
719#define CONFIG_HAS_ETH1
720#define CONFIG_HAS_ETH0
721#endif
722
723#define CONFIG_HOSTNAME mpc8349emds
724#define CONFIG_ROOTPATH "/nfsroot/rootfs"
725#define CONFIG_BOOTFILE "uImage"
726
727#define CONFIG_LOADADDR 800000
728
729#undef CONFIG_BOOTARGS
730
731#define CONFIG_BAUDRATE 115200
732
733#define CONFIG_PREBOOT "echo;" \
734 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
735 "echo"
736
737#define CONFIG_EXTRA_ENV_SETTINGS \
738 "netdev=eth0\0" \
739 "hostname=mpc8349emds\0" \
740 "nfsargs=setenv bootargs root=/dev/nfs rw " \
741 "nfsroot=${serverip}:${rootpath}\0" \
742 "ramargs=setenv bootargs root=/dev/ram rw\0" \
743 "addip=setenv bootargs ${bootargs} " \
744 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
745 ":${hostname}:${netdev}:off panic=1\0" \
746 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
747 "flash_nfs=run nfsargs addip addtty;" \
748 "bootm ${kernel_addr}\0" \
749 "flash_self=run ramargs addip addtty;" \
750 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
751 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
752 "bootm\0" \
753 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
754 "update=protect off fe000000 fe03ffff; " \
755 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
756 "upd=run load update\0" \
757 "fdtaddr=780000\0" \
758 "fdtfile=mpc834x_mds.dtb\0" \
759 ""
760
761#define CONFIG_NFSBOOTCOMMAND \
762 "setenv bootargs root=/dev/nfs rw " \
763 "nfsroot=$serverip:$rootpath " \
764 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
765 "$netdev:off " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr - $fdtaddr"
770
771#define CONFIG_RAMBOOTCOMMAND \
772 "setenv bootargs root=/dev/ram rw " \
773 "console=$consoledev,$baudrate $othbootargs;" \
774 "tftp $ramdiskaddr $ramdiskfile;" \
775 "tftp $loadaddr $bootfile;" \
776 "tftp $fdtaddr $fdtfile;" \
777 "bootm $loadaddr $ramdiskaddr $fdtaddr"
778
779#define CONFIG_BOOTCOMMAND "run flash_self"
780
781#endif
782