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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_SYS_TEXT_BASE 0xfff80000
14
15#define CONFIG_SYS_SRIO
16#define CONFIG_SRIO1
17
18#define CONFIG_PCI1 1
19#define CONFIG_PCIE1 1
20#define CONFIG_FSL_PCI_INIT 1
21#define CONFIG_PCI_INDIRECT_BRIDGE 1
22#define CONFIG_FSL_PCIE_RESET 1
23#define CONFIG_SYS_PCI_64BIT 1
24#define CONFIG_TSEC_ENET
25#define CONFIG_QE
26#define CONFIG_ENV_OVERWRITE
27
28#ifndef __ASSEMBLY__
29extern unsigned long get_clock_freq(void);
30#endif
31#define CONFIG_SYS_CLK_FREQ 66000000
32
33
34
35
36#define CONFIG_L2_CACHE
37#define CONFIG_BTB
38
39
40
41
42#define CONFIG_ENABLE_36BIT_PHYS 1
43
44#define CONFIG_BOARD_EARLY_INIT_F 1
45
46#define CONFIG_SYS_MEMTEST_START 0x00200000
47#define CONFIG_SYS_MEMTEST_END 0x00400000
48
49#define CONFIG_SYS_CCSRBAR 0xe0000000
50#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
51
52
53#undef CONFIG_FSL_DDR_INTERACTIVE
54#define CONFIG_SPD_EEPROM
55#define CONFIG_DDR_SPD
56#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
57
58#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
59
60#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
61#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
62
63#define CONFIG_DIMM_SLOTS_PER_CTLR 1
64#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
65
66
67#define SPD_EEPROM_ADDRESS 0x51
68
69
70#ifndef CONFIG_SPD_EEPROM
71#error ("CONFIG_SPD_EEPROM is required")
72#endif
73
74#undef CONFIG_CLOCKS_IN_MHZ
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108
109#define CONFIG_SYS_BCSR_BASE 0xf8000000
110
111#define CONFIG_SYS_FLASH_BASE 0xfe000000
112
113
114#define CONFIG_SYS_BR0_PRELIM 0xfe001001
115#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
116
117
118#define CONFIG_SYS_BR1_PRELIM 0xf8000801
119#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
120
121
122#define CONFIG_SYS_MAX_FLASH_BANKS 1
123#define CONFIG_SYS_MAX_FLASH_SECT 512
124#undef CONFIG_SYS_FLASH_CHECKSUM
125#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500
127
128#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
129
130#define CONFIG_FLASH_CFI_DRIVER
131#define CONFIG_SYS_FLASH_CFI
132#define CONFIG_SYS_FLASH_EMPTY_INFO
133
134
135
136
137#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
138#define CONFIG_SYS_LBC_SDRAM_SIZE 64
139
140
141#define CONFIG_SYS_BR2_PRELIM 0xf0001861
142#define CONFIG_SYS_OR2_PRELIM 0xfc006901
143
144#define CONFIG_SYS_LBC_LCRR 0x00030004
145#define CONFIG_SYS_LBC_LBCR 0x00000000
146#define CONFIG_SYS_LBC_LSRT 0x20000000
147#define CONFIG_SYS_LBC_MRTPR 0x00000000
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154
155#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
156 | LSDMR_PRETOACT7 \
157 | LSDMR_ACTTORW7 \
158 | LSDMR_BL8 \
159 | LSDMR_WRC4 \
160 | LSDMR_CL3 \
161 | LSDMR_RFEN \
162 )
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192
193#define CONFIG_SYS_BCSR (0xf8000000)
194
195
196#define CONFIG_SYS_BR4_PRELIM 0xf8008801
197#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
198
199
200#define CONFIG_SYS_BR5_PRELIM 0xf8010801
201#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
202
203#define CONFIG_SYS_INIT_RAM_LOCK 1
204#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
205#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
206
207#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
211#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
212
213
214#define CONFIG_CONS_INDEX 1
215#define CONFIG_SYS_NS16550_SERIAL
216#define CONFIG_SYS_NS16550_REG_SIZE 1
217#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
218
219#define CONFIG_SYS_BAUDRATE_TABLE \
220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
221
222#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
223#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
224
225
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227
228#define CONFIG_SYS_I2C
229#define CONFIG_SYS_I2C_FSL
230#define CONFIG_SYS_FSL_I2C_SPEED 400000
231#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
232#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
233#define CONFIG_SYS_FSL_I2C2_SPEED 400000
234#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
235#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
236#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
237#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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242
243#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
244#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
245#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
246#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
247#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
248#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
249#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
250#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000
251
252#define CONFIG_SYS_PCIE1_NAME "Slot"
253#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
254#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
255#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
256#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
257#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
258#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
259#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
260#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
261
262#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
263#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
264#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
265#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
266
267#ifdef CONFIG_QE
268
269
270
271#define CONFIG_UEC_ETH
272#ifndef CONFIG_TSEC_ENET
273#define CONFIG_ETHPRIME "UEC0"
274#endif
275#define CONFIG_PHY_MODE_NEED_CHANGE
276#define CONFIG_eTSEC_MDIO_BUS
277
278#ifdef CONFIG_eTSEC_MDIO_BUS
279#define CONFIG_MIIM_ADDRESS 0xE0024520
280#endif
281
282#define CONFIG_UEC_ETH1
283
284#ifdef CONFIG_UEC_ETH1
285#define CONFIG_SYS_UEC1_UCC_NUM 0
286#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
287#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
288#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
289#define CONFIG_SYS_UEC1_PHY_ADDR 7
290#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
291#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
292#endif
293
294#define CONFIG_UEC_ETH2
295
296#ifdef CONFIG_UEC_ETH2
297#define CONFIG_SYS_UEC2_UCC_NUM 1
298#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
299#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
300#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
301#define CONFIG_SYS_UEC2_PHY_ADDR 1
302#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
303#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
304#endif
305#endif
306
307#if defined(CONFIG_PCI)
308#undef CONFIG_EEPRO100
309#undef CONFIG_TULIP
310
311#undef CONFIG_PCI_SCAN_SHOW
312#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
313
314#endif
315
316#if defined(CONFIG_TSEC_ENET)
317
318#define CONFIG_MII 1
319#define CONFIG_TSEC1 1
320#define CONFIG_TSEC1_NAME "eTSEC0"
321#define CONFIG_TSEC2 1
322#define CONFIG_TSEC2_NAME "eTSEC1"
323
324#define TSEC1_PHY_ADDR 2
325#define TSEC2_PHY_ADDR 3
326
327#define TSEC1_PHYIDX 0
328#define TSEC2_PHYIDX 0
329
330#define TSEC1_FLAGS TSEC_GIGABIT
331#define TSEC2_FLAGS TSEC_GIGABIT
332
333
334#define CONFIG_ETHPRIME "eTSEC0"
335
336#endif
337
338
339
340
341#define CONFIG_ENV_IS_IN_FLASH 1
342#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
343#define CONFIG_ENV_SECT_SIZE 0x40000
344#define CONFIG_ENV_SIZE 0x2000
345
346#define CONFIG_LOADS_ECHO 1
347#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
348
349
350
351
352#define CONFIG_BOOTP_BOOTFILESIZE
353#define CONFIG_BOOTP_BOOTPATH
354#define CONFIG_BOOTP_GATEWAY
355#define CONFIG_BOOTP_HOSTNAME
356
357
358
359
360#define CONFIG_CMD_IRQ
361#define CONFIG_CMD_REGINFO
362
363#if defined(CONFIG_PCI)
364 #define CONFIG_CMD_PCI
365#endif
366
367#undef CONFIG_WATCHDOG
368
369
370
371
372#define CONFIG_SYS_LONGHELP
373#define CONFIG_CMDLINE_EDITING
374#define CONFIG_AUTO_COMPLETE
375#define CONFIG_SYS_LOAD_ADDR 0x2000000
376#if defined(CONFIG_CMD_KGDB)
377#define CONFIG_SYS_CBSIZE 1024
378#else
379#define CONFIG_SYS_CBSIZE 256
380#endif
381#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
382#define CONFIG_SYS_MAXARGS 16
383#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384
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389
390#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
391#define CONFIG_SYS_BOOTM_LEN (64 << 20)
392
393#if defined(CONFIG_CMD_KGDB)
394#define CONFIG_KGDB_BAUDRATE 230400
395#endif
396
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401
402#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
403#define CONFIG_HAS_ETH0
404#define CONFIG_HAS_ETH1
405#define CONFIG_HAS_ETH2
406#define CONFIG_HAS_ETH3
407#endif
408
409#define CONFIG_IPADDR 192.168.1.253
410
411#define CONFIG_HOSTNAME unknown
412#define CONFIG_ROOTPATH "/nfsroot"
413#define CONFIG_BOOTFILE "your.uImage"
414
415#define CONFIG_SERVERIP 192.168.1.1
416#define CONFIG_GATEWAYIP 192.168.1.1
417#define CONFIG_NETMASK 255.255.255.0
418
419#define CONFIG_LOADADDR 200000
420
421#undef CONFIG_BOOTARGS
422
423#define CONFIG_BAUDRATE 115200
424
425#define CONFIG_EXTRA_ENV_SETTINGS \
426 "netdev=eth0\0" \
427 "consoledev=ttyS0\0" \
428 "ramdiskaddr=600000\0" \
429 "ramdiskfile=your.ramdisk.u-boot\0" \
430 "fdtaddr=400000\0" \
431 "fdtfile=your.fdt.dtb\0" \
432 "nfsargs=setenv bootargs root=/dev/nfs rw " \
433 "nfsroot=$serverip:$rootpath " \
434 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
435 "console=$consoledev,$baudrate $othbootargs\0" \
436 "ramargs=setenv bootargs root=/dev/ram rw " \
437 "console=$consoledev,$baudrate $othbootargs\0" \
438
439#define CONFIG_NFSBOOTCOMMAND \
440 "run nfsargs;" \
441 "tftp $loadaddr $bootfile;" \
442 "tftp $fdtaddr $fdtfile;" \
443 "bootm $loadaddr - $fdtaddr"
444
445#define CONFIG_RAMBOOTCOMMAND \
446 "run ramargs;" \
447 "tftp $ramdiskaddr $ramdiskfile;" \
448 "tftp $loadaddr $bootfile;" \
449 "bootm $loadaddr $ramdiskaddr"
450
451#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
452
453#endif
454