1/* 2 * (C) Copyright 2003 3 * Denis Peter d.peter@mpl.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * File: PATI.h 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 */ 18 19#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 20#define CONFIG_PATI 1 /* ...On a PATI board */ 21 22#define CONFIG_SYS_TEXT_BASE 0xFFF00000 23 24/* Serial Console Configuration */ 25#define CONFIG_5xx_CONS_SCI1 26#undef CONFIG_5xx_CONS_SCI2 27 28#define CONFIG_BAUDRATE 9600 29 30/* 31 * BOOTP options 32 */ 33#define CONFIG_BOOTP_BOOTFILESIZE 34#define CONFIG_BOOTP_BOOTPATH 35#define CONFIG_BOOTP_GATEWAY 36#define CONFIG_BOOTP_HOSTNAME 37 38/* 39 * Command line configuration. 40 */ 41#define CONFIG_CMD_REGINFO 42#define CONFIG_CMD_REGINFO 43#define CONFIG_CMD_BSP 44#define CONFIG_CMD_EEPROM 45#define CONFIG_CMD_IRQ 46 47#define CONFIG_BOOTCOMMAND "" /* autoboot command */ 48 49#define CONFIG_BOOTARGS "" /* */ 50 51#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 52 53/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ 54 55#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 56 57/* 58 * Miscellaneous configurable options 59 */ 60#define CONFIG_PREBOOT 61 62#define CONFIG_SYS_LONGHELP /* undef to save memory */ 63#if defined(CONFIG_CMD_KGDB) 64#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 65#else 66#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 67#endif 68#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 69#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 70#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 71 72#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 73#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 74 75#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 76 77#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 78 79#define CONFIG_BOARD_EARLY_INIT_F 80 81/*********************************************************************** 82 * Last Stage Init 83 ***********************************************************************/ 84#define CONFIG_LAST_STAGE_INIT 85 86/* 87 * Low Level Configuration Settings 88 */ 89 90/* 91 * Internal Memory Mapped (This is not the IMMR content) 92 */ 93#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 94 95/* 96 * Definitions for initial stack pointer and data area 97 */ 98#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 99#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 100#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 101#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 102/* 103 * Start addresses for the final memory configuration 104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 105 */ 106#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 107#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 108#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 109#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 110#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 111 112#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 113/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 114 /* This adress is given to the linker with -Ttext to */ 115 /* locate the text section at this adress. */ 116#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 117#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 118 119#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 120 121/* 122 * For booting Linux, the board info and command line data 123 * have to be in the first 8 MB of memory, since this is 124 * the maximum mapped by the Linux kernel during initialization. 125 */ 126#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 127 128/*----------------------------------------------------------------------- 129 * FLASH organization 130 *----------------------------------------------------------------------- 131 * 132 */ 133 134#define CONFIG_SYS_FLASH_PROTECTION 135#define CONFIG_SYS_FLASH_EMPTY_INFO 136 137#define CONFIG_SYS_FLASH_CFI 138#define CONFIG_FLASH_CFI_DRIVER 139 140#define CONFIG_FLASH_SHOW_PROGRESS 45 141 142#define CONFIG_SYS_MAX_FLASH_BANKS 1 143#define CONFIG_SYS_MAX_FLASH_SECT 128 144 145#define CONFIG_ENV_IS_IN_EEPROM 146#ifdef CONFIG_ENV_IS_IN_EEPROM 147#define CONFIG_ENV_OFFSET 0 148#define CONFIG_ENV_SIZE 2048 149#endif 150 151#undef CONFIG_ENV_IS_IN_FLASH 152#ifdef CONFIG_ENV_IS_IN_FLASH 153#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 154#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 155#endif 156 157#define CONFIG_SPI 1 158#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 159#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 160#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 161/*----------------------------------------------------------------------- 162 * SYPCR - System Protection Control 163 * SYPCR can only be written once after reset! 164 *----------------------------------------------------------------------- 165 * SW Watchdog freeze 166 */ 167#undef CONFIG_WATCHDOG 168#if defined(CONFIG_WATCHDOG) 169#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 170 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 171#else 172#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 173 SYPCR_SWP) 174#endif /* CONFIG_WATCHDOG */ 175 176/*----------------------------------------------------------------------- 177 * TBSCR - Time Base Status and Control 178 *----------------------------------------------------------------------- 179 * Clear Reference Interrupt Status, Timebase freezing enabled 180 */ 181#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 182 183/*----------------------------------------------------------------------- 184 * PISCR - Periodic Interrupt Status and Control 185 *----------------------------------------------------------------------- 186 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 187 */ 188#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 189 190/*----------------------------------------------------------------------- 191 * SCCR - System Clock and reset Control Register 192 *----------------------------------------------------------------------- 193 * Set clock output, timebase and RTC source and divider, 194 * power management and some other internal clocks 195 */ 196#define SCCR_MASK SCCR_EBDF00 197#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 198 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 199 200/*----------------------------------------------------------------------- 201 * SIUMCR - SIU Module Configuration 202 *----------------------------------------------------------------------- 203 * Data show cycle 204 */ 205#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 206 207/*----------------------------------------------------------------------- 208 * PLPRCR - PLL, Low-Power, and Reset Control Register 209 *----------------------------------------------------------------------- 210 * Set all bits to 40 Mhz 211 * 212 */ 213#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 214 215#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 216 217/*----------------------------------------------------------------------- 218 * UMCR - UIMB Module Configuration Register 219 *----------------------------------------------------------------------- 220 * 221 */ 222#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 223 224/*----------------------------------------------------------------------- 225 * ICTRL - I-Bus Support Control Register 226 */ 227#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 228 229/*----------------------------------------------------------------------- 230 * USIU - Memory Controller Register 231 *----------------------------------------------------------------------- 232 */ 233#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 234#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 235/* SDRAM */ 236#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 237#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 238/* PCI */ 239#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 240#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 241/* config registers: */ 242#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 243#define CONFIG_SYS_OR3_PRELIM (0xffff0000) 244 245#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 246 247/*----------------------------------------------------------------------- 248 * DER - Timer Decrementer 249 *----------------------------------------------------------------------- 250 * Initialise to zero 251 */ 252#define CONFIG_SYS_DER 0x00000000 253 254#endif /* __CONFIG_H */ 255