LXR uboot/include/configs/digsy

   1/*
   2 * (C) Copyright 2003-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2005-2007
   6 * Modified for InterControl digsyMTC MPC5200 board by
   7 * Frank Bodammer, GCD Hard- & Software GmbH,
   8 *                 frank.bodammer@gcd-solutions.de
   9 *
  10 * (C) Copyright 2009 Semihalf
  11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16#ifndef __CONFIG_H
  17#define __CONFIG_H
  18
  19/*
  20 * High Level Configuration Options
  21 */
  22
  23#define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  24#define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
  25
  26/*
  27 * Valid values for CONFIG_SYS_TEXT_BASE are:
  28 * 0xFFF00000   boot high (standard configuration)
  29 * 0xFE000000   boot low
  30 * 0x00100000   boot from RAM (for testing only)
  31 */
  32#ifndef CONFIG_SYS_TEXT_BASE
  33#define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34#endif
  35
  36#define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  37
  38#define CONFIG_SYS_CACHELINE_SIZE       32
  39
  40/*
  41 * Serial console configuration
  42 */
  43#define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
  44#define CONFIG_BAUDRATE         115200  /* ... at 115200  bps  */
  45#define CONFIG_SYS_BAUDRATE_TABLE       \
  46        { 9600, 19200, 38400, 57600, 115200, 230400 }
  47
  48/*
  49 * PCI Mapping:
  50 * 0x40000000 - 0x4fffffff - PCI Memory
  51 * 0x50000000 - 0x50ffffff - PCI IO Space
  52 */
  53#define CONFIG_PCI_SCAN_SHOW    1
  54#define CONFIG_PCI_BOOTDELAY    250
  55
  56#define CONFIG_PCI_MEM_BUS      0x40000000
  57#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  58#define CONFIG_PCI_MEM_SIZE     0x10000000
  59
  60#define CONFIG_PCI_IO_BUS       0x50000000
  61#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  62#define CONFIG_PCI_IO_SIZE      0x01000000
  63
  64/*
  65 *  Partitions
  66 */
  67#define CONFIG_DOS_PARTITION
  68#define CONFIG_BZIP2
  69
  70/*
  71 * Video
  72 */
  73
  74#ifdef CONFIG_VIDEO
  75#define CONFIG_VIDEO_MB862xx
  76#define CONFIG_VIDEO_MB862xx_ACCEL
  77#define CONFIG_VIDEO_CORALP
  78#define CONFIG_VIDEO_LOGO
  79#define CONFIG_VIDEO_BMP_LOGO
  80#define CONFIG_SPLASH_SCREEN
  81#define CONFIG_VIDEO_BMP_GZIP
  82#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  83
  84/* Coral-PA clock frequency, geo and other both 133MHz */
  85#define CONFIG_SYS_MB862xx_CCF  0x00050000
  86/* Video SDRAM parameters */
  87#define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
  88#endif
  89
  90/*
  91 * Command line configuration.
  92 */
  93#ifdef CONFIG_VIDEO
  94#define CONFIG_CMD_BMP
  95#endif
  96#define CONFIG_CMD_DATE
  97#define CONFIG_CMD_DIAG
  98#define CONFIG_CMD_EEPROM
  99#define CONFIG_CMD_IDE
 100#define CONFIG_CMD_IRQ
 101#define CONFIG_CMD_PCI
 102#define CONFIG_CMD_REGINFO
 103#define CONFIG_CMD_SAVES
 104
 105#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
 106#define CONFIG_SYS_LOWBOOT      1
 107#endif
 108
 109/*
 110 * Autobooting
 111 */
 112
 113#undef  CONFIG_BOOTARGS
 114
 115#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 116        "fw_image=digsyMPC.img\0"                                       \
 117        "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
 118        "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
 119                "do mtc led $x; done\0"                                 \
 120        "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
 121                "else run mtcb_fw; fi\0"                                \
 122        "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
 123                "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
 124        "mtcb_update=mtc led user1 orange;"                             \
 125                "while mtc key; do ; done; run mtcb_2;\0"               \
 126        "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
 127        "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
 128                "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
 129        "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
 130                "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
 131        "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
 132                "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
 133        "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
 134                "source 400000; else run mtcb_error; fi\0"              \
 135        "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
 136        "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
 137                "else run mtcb_error; fi\0"                             \
 138        "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
 139                "run mtcb_checkfw\0"                                    \
 140        "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
 141                "else run mtcb_error; fi\0"                             \
 142        "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
 143        "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
 144        "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
 145        "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
 146        "mtcb_error=mtc led user1 red\0"                                \
 147        "mtcb_clear=erase ff000000 ff0fffff\0"                          \
 148        "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
 149        "mtcb_success=mtc led user1 green\0"                            \
 150        "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
 151                "then run mtcb_doide; else run mtcb_error; fi\0"        \
 152        "mtcb_doide=mtc led user2 green 1;"                             \
 153                "run mtcb_wait_flickr mtcb_di_1;\0"                     \
 154        "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
 155                "else run mtcb_error; fi\0"                             \
 156        "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
 157        "ramdisk_num_sector=16\0"                                       \
 158        "flash_base=ff000000\0"                                         \
 159        "flashdisk_size=e00000\0"                                       \
 160        "env_sector=fff60000\0"                                         \
 161        "flashdisk_start=ff100000\0"                                    \
 162        "load_cmd=tftp 400000 digsyMPC.img\0"                           \
 163        "clear_cmd=erase ff000000 ff0fffff\0"                           \
 164        "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
 165        "update_cmd=run load_cmd; "                                     \
 166        "iminfo 400000; "                                               \
 167        "run clear_cmd flash_cmd; "                                     \
 168        "iminfo ff000000\0"                                             \
 169        "spi_driver=yes\0"                                              \
 170        "spi_watchdog=no\0"                                             \
 171        "ftps_start=yes\0"                                              \
 172        "ftps_user1=admin\0"                                            \
 173        "ftps_pass1=admin\0"                                            \
 174        "ftps_base1=/\0"                                                \
 175        "ftps_home1=/\0"                                                \
 176        "plc_sio_srv=no\0"                                              \
 177        "plc_sio_baud=57600\0"                                          \
 178        "plc_sio_parity=no\0"                                           \
 179        "plc_sio_stop=1\0"                                              \
 180        "plc_sio_com=2\0"                                               \
 181        "plc_eth_srv=yes\0"                                             \
 182        "plc_eth_port=1200\0"                                           \
 183        "plc_root=/ide/\0"                                              \
 184        "diag_level=0\0"                                                \
 185        "webvisu=no\0"                                                  \
 186        "plc_can1_routing=no\0"                                         \
 187        "plc_can1_baudrate=250\0"                                       \
 188        "plc_can2_routing=no\0"                                         \
 189        "plc_can2_baudrate=250\0"                                       \
 190        "plc_can3_routing=no\0"                                         \
 191        "plc_can3_baudrate=250\0"                                       \
 192        "plc_can4_routing=no\0"                                         \
 193        "plc_can4_baudrate=250\0"                                       \
 194        "netdev=eth0\0"                                                 \
 195        "console=ttyPSC0\0"                                             \
 196        "kernel_addr_r=400000\0"                                        \
 197        "fdt_addr_r=600000\0"                                           \
 198        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 199        "nfsroot=${serverip}:${rootpath}\0"                             \
 200        "addip=setenv bootargs ${bootargs} "                            \
 201        "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 202        "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 203        "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
 204        "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 205        "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 206                "tftp ${fdt_addr_r} ${fdt_file};"                       \
 207                "run nfsargs addip addcons;"                            \
 208                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 209        "load=tftp 200000 ${u-boot}\0"                                  \
 210        "update=protect off FFF00000 +${filesize};"                     \
 211                "erase FFF00000 +${filesize};"                          \
 212                "cp.b 200000 FFF00000 ${filesize};"                     \
 213                "protect on FFF00000 +${filesize}\0"                    \
 214        ""
 215
 216#define CONFIG_BOOTCOMMAND      "run mtcb_start"
 217
 218/*
 219 * I2C configuration
 220 */
 221#define CONFIG_HARD_I2C         1
 222#define CONFIG_SYS_I2C_MODULE   1
 223#define CONFIG_SYS_I2C_SPEED    100000
 224#define CONFIG_SYS_I2C_SLAVE    0x7F
 225
 226/*
 227 * EEPROM configuration
 228 */
 229#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 230#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 231#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 232#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 233
 234/*
 235 * RTC configuration
 236 */
 237#if defined(CONFIG_DIGSY_REV5)
 238#define CONFIG_SYS_I2C_RTC_ADDR 0x56
 239#define CONFIG_RTC_RV3029
 240/* Enable 5k Ohm trickle charge resistor */
 241#define CONFIG_SYS_RV3029_TCR   0x20
 242#else
 243#define CONFIG_RTC_DS1337
 244#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 245#define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
 246#endif
 247
 248/*
 249 * Flash configuration
 250 */
 251#define CONFIG_SYS_FLASH_CFI            1
 252#define CONFIG_FLASH_CFI_DRIVER 1
 253
 254#if defined(CONFIG_DIGSY_REV5)
 255#define CONFIG_SYS_FLASH_BASE           0xFE000000
 256#define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
 257#define CONFIG_SYS_MAX_FLASH_BANKS      2
 258#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 259                                        CONFIG_SYS_FLASH_BASE_CS1}
 260#define CONFIG_SYS_UPDATE_FLASH_SIZE
 261#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 262#else
 263#define CONFIG_SYS_FLASH_BASE           0xFF000000
 264#define CONFIG_SYS_MAX_FLASH_BANKS      1
 265#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 266#endif
 267
 268#define CONFIG_SYS_MAX_FLASH_SECT       256
 269#define CONFIG_FLASH_16BIT
 270#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 271#define CONFIG_SYS_FLASH_SIZE   0x01000000
 272#define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 273#define CONFIG_SYS_FLASH_WRITE_TOUT     500
 274
 275#define OF_CPU                  "PowerPC,5200@0"
 276#define OF_SOC                  "soc5200@f0000000"
 277#define OF_TBCLK                (bd->bi_busfreq / 4)
 278
 279#define CONFIG_BOARD_EARLY_INIT_R
 280#define CONFIG_MISC_INIT_R
 281
 282/*
 283 * Environment settings
 284 */
 285#define CONFIG_ENV_IS_IN_FLASH  1
 286#if defined(CONFIG_LOWBOOT)
 287#define CONFIG_ENV_ADDR         0xFF060000
 288#else   /* CONFIG_LOWBOOT */
 289#define CONFIG_ENV_ADDR         0xFFF60000
 290#endif  /* CONFIG_LOWBOOT */
 291#define CONFIG_ENV_SIZE         0x10000
 292#define CONFIG_ENV_SECT_SIZE    0x20000
 293#define CONFIG_ENV_OVERWRITE    1
 294
 295/*
 296 * Memory map
 297 */
 298#define CONFIG_SYS_MBAR         0xF0000000
 299#define CONFIG_SYS_SDRAM_BASE           0x00000000
 300#if !defined(CONFIG_SYS_LOWBOOT)
 301#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 302#else
 303#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
 304#endif
 305
 306/*
 307 *  Use SRAM until RAM will be available
 308 */
 309#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 310#define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 311
 312#define CONFIG_SYS_GBL_DATA_OFFSET      \
 313        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 314#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 315
 316#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 317#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 318#define CONFIG_SYS_RAMBOOT              1
 319#endif
 320
 321#define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 322#define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
 323#define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 324
 325/*
 326 * Ethernet configuration
 327 */
 328#define CONFIG_MPC5xxx_FEC      1
 329#define CONFIG_MPC5xxx_FEC_MII100
 330#if defined(CONFIG_DIGSY_REV5)
 331#define CONFIG_PHY_ADDR         0x01
 332#else
 333#define CONFIG_PHY_ADDR         0x00
 334#endif
 335#define CONFIG_PHY_RESET_DELAY  1000
 336
 337#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 338
 339/*
 340 * GPIO configuration
 341 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 342 *  Bit 0   (mask 0x80000000) : 0x1
 343 * SPI on Tmr2/3/4/5 pins
 344 *  Bit 2:3 (mask 0x30000000) : 0x2
 345 * ATA cs0/1 on csb_4/5
 346 *  Bit 6:7 (mask 0x03000000) : 0x2
 347 * Ethernet 100Mbit with MD
 348 *  Bits 12:15 (mask 0x000f0000): 0x5
 349 * USB - Two UARTs
 350 *  Bits 18:19 (mask 0x00003000) : 0x2
 351 * PSC3 - USB2 on PSC3
 352 *  Bits 20:23 (mask 0x00000f00) : 0x1
 353 * PSC2 - CAN1&2 on PSC2 pins
 354 *  Bits 25:27 (mask 0x00000070) : 0x1
 355 * PSC1 - AC97 functionality
 356 *  Bits 29:31 (mask 0x00000007) : 0x2
 357 */
 358#define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
 359
 360/*
 361 * Miscellaneous configurable options
 362 */
 363#define CONFIG_SYS_LONGHELP
 364#define CONFIG_AUTO_COMPLETE    1
 365#define CONFIG_CMDLINE_EDITING  1
 366
 367#define CONFIG_MX_CYCLIC        1
 368
 369#define CONFIG_SYS_CBSIZE               1024
 370#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 371#define CONFIG_SYS_MAXARGS              32
 372#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 373
 374#define CONFIG_SYS_ALT_MEMTEST
 375#define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
 376#define CONFIG_SYS_MEMTEST_START        0x00010000
 377#define CONFIG_SYS_MEMTEST_END          0x019fffff
 378
 379#define CONFIG_SYS_LOAD_ADDR            0x00100000
 380
 381/*
 382 * Various low-level settings
 383 */
 384#define CONFIG_SYS_SDRAM_CS1            1
 385#define CONFIG_SYS_XLB_PIPELINING       1
 386
 387#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 388#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 389
 390#if defined(CONFIG_SYS_LOWBOOT)
 391#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 392#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 393#define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 394#endif
 395
 396#define CONFIG_SYS_CS4_START            0x60000000
 397#define CONFIG_SYS_CS4_SIZE             0x1000
 398#define CONFIG_SYS_CS4_CFG              0x0008FC00
 399
 400#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 401#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 402#define CONFIG_SYS_CS0_CFG              0x0002DD00
 403
 404#if defined(CONFIG_DIGSY_REV5)
 405#define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
 406#define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 407#define CONFIG_SYS_CS1_CFG              0x0002DD00
 408#endif
 409
 410#define CONFIG_SYS_CS_BURST             0x00000000
 411#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
 412
 413#if !defined(CONFIG_SYS_LOWBOOT)
 414#define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 415#else
 416#define CONFIG_SYS_RESET_ADDRESS        0xff000100
 417#endif
 418
 419/*
 420 * USB
 421 */
 422#define CONFIG_USB_OHCI_NEW
 423#define CONFIG_SYS_OHCI_BE_CONTROLLER
 424
 425#define CONFIG_USB_CLOCK        0x00013333
 426#define CONFIG_USB_CONFIG       0x00002000
 427
 428#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 429#define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 430#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 431#define CONFIG_SYS_USB_OHCI_CPU_INIT
 432
 433/*
 434 * IDE/ATA
 435 */
 436#define CONFIG_IDE_RESET
 437#define CONFIG_IDE_PREINIT
 438
 439#define CONFIG_SYS_ATA_CS_ON_I2C2
 440#define CONFIG_SYS_IDE_MAXBUS           1
 441#define CONFIG_SYS_IDE_MAXDEVICE        1
 442
 443#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 444#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 445#define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 446#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 447#define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 448#define CONFIG_SYS_ATA_STRIDE           4
 449
 450#define CONFIG_ATAPI            1
 451#define CONFIG_LBA48            1
 452
 453#endif /* __CONFIG_H */
 454