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8#ifndef _CONFIG_KMP204X_H
9#define _CONFIG_KMP204X_H
10
11#define CONFIG_SYS_TEXT_BASE 0xfff40000
12
13#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
14
15
16
17#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
18
19#define CONFIG_NAND_ECC_BCH
20
21
22#include "keymile-common.h"
23
24#define CONFIG_SYS_RAMBOOT
25#define CONFIG_RAMBOOT_PBL
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
29#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
30
31
32#define CONFIG_SYS_BOOK3E_HV
33#define CONFIG_FSL_CORENET
34#define CONFIG_MP
35
36#define CONFIG_SYS_FSL_CPC
37#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
38#define CONFIG_FSL_ELBC
39#define CONFIG_PCIE1
40#define CONFIG_PCIE3
41#define CONFIG_FSL_PCI_INIT
42#define CONFIG_SYS_PCI_64BIT
43
44#define CONFIG_SYS_DPAA_RMAN
45
46
47#define CONFIG_SYS_EXTRA_ENV_RELOC
48#define CONFIG_ENV_IS_IN_SPI_FLASH
49#define CONFIG_ENV_SPI_BUS 0
50#define CONFIG_ENV_SPI_CS 0
51#define CONFIG_ENV_SPI_MAX_HZ 20000000
52#define CONFIG_ENV_SPI_MODE 0
53#define CONFIG_ENV_OFFSET 0x100000
54#define CONFIG_ENV_SIZE 0x004000
55#define CONFIG_ENV_SECT_SIZE 0x010000
56#define CONFIG_ENV_OFFSET_REDUND 0x110000
57#define CONFIG_ENV_TOTAL_SIZE 0x020000
58
59#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
60
61#ifndef __ASSEMBLY__
62unsigned long get_board_sys_clk(unsigned long dummy);
63#endif
64#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
65
66
67
68
69#define CONFIG_SYS_CACHE_STASHING
70#define CONFIG_BACKSIDE_L2_CACHE
71#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
72#define CONFIG_BTB
73
74#define CONFIG_ENABLE_36BIT_PHYS
75
76#define CONFIG_ADDR_MAP
77#define CONFIG_SYS_NUM_ADDR_MAP 64
78
79#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
80
81
82
83
84#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
85#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
86 CONFIG_RAMBOOT_TEXT_BASE)
87#define CONFIG_SYS_L3_SIZE (1024 << 10)
88#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
89
90#define CONFIG_SYS_DCSRBAR 0xf0000000
91#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
92
93
94
95
96#define CONFIG_VERY_BIG_RAM
97#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99
100#define CONFIG_DIMM_SLOTS_PER_CTLR 1
101#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
102
103#define CONFIG_DDR_SPD
104#define CONFIG_FSL_DDR_INTERACTIVE
105
106#define CONFIG_SYS_SPD_BUS_NUM 0
107#define SPD_EEPROM_ADDRESS 0x54
108#define CONFIG_SYS_SDRAM_SIZE 4096
109
110#define CONFIG_SYS_LOAD_ADDR 0x100000
111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
112
113
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117
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123
124
125
126
127#define CONFIG_KM_ROOTFSSIZE 0x0
128
129#define CONFIG_KM_PNVRAM 0x80000
130
131#define CONFIG_KM_PHRAM 0x100000
132
133
134#define CONFIG_KM_RESERVED_PRAM 0x1000
135
136
137#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
138
139#define CONFIG_KM_CRAMFS_ADDR 0x2000000
140#define CONFIG_KM_KERNEL_ADDR 0x1000000
141#define CONFIG_KM_FDT_ADDR 0x1F80000
142
143
144
145
146
147
148#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
149
150
151#define CONFIG_NAND_FSL_ELBC
152#define CONFIG_SYS_NAND_BASE 0xffa00000
153#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
154
155#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
156#define CONFIG_SYS_MAX_NAND_DEVICE 1
157#define CONFIG_CMD_NAND
158#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
159
160#define CONFIG_BCH
161
162
163#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
164 | BR_PS_8 \
165 | BR_MS_FCM \
166 | BR_V)
167
168#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
169 | OR_FCM_BCTLD \
170 | OR_FCM_SCY_1 \
171 | OR_FCM_RST \
172 | OR_FCM_PGS \
173 | OR_FCM_CST)
174
175#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
176#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
177
178
179#define CONFIG_SYS_QRIO_BASE 0xfb000000
180#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
181
182#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
183 | BR_PS_8 \
184 | BR_DECC_OFF \
185 | BR_MS_GPCM \
186 | BR_V)
187
188#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB \
189 | OR_GPCM_BCTLD \
190 | OR_GPCM_ACS_DIV4 \
191 | OR_GPCM_SCY_2 \
192 | OR_GPCM_TRLX \
193 | OR_GPCM_EAD)
194
195#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM
196#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM
197
198
199#define CONFIG_BOOTCOUNT_LIMIT
200#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
201
202#define CONFIG_BOARD_EARLY_INIT_F
203#define CONFIG_BOARD_EARLY_INIT_R
204#define CONFIG_MISC_INIT_F
205#define CONFIG_MISC_INIT_R
206#define CONFIG_LAST_STAGE_INIT
207
208#define CONFIG_HWCONFIG
209
210
211#define CONFIG_L1_INIT_RAM
212#define CONFIG_SYS_INIT_RAM_LOCK
213#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
214#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
215#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
216
217#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
218 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
219 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
220#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
221
222#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
223 GENERATED_GBL_DATA_SIZE)
224#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
225
226#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
227#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
228#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
229
230
231
232
233
234#define CONFIG_CONS_INDEX 1
235#define CONFIG_SYS_NS16550_SERIAL
236#define CONFIG_SYS_NS16550_REG_SIZE 1
237#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
238
239#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
240#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
241#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
242#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
243
244#define CONFIG_KM_CONSOLE_TTY "ttyS0"
245
246
247
248#define CONFIG_SYS_I2C
249#define CONFIG_SYS_I2C_INIT_BOARD
250#define CONFIG_SYS_I2C_SPEED 100000
251#define CONFIG_SYS_NUM_I2C_BUSES 3
252#define CONFIG_SYS_I2C_MAX_HOPS 1
253#define CONFIG_SYS_I2C_FSL
254#define CONFIG_I2C_MULTI_BUS
255#define CONFIG_I2C_CMD_TREE
256#define CONFIG_SYS_FSL_I2C_SPEED 400000
257#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
258#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
259#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
260 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
261 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
262 }
263#ifndef __ASSEMBLY__
264void set_sda(int state);
265void set_scl(int state);
266int get_sda(void);
267int get_scl(void);
268#endif
269
270#define CONFIG_KM_IVM_BUS 1
271
272
273
274
275#define CONFIG_SPI_FLASH_BAR
276#define CONFIG_SF_DEFAULT_SPEED 20000000
277#define CONFIG_SF_DEFAULT_MODE 0
278
279
280
281
282
283
284
285#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
286#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
287#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
288#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
289#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
290#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
291#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
292#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
293
294
295#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
296#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
297#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
298#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
299#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
300#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
301#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
302#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
303
304
305#define CONFIG_SYS_DPAA_QBMAN
306#define CONFIG_SYS_BMAN_NUM_PORTALS 10
307#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
308#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
309#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
310#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
311#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
312#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
313#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
314#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
315 CONFIG_SYS_BMAN_CENA_SIZE)
316#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
317#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
318#define CONFIG_SYS_QMAN_NUM_PORTALS 10
319#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
320#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
321#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
322#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
323#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
324#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
325#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
326#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
327 CONFIG_SYS_QMAN_CENA_SIZE)
328#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
329#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
330
331#define CONFIG_SYS_DPAA_FMAN
332#define CONFIG_SYS_DPAA_PME
333
334
335
336
337#define CONFIG_SYS_QE_FW_IN_SPIFLASH
338#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
339#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
340#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
341
342#define CONFIG_FMAN_ENET
343#define CONFIG_PHYLIB_10G
344#define CONFIG_PHY_MARVELL
345
346#define CONFIG_PCI_INDIRECT_BRIDGE
347
348#define CONFIG_PCI_SCAN_SHOW
349#define CONFIG_DOS_PARTITION
350
351
352#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
353#define CONFIG_SYS_TBIPA_VALUE 8
354#define CONFIG_PHYLIB
355#define CONFIG_ETHPRIME "FM1@DTSEC5"
356#define CONFIG_PHY_GIGE
357
358
359
360
361#define CONFIG_LOADS_ECHO
362#define CONFIG_SYS_LOADS_BAUD_CHANGE
363
364
365
366
367#define CONFIG_WATCHDOG
368#define CONFIG_WATCHDOG_PRESC 34
369#define CONFIG_WATCHDOG_RC WRC_CHIP
370
371
372
373
374
375#define CONFIG_CMD_PCI
376#define CONFIG_CMD_ERRATA
377
378
379#define CONFIG_SYS_NO_FLASH
380#undef CONFIG_FLASH_CFI_MTD
381#undef CONFIG_JFFS2_CMDLINE
382
383
384
385
386
387
388#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
389#define CONFIG_SYS_BOOTM_LEN (64 << 20)
390
391#ifdef CONFIG_CMD_KGDB
392#define CONFIG_KGDB_BAUDRATE 230400
393#endif
394
395#define __USB_PHY_TYPE utmi
396#define CONFIG_USB_EHCI_FSL
397
398
399
400
401#define CONFIG_ENV_OVERWRITE
402#ifndef CONFIG_KM_DEF_ENV
403#define CONFIG_KM_DEF_ENV "km-common=empty\0"
404#endif
405
406#ifndef MTDIDS_DEFAULT
407# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
408#endif
409
410#ifndef MTDPARTS_DEFAULT
411# define MTDPARTS_DEFAULT "mtdparts=" \
412 "fsl_elbc_nand:" \
413 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
414#endif
415
416
417#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
418
419
420#define CONFIG_KM_DEF_ENV_CPU \
421 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
422 "cramfsloadfdt=" \
423 "cramfsload ${fdt_addr_r} " \
424 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
425 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
426 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
427 "update=" \
428 "sf probe 0;sf erase 0 +${filesize};" \
429 "sf write ${load_addr_r} 0 ${filesize};\0" \
430 "set_fdthigh=true\0" \
431 "checkfdt=true\0" \
432 ""
433
434#define CONFIG_HW_ENV_SETTINGS \
435 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
436 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
437 "usb_dr_mode=host\0"
438
439#define CONFIG_KM_NEW_ENV \
440 "newenv=sf probe 0;" \
441 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
442 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
443
444
445#ifndef CONFIG_KM_DEF_ARCH
446#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
447#endif
448
449#define CONFIG_EXTRA_ENV_SETTINGS \
450 CONFIG_KM_DEF_ENV \
451 CONFIG_KM_DEF_ARCH \
452 CONFIG_KM_NEW_ENV \
453 CONFIG_HW_ENV_SETTINGS \
454 "EEprom_ivm=pca9547:70:9\0" \
455 ""
456
457#endif
458