LXR uboot/include/configs/makalu.h

   1/*
   2 * Copyright (c) 2008 Nuovation System Designs, LLC
   3 *   Grant Erickson <gerickson@nuovations.com>
   4 *
   5 * (C) Copyright 2007-2008
   6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11/************************************************************************
  12 * makalu.h - configuration for AMCC Makalu (405EX)
  13 ***********************************************************************/
  14
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*-----------------------------------------------------------------------
  19 * High Level Configuration Options
  20 *----------------------------------------------------------------------*/
  21#define CONFIG_MAKALU           1               /* Board is Makalu      */
  22#define CONFIG_405EX            1               /* Specifc 405EX support*/
  23#define CONFIG_SYS_CLK_FREQ     33330000        /* ext frequency to pll */
  24
  25#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  26
  27/*
  28 * Include common defines/options for all AMCC eval boards
  29 */
  30#define CONFIG_HOSTNAME makalu
  31#define CONFIG_ADDMISC  "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
  32#include "amcc-common.h"
  33
  34#define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  35#define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  36
  37/*-----------------------------------------------------------------------
  38 * Base addresses -- Note these are effective addresses where the
  39 * actual resources get mapped (not physical addresses)
  40 *----------------------------------------------------------------------*/
  41#define CONFIG_SYS_FLASH_BASE           0xFC000000
  42#define CONFIG_SYS_FPGA_BASE            0xF0000000
  43
  44/*-----------------------------------------------------------------------
  45 * Initial RAM & Stack Pointer Configuration Options
  46 *
  47 *   There are traditionally three options for the primordial
  48 *   (i.e. initial) stack usage on the 405-series:
  49 *
  50 *      1) On-chip Memory (OCM) (i.e. SRAM)
  51 *      2) Data cache
  52 *      3) SDRAM
  53 *
  54 *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  55 *   the latter of which is less than desireable since it requires
  56 *   setting up the SDRAM and ECC in assembly code.
  57 *
  58 *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  59 *   select on the External Bus Controller (EBC) and then select a
  60 *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  61 *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  62 *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  63 *   physical SDRAM to use (3).
  64 *-----------------------------------------------------------------------*/
  65
  66#define CONFIG_SYS_INIT_DCACHE_CS       4
  67
  68#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  69#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  70#else
  71#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  72#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  73
  74#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
  75#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  76
  77/*
  78 * If the data cache is being used for the primordial stack and global
  79 * data area, the POST word must be placed somewhere else. The General
  80 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  81 * its compare and mask register contents across reset, so it is used
  82 * for the POST word.
  83 */
  84
  85#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  86# define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
  87# define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  88#else
  89# define CONFIG_SYS_INIT_EXTRA_SIZE     16
  90# define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
  91# define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
  92#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  93
  94/*-----------------------------------------------------------------------
  95 * Serial Port
  96 *----------------------------------------------------------------------*/
  97#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  98#undef CONFIG_SYS_EXT_SERIAL_CLOCK                      /* no ext. clk          */
  99
 100/*-----------------------------------------------------------------------
 101 * Environment
 102 *----------------------------------------------------------------------*/
 103#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 104
 105/*-----------------------------------------------------------------------
 106 * FLASH related
 107 *----------------------------------------------------------------------*/
 108#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 109#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 110
 111#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 112#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 113#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 114
 115#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 116#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 117
 118#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 119#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 120
 121#ifdef CONFIG_ENV_IS_IN_FLASH
 122#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 123#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 124#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 125
 126/* Address and size of Redundant Environment Sector     */
 127#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 128#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 129#endif /* CONFIG_ENV_IS_IN_FLASH */
 130
 131/*-----------------------------------------------------------------------
 132 * DDR SDRAM
 133 *----------------------------------------------------------------------*/
 134#define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 135
 136#define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 137#define CONFIG_SYS_SDRAM0_MB1CF_BASE    ((128 << 20) + CONFIG_SYS_SDRAM_BASE)
 138
 139/* DDR1/2 SDRAM Device Control Register Data Values */
 140#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 141                                 SDRAM_RXBAS_SDSZ_128MB         | \
 142                                 SDRAM_RXBAS_SDAM_MODE2         | \
 143                                 SDRAM_RXBAS_SDBE_ENABLE)
 144#define CONFIG_SYS_SDRAM0_MB1CF ((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3)    | \
 145                                 SDRAM_RXBAS_SDSZ_128MB         | \
 146                                 SDRAM_RXBAS_SDAM_MODE2         | \
 147                                 SDRAM_RXBAS_SDBE_ENABLE)
 148#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 149#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 150#define CONFIG_SYS_SDRAM0_MCOPT1        0x04322000
 151#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 152#define CONFIG_SYS_SDRAM0_MODT0 0x01800000
 153#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 154#define CONFIG_SYS_SDRAM0_CODT          0x0080f837
 155#define CONFIG_SYS_SDRAM0_RTR           0x06180000
 156#define CONFIG_SYS_SDRAM0_INITPLR0      0xa8380000
 157#define CONFIG_SYS_SDRAM0_INITPLR1      0x81900400
 158#define CONFIG_SYS_SDRAM0_INITPLR2      0x81020000
 159#define CONFIG_SYS_SDRAM0_INITPLR3      0x81030000
 160#define CONFIG_SYS_SDRAM0_INITPLR4      0x81010404
 161#define CONFIG_SYS_SDRAM0_INITPLR5      0x81000542
 162#define CONFIG_SYS_SDRAM0_INITPLR6      0x81900400
 163#define CONFIG_SYS_SDRAM0_INITPLR7      0x8D080000
 164#define CONFIG_SYS_SDRAM0_INITPLR8      0x8D080000
 165#define CONFIG_SYS_SDRAM0_INITPLR9      0x8D080000
 166#define CONFIG_SYS_SDRAM0_INITPLR10     0x8D080000
 167#define CONFIG_SYS_SDRAM0_INITPLR11     0x81000442
 168#define CONFIG_SYS_SDRAM0_INITPLR12     0x81010780
 169#define CONFIG_SYS_SDRAM0_INITPLR13     0x81010400
 170#define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 171#define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 172#define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 173#define CONFIG_SYS_SDRAM0_RFDC          0x00000209
 174#define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 175#define CONFIG_SYS_SDRAM0_DLCR          0x030000a5
 176#define CONFIG_SYS_SDRAM0_CLKTR 0x80000000
 177#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 178#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
 179#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
 180#define CONFIG_SYS_SDRAM0_SDTR3 0x080b0d1a
 181#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
 182#define CONFIG_SYS_SDRAM0_MEMODE        0x00000404
 183
 184/*-----------------------------------------------------------------------
 185 * I2C
 186 *----------------------------------------------------------------------*/
 187#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 188
 189#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   6       /* 24C02 requires 5ms delay */
 190#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 191#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 192
 193/* Standard DTT sensor configuration */
 194#define CONFIG_DTT_DS1775       1
 195#define CONFIG_DTT_SENSORS      { 0 }
 196#define CONFIG_SYS_I2C_DTT_ADDR 0x48
 197
 198/* RTC configuration */
 199#define CONFIG_RTC_X1205        1
 200#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
 201
 202/*-----------------------------------------------------------------------
 203 * Ethernet
 204 *----------------------------------------------------------------------*/
 205#define CONFIG_M88E1111_PHY     1
 206#define CONFIG_IBM_EMAC4_V4     1
 207#define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 208#define CONFIG_PHY_ADDR         6       /* PHY address, See schematics  */
 209
 210#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 211#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 212
 213#define CONFIG_HAS_ETH0         1
 214
 215#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 216#define CONFIG_PHY1_ADDR        0
 217
 218/*
 219 * Default environment variables
 220 */
 221#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 222        CONFIG_AMCC_DEF_ENV                                             \
 223        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 224        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 225        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 226        "kernel_addr=fc000000\0"                                        \
 227        "fdt_addr=fc1e0000\0"                                           \
 228        "ramdisk_addr=fc200000\0"                                       \
 229        "pciconfighost=1\0"                                             \
 230        "pcie_mode=RP:RP\0"                                             \
 231        ""
 232
 233/*
 234 * Commands additional to the ones defined in amcc-common.h
 235 */
 236#define CONFIG_CMD_DATE
 237#define CONFIG_CMD_DTT
 238#define CONFIG_CMD_PCI
 239
 240/* POST support */
 241#define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 242                                 CONFIG_SYS_POST_CPU            | \
 243                                 CONFIG_SYS_POST_ETHER          | \
 244                                 CONFIG_SYS_POST_I2C            | \
 245                                 CONFIG_SYS_POST_MEMORY | \
 246                                 CONFIG_SYS_POST_UART)
 247
 248/* Define here the base-addresses of the UARTs to test in POST */
 249#define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 250                        CONFIG_SYS_NS16550_COM2 }
 251
 252#define CONFIG_LOGBUFFER
 253#define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 254
 255/*-----------------------------------------------------------------------
 256 * PCI stuff
 257 *----------------------------------------------------------------------*/
 258#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 259#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 260#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 261
 262/*-----------------------------------------------------------------------
 263 * PCIe stuff
 264 *----------------------------------------------------------------------*/
 265#define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 266#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 267
 268#define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 269#define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 270#define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 271
 272#define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 273#define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 274#define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 275
 276#define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 277#define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 278
 279/* base address of inbound PCIe window */
 280#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 281
 282/*-----------------------------------------------------------------------
 283 * External Bus Controller (EBC) Setup
 284 *----------------------------------------------------------------------*/
 285/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 286#define CONFIG_SYS_EBC_PB0AP            0x08033700
 287#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 288
 289/* Memory Bank 2 (CPLD) initialization                                          */
 290#define CONFIG_SYS_EBC_PB2AP           0x9400C800
 291#define CONFIG_SYS_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit   */
 292
 293#define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 294
 295/*-----------------------------------------------------------------------
 296 * GPIO Setup
 297 *----------------------------------------------------------------------*/
 298#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 299{                                                                                       \
 300/* GPIO Core 0 */                                                                       \
 301{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 302{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 303{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 304{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 305{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 306{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 307{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 308{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 309{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 310{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 311{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 312{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 313{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 314{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 315{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 316{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 317{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 318{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 319{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 320{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 321{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 322{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 323{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 324{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 325{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 326{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 327{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 328{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 329{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28                                */      \
 330{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 331{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 332{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 333}                                                                                               \
 334}
 335
 336#define CONFIG_SYS_GPIO_PCIE_RST        23
 337#define CONFIG_SYS_GPIO_PCIE_CLKREQ     27
 338#define CONFIG_SYS_GPIO_PCIE_WAKE       28
 339
 340#endif  /* __CONFIG_H */
 341