1/* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __MX6QSABREAUTO_CONFIG_H 10#define __MX6QSABREAUTO_CONFIG_H 11 12#define CONFIG_MACH_TYPE 3529 13#define CONFIG_MXC_UART_BASE UART4_BASE 14#define CONSOLE_DEV "ttymxc3" 15#define CONFIG_MMCROOT "/dev/mmcblk0p2" 16 17/* USB Configs */ 18#define CONFIG_USB_EHCI 19#define CONFIG_USB_EHCI_MX6 20#define CONFIG_USB_HOST_ETHER 21#define CONFIG_USB_ETHER_ASIX 22#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 23#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 24#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 25#define CONFIG_MXC_USB_FLAGS 0 26 27#define CONFIG_PCA953X 28#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 29 30#include "mx6sabre_common.h" 31 32#undef CONFIG_SYS_NO_FLASH 33#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 34#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 35#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 36#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 37#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 38#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 39#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 40#define CONFIG_SYS_FLASH_EMPTY_INFO 41 42#define CONFIG_SYS_FSL_USDHC_NUM 2 43#if defined(CONFIG_ENV_IS_IN_MMC) 44#define CONFIG_SYS_MMC_ENV_DEV 0 45#endif 46 47/* I2C Configs */ 48#define CONFIG_SYS_I2C 49#define CONFIG_SYS_I2C_MXC 50#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 51#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 52#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 53#define CONFIG_SYS_I2C_SPEED 100000 54 55/* NAND flash command */ 56#define CONFIG_CMD_NAND 57#define CONFIG_CMD_NAND_TRIMFFS 58 59/* NAND stuff */ 60#define CONFIG_NAND_MXS 61#define CONFIG_SYS_MAX_NAND_DEVICE 1 62#define CONFIG_SYS_NAND_BASE 0x40000000 63#define CONFIG_SYS_NAND_5_ADDR_CYCLE 64#define CONFIG_SYS_NAND_ONFI_DETECTION 65 66/* DMA stuff, needed for GPMI/MXS NAND support */ 67#define CONFIG_APBH_DMA 68#define CONFIG_APBH_DMA_BURST 69#define CONFIG_APBH_DMA_BURST8 70 71/* PMIC */ 72#define CONFIG_POWER 73#define CONFIG_POWER_I2C 74#define CONFIG_POWER_PFUZE100 75#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 76 77#endif /* __MX6QSABREAUTO_CONFIG_H */ 78