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7#include <common.h>
8#include <config.h>
9#include <fuse.h>
10#include <asm/io.h>
11#include <asm/system.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/imx-common/hab.h>
15
16
17
18#define hab_rvt_report_event_p \
19( \
20 (is_mx6dqp()) ? \
21 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
22 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
23 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
24 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
25 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
26 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
27)
28
29#define hab_rvt_report_status_p \
30( \
31 (is_mx6dqp()) ? \
32 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
33 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
34 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
35 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
36 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
37 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
38)
39
40#define hab_rvt_authenticate_image_p \
41( \
42 (is_mx6dqp()) ? \
43 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
44 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
45 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
46 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
47 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
48 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
49)
50
51#define hab_rvt_entry_p \
52( \
53 (is_mx6dqp()) ? \
54 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
55 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
56 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
57 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
58 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
59 ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
60)
61
62#define hab_rvt_exit_p \
63( \
64 (is_mx6dqp()) ? \
65 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
66 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
67 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
68 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
69 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
70 ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
71)
72
73#define IVT_SIZE 0x20
74#define ALIGN_SIZE 0x1000
75#define CSF_PAD_SIZE 0x2000
76#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
77#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
78#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
79#define IS_HAB_ENABLED_BIT \
80 (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
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113static bool is_hab_enabled(void);
114
115#if !defined(CONFIG_SPL_BUILD)
116
117#define MAX_RECORD_BYTES (8*1024)
118
119struct record {
120 uint8_t tag;
121 uint8_t len[2];
122 uint8_t par;
123 uint8_t contents[MAX_RECORD_BYTES];
124 bool any_rec_flag;
125};
126
127char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
128 "RSN = HAB_ENG_FAIL (0x30)\n",
129 "RSN = HAB_INV_ADDRESS (0x22)\n",
130 "RSN = HAB_INV_ASSERTION (0x0C)\n",
131 "RSN = HAB_INV_CALL (0x28)\n",
132 "RSN = HAB_INV_CERTIFICATE (0x21)\n",
133 "RSN = HAB_INV_COMMAND (0x06)\n",
134 "RSN = HAB_INV_CSF (0x11)\n",
135 "RSN = HAB_INV_DCD (0x27)\n",
136 "RSN = HAB_INV_INDEX (0x0F)\n",
137 "RSN = HAB_INV_IVT (0x05)\n",
138 "RSN = HAB_INV_KEY (0x1D)\n",
139 "RSN = HAB_INV_RETURN (0x1E)\n",
140 "RSN = HAB_INV_SIGNATURE (0x18)\n",
141 "RSN = HAB_INV_SIZE (0x17)\n",
142 "RSN = HAB_MEM_FAIL (0x2E)\n",
143 "RSN = HAB_OVR_COUNT (0x2B)\n",
144 "RSN = HAB_OVR_STORAGE (0x2D)\n",
145 "RSN = HAB_UNS_ALGORITHM (0x12)\n",
146 "RSN = HAB_UNS_COMMAND (0x03)\n",
147 "RSN = HAB_UNS_ENGINE (0x0A)\n",
148 "RSN = HAB_UNS_ITEM (0x24)\n",
149 "RSN = HAB_UNS_KEY (0x1B)\n",
150 "RSN = HAB_UNS_PROTOCOL (0x14)\n",
151 "RSN = HAB_UNS_STATE (0x09)\n",
152 "RSN = INVALID\n",
153 NULL};
154
155char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
156 "STS = HAB_FAILURE (0x33)\n",
157 "STS = HAB_WARNING (0x69)\n",
158 "STS = INVALID\n",
159 NULL};
160
161char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
162 "ENG = HAB_ENG_SCC (0x03)\n",
163 "ENG = HAB_ENG_RTIC (0x05)\n",
164 "ENG = HAB_ENG_SAHARA (0x06)\n",
165 "ENG = HAB_ENG_CSU (0x0A)\n",
166 "ENG = HAB_ENG_SRTC (0x0C)\n",
167 "ENG = HAB_ENG_DCP (0x1B)\n",
168 "ENG = HAB_ENG_CAAM (0x1D)\n",
169 "ENG = HAB_ENG_SNVS (0x1E)\n",
170 "ENG = HAB_ENG_OCOTP (0x21)\n",
171 "ENG = HAB_ENG_DTCP (0x22)\n",
172 "ENG = HAB_ENG_ROM (0x36)\n",
173 "ENG = HAB_ENG_HDCP (0x24)\n",
174 "ENG = HAB_ENG_RTL (0x77)\n",
175 "ENG = HAB_ENG_SW (0xFF)\n",
176 "ENG = INVALID\n",
177 NULL};
178
179char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
180 "CTX = HAB_CTX_FAB (0xFF)\n",
181 "CTX = HAB_CTX_ENTRY (0xE1)\n",
182 "CTX = HAB_CTX_TARGET (0x33)\n",
183 "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
184 "CTX = HAB_CTX_DCD (0xDD)\n",
185 "CTX = HAB_CTX_CSF (0xCF)\n",
186 "CTX = HAB_CTX_COMMAND (0xC0)\n",
187 "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
188 "CTX = HAB_CTX_ASSERT (0xA0)\n",
189 "CTX = HAB_CTX_EXIT (0xEE)\n",
190 "CTX = INVALID\n",
191 NULL};
192
193uint8_t hab_statuses[5] = {
194 HAB_STS_ANY,
195 HAB_FAILURE,
196 HAB_WARNING,
197 HAB_SUCCESS,
198 -1
199};
200
201uint8_t hab_reasons[26] = {
202 HAB_RSN_ANY,
203 HAB_ENG_FAIL,
204 HAB_INV_ADDRESS,
205 HAB_INV_ASSERTION,
206 HAB_INV_CALL,
207 HAB_INV_CERTIFICATE,
208 HAB_INV_COMMAND,
209 HAB_INV_CSF,
210 HAB_INV_DCD,
211 HAB_INV_INDEX,
212 HAB_INV_IVT,
213 HAB_INV_KEY,
214 HAB_INV_RETURN,
215 HAB_INV_SIGNATURE,
216 HAB_INV_SIZE,
217 HAB_MEM_FAIL,
218 HAB_OVR_COUNT,
219 HAB_OVR_STORAGE,
220 HAB_UNS_ALGORITHM,
221 HAB_UNS_COMMAND,
222 HAB_UNS_ENGINE,
223 HAB_UNS_ITEM,
224 HAB_UNS_KEY,
225 HAB_UNS_PROTOCOL,
226 HAB_UNS_STATE,
227 -1
228};
229
230uint8_t hab_contexts[12] = {
231 HAB_CTX_ANY,
232 HAB_CTX_FAB,
233 HAB_CTX_ENTRY,
234 HAB_CTX_TARGET,
235 HAB_CTX_AUTHENTICATE,
236 HAB_CTX_DCD,
237 HAB_CTX_CSF,
238 HAB_CTX_COMMAND,
239 HAB_CTX_AUT_DAT,
240 HAB_CTX_ASSERT,
241 HAB_CTX_EXIT,
242 -1
243};
244
245uint8_t hab_engines[16] = {
246 HAB_ENG_ANY,
247 HAB_ENG_SCC,
248 HAB_ENG_RTIC,
249 HAB_ENG_SAHARA,
250 HAB_ENG_CSU,
251 HAB_ENG_SRTC,
252 HAB_ENG_DCP,
253 HAB_ENG_CAAM,
254 HAB_ENG_SNVS,
255 HAB_ENG_OCOTP,
256 HAB_ENG_DTCP,
257 HAB_ENG_ROM,
258 HAB_ENG_HDCP,
259 HAB_ENG_RTL,
260 HAB_ENG_SW,
261 -1
262};
263
264static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
265{
266 uint8_t idx = 0;
267 uint8_t element = list[idx];
268 while (element != -1) {
269 if (element == tgt)
270 return idx;
271 element = list[++idx];
272 }
273 return -1;
274}
275
276void process_event_record(uint8_t *event_data, size_t bytes)
277{
278 struct record *rec = (struct record *)event_data;
279
280 printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
281 printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
282 printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
283 printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
284}
285
286void display_event(uint8_t *event_data, size_t bytes)
287{
288 uint32_t i;
289
290 if (!(event_data && bytes > 0))
291 return;
292
293 for (i = 0; i < bytes; i++) {
294 if (i == 0)
295 printf("\t0x%02x", event_data[i]);
296 else if ((i % 8) == 0)
297 printf("\n\t0x%02x", event_data[i]);
298 else
299 printf(" 0x%02x", event_data[i]);
300 }
301
302 process_event_record(event_data, bytes);
303}
304
305int get_hab_status(void)
306{
307 uint32_t index = 0;
308 uint8_t event_data[128];
309 size_t bytes = sizeof(event_data);
310 enum hab_config config = 0;
311 enum hab_state state = 0;
312 hab_rvt_report_event_t *hab_rvt_report_event;
313 hab_rvt_report_status_t *hab_rvt_report_status;
314
315 hab_rvt_report_event = hab_rvt_report_event_p;
316 hab_rvt_report_status = hab_rvt_report_status_p;
317
318 if (is_hab_enabled())
319 puts("\nSecure boot enabled\n");
320 else
321 puts("\nSecure boot disabled\n");
322
323
324 if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
325 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
326 config, state);
327
328
329 while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
330 &bytes) == HAB_SUCCESS) {
331 puts("\n");
332 printf("--------- HAB Event %d -----------------\n",
333 index + 1);
334 puts("event data:\n");
335 display_event(event_data, bytes);
336 puts("\n");
337 bytes = sizeof(event_data);
338 index++;
339 }
340 }
341
342 else {
343 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
344 config, state);
345 puts("No HAB Events Found!\n\n");
346 }
347 return 0;
348}
349
350int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
351{
352 if ((argc != 1)) {
353 cmd_usage(cmdtp);
354 return 1;
355 }
356
357 get_hab_status();
358
359 return 0;
360}
361
362static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
363 char * const argv[])
364{
365 ulong addr, ivt_offset;
366 int rcode = 0;
367
368 if (argc < 3)
369 return CMD_RET_USAGE;
370
371 addr = simple_strtoul(argv[1], NULL, 16);
372 ivt_offset = simple_strtoul(argv[2], NULL, 16);
373
374 rcode = authenticate_image(addr, ivt_offset);
375
376 return rcode;
377}
378
379U_BOOT_CMD(
380 hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
381 "display HAB status",
382 ""
383 );
384
385U_BOOT_CMD(
386 hab_auth_img, 3, 0, do_authenticate_image,
387 "authenticate image via HAB",
388 "addr ivt_offset\n"
389 "addr - image hex address\n"
390 "ivt_offset - hex offset of IVT in the image"
391 );
392
393
394#endif
395
396static bool is_hab_enabled(void)
397{
398 struct imx_sec_config_fuse_t *fuse =
399 (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
400 uint32_t reg;
401 int ret;
402
403 ret = fuse_read(fuse->bank, fuse->word, ®);
404 if (ret) {
405 puts("\nSecure boot fuse read error\n");
406 return ret;
407 }
408
409 return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
410}
411
412uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
413{
414 uint32_t load_addr = 0;
415 size_t bytes;
416 ptrdiff_t ivt_offset = 0;
417 int result = 0;
418 ulong start;
419 hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
420 hab_rvt_entry_t *hab_rvt_entry;
421 hab_rvt_exit_t *hab_rvt_exit;
422
423 hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
424 hab_rvt_entry = hab_rvt_entry_p;
425 hab_rvt_exit = hab_rvt_exit_p;
426
427 if (is_hab_enabled()) {
428 printf("\nAuthenticate image from DDR location 0x%x...\n",
429 ddr_start);
430
431 hab_caam_clock_enable(1);
432
433 if (hab_rvt_entry() == HAB_SUCCESS) {
434
435 ivt_offset = (image_size + ALIGN_SIZE - 1) &
436 ~(ALIGN_SIZE - 1);
437
438 start = ddr_start;
439 bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
440#ifdef DEBUG
441 printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
442 ivt_offset, ddr_start + ivt_offset);
443 puts("Dumping IVT\n");
444 print_buffer(ddr_start + ivt_offset,
445 (void *)(ddr_start + ivt_offset),
446 4, 0x8, 0);
447
448 puts("Dumping CSF Header\n");
449 print_buffer(ddr_start + ivt_offset+IVT_SIZE,
450 (void *)(ddr_start + ivt_offset+IVT_SIZE),
451 4, 0x10, 0);
452
453#if !defined(CONFIG_SPL_BUILD)
454 get_hab_status();
455#endif
456
457 puts("\nCalling authenticate_image in ROM\n");
458 printf("\tivt_offset = 0x%x\n", ivt_offset);
459 printf("\tstart = 0x%08lx\n", start);
460 printf("\tbytes = 0x%x\n", bytes);
461#endif
462
463
464
465
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472
473 if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
474 if (is_mx6dq()) {
475
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477
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479
480
481 if (!is_mx6dqp())
482 writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
483 } else if (is_mx6sdl()) {
484 writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
485 } else if (is_mx6sl()) {
486 writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
487 }
488 }
489
490 load_addr = (uint32_t)hab_rvt_authenticate_image(
491 HAB_CID_UBOOT,
492 ivt_offset, (void **)&start,
493 (size_t *)&bytes, NULL);
494 if (hab_rvt_exit() != HAB_SUCCESS) {
495 puts("hab exit function fail\n");
496 load_addr = 0;
497 }
498 } else {
499 puts("hab entry function fail\n");
500 }
501
502 hab_caam_clock_enable(0);
503
504#if !defined(CONFIG_SPL_BUILD)
505 get_hab_status();
506#endif
507 } else {
508 puts("hab fuse not enabled\n");
509 }
510
511 if ((!is_hab_enabled()) || (load_addr != 0))
512 result = 1;
513
514 return result;
515}
516
