1/* 2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 3 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _IMX_REGS_H 9#define _IMX_REGS_H 10 11#include <asm/arch/regs-rtc.h> 12 13#ifndef __ASSEMBLY__ 14 15extern void imx_gpio_mode (int gpio_mode); 16 17#ifdef CONFIG_MXC_UART 18extern void mx27_uart1_init_pins(void); 19#endif /* CONFIG_MXC_UART */ 20 21#ifdef CONFIG_FEC_MXC 22extern void mx27_fec_init_pins(void); 23#endif /* CONFIG_FEC_MXC */ 24 25#ifdef CONFIG_MXC_MMC 26extern void mx27_sd1_init_pins(void); 27extern void mx27_sd2_init_pins(void); 28#endif /* CONFIG_MXC_MMC */ 29 30/* AIPI */ 31struct aipi_regs { 32 u32 psr0; 33 u32 psr1; 34}; 35 36/* System Control */ 37struct system_control_regs { 38 u32 res[5]; 39 u32 fmcr; 40 u32 gpcr; 41 u32 wbcr; 42 u32 dscr1; 43 u32 dscr2; 44 u32 dscr3; 45 u32 dscr4; 46 u32 dscr5; 47 u32 dscr6; 48 u32 dscr7; 49 u32 dscr8; 50 u32 dscr9; 51 u32 dscr10; 52 u32 dscr11; 53 u32 dscr12; 54 u32 dscr13; 55 u32 pscr; 56 u32 pmcr; 57 u32 res1; 58 u32 dcvr0; 59 u32 dcvr1; 60 u32 dcvr2; 61 u32 dcvr3; 62}; 63 64/* Chip Select Registers */ 65struct weim_regs { 66 u32 cs0u; /* Chip Select 0 Upper Register */ 67 u32 cs0l; /* Chip Select 0 Lower Register */ 68 u32 cs0a; /* Chip Select 0 Addition Register */ 69 u32 pad0; 70 u32 cs1u; /* Chip Select 1 Upper Register */ 71 u32 cs1l; /* Chip Select 1 Lower Register */ 72 u32 cs1a; /* Chip Select 1 Addition Register */ 73 u32 pad1; 74 u32 cs2u; /* Chip Select 2 Upper Register */ 75 u32 cs2l; /* Chip Select 2 Lower Register */ 76 u32 cs2a; /* Chip Select 2 Addition Register */ 77 u32 pad2; 78 u32 cs3u; /* Chip Select 3 Upper Register */ 79 u32 cs3l; /* Chip Select 3 Lower Register */ 80 u32 cs3a; /* Chip Select 3 Addition Register */ 81 u32 pad3; 82 u32 cs4u; /* Chip Select 4 Upper Register */ 83 u32 cs4l; /* Chip Select 4 Lower Register */ 84 u32 cs4a; /* Chip Select 4 Addition Register */ 85 u32 pad4; 86 u32 cs5u; /* Chip Select 5 Upper Register */ 87 u32 cs5l; /* Chip Select 5 Lower Register */ 88 u32 cs5a; /* Chip Select 5 Addition Register */ 89 u32 pad5; 90 u32 eim; /* WEIM Configuration Register */ 91}; 92 93/* SDRAM Controller registers */ 94struct esdramc_regs { 95/* Enhanced SDRAM Control Register 0 */ 96 u32 esdctl0; 97/* Enhanced SDRAM Configuration Register 0 */ 98 u32 esdcfg0; 99/* Enhanced SDRAM Control Register 1 */ 100 u32 esdctl1; 101/* Enhanced SDRAM Configuration Register 1 */ 102 u32 esdcfg1; 103/* Enhanced SDRAM Miscellanious Register */ 104 u32 esdmisc; 105}; 106 107/* Watchdog Registers*/ 108struct wdog_regs { 109 u16 wcr; 110 u16 wsr; 111 u16 wstr; 112}; 113 114/* PLL registers */ 115struct pll_regs { 116 u32 cscr; /* Clock Source Control Register */ 117 u32 mpctl0; /* MCU PLL Control Register 0 */ 118 u32 mpctl1; /* MCU PLL Control Register 1 */ 119 u32 spctl0; /* System PLL Control Register 0 */ 120 u32 spctl1; /* System PLL Control Register 1 */ 121 u32 osc26mctl; /* Oscillator 26M Register */ 122 u32 pcdr0; /* Peripheral Clock Divider Register 0 */ 123 u32 pcdr1; /* Peripheral Clock Divider Register 1 */ 124 u32 pccr0; /* Peripheral Clock Control Register 0 */ 125 u32 pccr1; /* Peripheral Clock Control Register 1 */ 126 u32 ccsr; /* Clock Control Status Register */ 127}; 128 129/* 130 * Definitions for the clocksource registers 131 */ 132struct gpt_regs { 133 u32 gpt_tctl; 134 u32 gpt_tprer; 135 u32 gpt_tcmp; 136 u32 gpt_tcr; 137 u32 gpt_tcn; 138 u32 gpt_tstat; 139}; 140 141/* IIM Control Registers */ 142struct iim_regs { 143 u32 iim_stat; 144 u32 iim_statm; 145 u32 iim_err; 146 u32 iim_emask; 147 u32 iim_fctl; 148 u32 iim_ua; 149 u32 iim_la; 150 u32 iim_sdat; 151 u32 iim_prev; 152 u32 iim_srev; 153 u32 iim_prg_p; 154 u32 iim_scs0; 155 u32 iim_scs1; 156 u32 iim_scs2; 157 u32 iim_scs3; 158 u32 res[0x1f1]; 159 struct fuse_bank { 160 u32 fuse_regs[0x20]; 161 u32 fuse_rsvd[0xe0]; 162 } bank[2]; 163}; 164 165struct fuse_bank0_regs { 166 u32 fuse0_3[5]; 167 u32 mac_addr[6]; 168 u32 fuse10_31[0x16]; 169}; 170 171#endif 172 173#define ARCH_MXC 174 175#define IMX_IO_BASE 0x10000000 176 177#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) 178#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) 179#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) 180#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) 181#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) 182#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) 183#define UART1_BASE (0x0a000 + IMX_IO_BASE) 184#define UART2_BASE (0x0b000 + IMX_IO_BASE) 185#define UART3_BASE (0x0c000 + IMX_IO_BASE) 186#define UART4_BASE (0x0d000 + IMX_IO_BASE) 187#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) 188#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) 189#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) 190#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) 191#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) 192#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) 193#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) 194#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) 195#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) 196#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) 197#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) 198#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) 199#define IIM_BASE_ADDR IMX_IIM_BASE 200#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) 201 202#define IMX_NFC_BASE (0xD8000000) 203#define IMX_ESD_BASE (0xD8001000) 204#define IMX_WEIM_BASE (0xD8002000) 205 206#define NFC_BASE_ADDR IMX_NFC_BASE 207 208 209/* FMCR System Control bit definition*/ 210#define UART4_RXD_CTL (1 << 25) 211#define UART4_RTS_CTL (1 << 24) 212#define KP_COL6_CTL (1 << 18) 213#define KP_ROW7_CTL (1 << 17) 214#define KP_ROW6_CTL (1 << 16) 215#define PC_WAIT_B_CTL (1 << 14) 216#define PC_READY_CTL (1 << 13) 217#define PC_VS1_CTL (1 << 12) 218#define PC_VS2_CTL (1 << 11) 219#define PC_BVD1_CTL (1 << 10) 220#define PC_BVD2_CTL (1 << 9) 221#define IOS16_CTL (1 << 8) 222#define NF_FMS (1 << 5) 223#define NF_16BIT_SEL (1 << 4) 224#define SLCDC_SEL (1 << 2) 225#define SDCS1_SEL (1 << 1) 226#define SDCS0_SEL (1 << 0) 227 228 229/* important definition of some bits of WCR */ 230#define WCR_WDE 0x04 231 232#define CSCR_MPEN (1 << 0) 233#define CSCR_SPEN (1 << 1) 234#define CSCR_FPM_EN (1 << 2) 235#define CSCR_OSC26M_DIS (1 << 3) 236#define CSCR_OSC26M_DIV1P5 (1 << 4) 237#define CSCR_AHB_DIV 238#define CSCR_ARM_DIV 239#define CSCR_ARM_SRC_MPLL (1 << 15) 240#define CSCR_MCU_SEL (1 << 16) 241#define CSCR_SP_SEL (1 << 17) 242#define CSCR_MPLL_RESTART (1 << 18) 243#define CSCR_SPLL_RESTART (1 << 19) 244#define CSCR_MSHC_SEL (1 << 20) 245#define CSCR_H264_SEL (1 << 21) 246#define CSCR_SSI1_SEL (1 << 22) 247#define CSCR_SSI2_SEL (1 << 23) 248#define CSCR_SD_CNT 249#define CSCR_USB_DIV 250#define CSCR_UPDATE_DIS (1 << 31) 251 252#define MPCTL1_BRMO (1 << 6) 253#define MPCTL1_LF (1 << 15) 254 255#define PCCR0_SSI2_EN (1 << 0) 256#define PCCR0_SSI1_EN (1 << 1) 257#define PCCR0_SLCDC_EN (1 << 2) 258#define PCCR0_SDHC3_EN (1 << 3) 259#define PCCR0_SDHC2_EN (1 << 4) 260#define PCCR0_SDHC1_EN (1 << 5) 261#define PCCR0_SDC_EN (1 << 6) 262#define PCCR0_SAHARA_EN (1 << 7) 263#define PCCR0_RTIC_EN (1 << 8) 264#define PCCR0_RTC_EN (1 << 9) 265#define PCCR0_PWM_EN (1 << 11) 266#define PCCR0_OWIRE_EN (1 << 12) 267#define PCCR0_MSHC_EN (1 << 13) 268#define PCCR0_LCDC_EN (1 << 14) 269#define PCCR0_KPP_EN (1 << 15) 270#define PCCR0_IIM_EN (1 << 16) 271#define PCCR0_I2C2_EN (1 << 17) 272#define PCCR0_I2C1_EN (1 << 18) 273#define PCCR0_GPT6_EN (1 << 19) 274#define PCCR0_GPT5_EN (1 << 20) 275#define PCCR0_GPT4_EN (1 << 21) 276#define PCCR0_GPT3_EN (1 << 22) 277#define PCCR0_GPT2_EN (1 << 23) 278#define PCCR0_GPT1_EN (1 << 24) 279#define PCCR0_GPIO_EN (1 << 25) 280#define PCCR0_FEC_EN (1 << 26) 281#define PCCR0_EMMA_EN (1 << 27) 282#define PCCR0_DMA_EN (1 << 28) 283#define PCCR0_CSPI3_EN (1 << 29) 284#define PCCR0_CSPI2_EN (1 << 30) 285#define PCCR0_CSPI1_EN (1 << 31) 286 287#define PCCR1_MSHC_BAUDEN (1 << 2) 288#define PCCR1_NFC_BAUDEN (1 << 3) 289#define PCCR1_SSI2_BAUDEN (1 << 4) 290#define PCCR1_SSI1_BAUDEN (1 << 5) 291#define PCCR1_H264_BAUDEN (1 << 6) 292#define PCCR1_PERCLK4_EN (1 << 7) 293#define PCCR1_PERCLK3_EN (1 << 8) 294#define PCCR1_PERCLK2_EN (1 << 9) 295#define PCCR1_PERCLK1_EN (1 << 10) 296#define PCCR1_HCLK_USB (1 << 11) 297#define PCCR1_HCLK_SLCDC (1 << 12) 298#define PCCR1_HCLK_SAHARA (1 << 13) 299#define PCCR1_HCLK_RTIC (1 << 14) 300#define PCCR1_HCLK_LCDC (1 << 15) 301#define PCCR1_HCLK_H264 (1 << 16) 302#define PCCR1_HCLK_FEC (1 << 17) 303#define PCCR1_HCLK_EMMA (1 << 18) 304#define PCCR1_HCLK_EMI (1 << 19) 305#define PCCR1_HCLK_DMA (1 << 20) 306#define PCCR1_HCLK_CSI (1 << 21) 307#define PCCR1_HCLK_BROM (1 << 22) 308#define PCCR1_HCLK_ATA (1 << 23) 309#define PCCR1_WDT_EN (1 << 24) 310#define PCCR1_USB_EN (1 << 25) 311#define PCCR1_UART6_EN (1 << 26) 312#define PCCR1_UART5_EN (1 << 27) 313#define PCCR1_UART4_EN (1 << 28) 314#define PCCR1_UART3_EN (1 << 29) 315#define PCCR1_UART2_EN (1 << 30) 316#define PCCR1_UART1_EN (1 << 31) 317 318/* SDRAM Controller registers bitfields */ 319#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) 320#define ESDCTL_BL (1 << 7) 321#define ESDCTL_FP (1 << 8) 322#define ESDCTL_PWDT(x) (((x) & 3) << 10) 323#define ESDCTL_SREFR(x) (((x) & 7) << 13) 324#define ESDCTL_DSIZ_16_UPPER (0 << 16) 325#define ESDCTL_DSIZ_16_LOWER (1 << 16) 326#define ESDCTL_DSIZ_32 (2 << 16) 327#define ESDCTL_COL8 (0 << 20) 328#define ESDCTL_COL9 (1 << 20) 329#define ESDCTL_COL10 (2 << 20) 330#define ESDCTL_ROW11 (0 << 24) 331#define ESDCTL_ROW12 (1 << 24) 332#define ESDCTL_ROW13 (2 << 24) 333#define ESDCTL_ROW14 (3 << 24) 334#define ESDCTL_ROW15 (4 << 24) 335#define ESDCTL_SP (1 << 27) 336#define ESDCTL_SMODE_NORMAL (0 << 28) 337#define ESDCTL_SMODE_PRECHARGE (1 << 28) 338#define ESDCTL_SMODE_AUTO_REF (2 << 28) 339#define ESDCTL_SMODE_LOAD_MODE (3 << 28) 340#define ESDCTL_SMODE_MAN_REF (4 << 28) 341#define ESDCTL_SDE (1 << 31) 342 343#define ESDCFG_TRC(x) (((x) & 0xf) << 0) 344#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) 345#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) 346#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) 347#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) 348#define ESDCFG_TWR (1 << 15) 349#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) 350#define ESDCFG_TRP(x) (((x) & 0x3) << 18) 351#define ESDCFG_TWTR (1 << 20) 352#define ESDCFG_TXP(x) (((x) & 0x3) << 21) 353 354#define ESDMISC_RST (1 << 1) 355#define ESDMISC_MDDREN (1 << 2) 356#define ESDMISC_MDDR_DL_RST (1 << 3) 357#define ESDMISC_MDDR_MDIS (1 << 4) 358#define ESDMISC_LHD (1 << 5) 359#define ESDMISC_MA10_SHARE (1 << 6) 360#define ESDMISC_SDRAM_RDY (1 << 31) 361 362#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) 363#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) 364#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) 365#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) 366#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) 367#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) 368#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) 369#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) 370#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) 371 372#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) 373#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) 374#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) 375#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) 376#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) 377#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) 378#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) 379#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) 380#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) 381#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) 382#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) 383#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) 384#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) 385#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) 386#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) 387#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) 388#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) 389#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) 390 391#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) 392#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) 393#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) 394#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) 395#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) 396#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) 397#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) 398#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) 399#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) 400#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) 401#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) 402#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) 403#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) 404#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) 405#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) 406#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 407#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 408#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 409#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 410#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 411#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 412#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 413#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 414#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 415#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 416#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 417#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 418#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) 419#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) 420#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) 421#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) 422 423/* Clocksource Bitfields */ 424#define TCTL_SWR (1 << 15) /* Software reset */ 425#define TCTL_FRR (1 << 8) /* Freerun / restart */ 426#define TCTL_CAP (3 << 6) /* Capture Edge */ 427#define TCTL_OM (1 << 5) /* output mode */ 428#define TCTL_IRQEN (1 << 4) /* interrupt enable */ 429#define TCTL_CLKSOURCE 1 /* Clock source bit position */ 430#define TCTL_TEN 1 /* Timer enable */ 431#define TPRER_PRES 0xff /* Prescale */ 432#define TSTAT_CAPT (1 << 1) /* Capture event */ 433#define TSTAT_COMP 1 /* Compare event */ 434 435#define GPIO1_BASE_ADDR 0x10015000 436#define GPIO2_BASE_ADDR 0x10015100 437#define GPIO3_BASE_ADDR 0x10015200 438#define GPIO4_BASE_ADDR 0x10015300 439#define GPIO5_BASE_ADDR 0x10015400 440#define GPIO6_BASE_ADDR 0x10015500 441 442#define GPIO_OUT (1 << 8) 443#define GPIO_IN (0 << 8) 444#define GPIO_PUEN (1 << 9) 445 446#define GPIO_PF (1 << 10) 447#define GPIO_AF (1 << 11) 448 449#define GPIO_OCR_SHIFT 12 450#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) 451#define GPIO_AIN (0 << GPIO_OCR_SHIFT) 452#define GPIO_BIN (1 << GPIO_OCR_SHIFT) 453#define GPIO_CIN (2 << GPIO_OCR_SHIFT) 454#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) 455 456#define GPIO_AOUT_SHIFT 14 457#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) 458#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) 459#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) 460#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) 461#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) 462 463#define GPIO_BOUT_SHIFT 16 464#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) 465#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) 466#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) 467#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) 468#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) 469 470#define IIM_STAT_BUSY (1 << 7) 471#define IIM_STAT_PRGD (1 << 1) 472#define IIM_STAT_SNSD (1 << 0) 473#define IIM_ERR_PRGE (1 << 7) 474#define IIM_ERR_WPE (1 << 6) 475#define IIM_ERR_OPE (1 << 5) 476#define IIM_ERR_RPE (1 << 4) 477#define IIM_ERR_WLRE (1 << 3) 478#define IIM_ERR_SNSE (1 << 2) 479#define IIM_ERR_PARITYE (1 << 1) 480 481#endif /* _IMX_REGS_H */ 482