1/* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _SYS_PROTO_H_ 9#define _SYS_PROTO_H_ 10 11#include <asm/arch/omap.h> 12#include <asm/arch/clock.h> 13#include <asm/io.h> 14#include <asm/omap_common.h> 15#include <linux/mtd/omap_gpmc.h> 16#include <asm/arch/mux_omap4.h> 17#include <asm/ti-common/sys_proto.h> 18 19DECLARE_GLOBAL_DATA_PTR; 20 21#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 22extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; 23extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; 24extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; 25extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; 26extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; 27extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; 28extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; 29#else 30extern const struct lpddr2_device_details elpida_2G_S4_details; 31extern const struct lpddr2_device_details elpida_4G_S4_details; 32#endif 33 34#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 35extern const struct lpddr2_device_timings jedec_default_timings; 36#else 37extern const struct lpddr2_device_timings elpida_2G_S4_timings; 38#endif 39 40struct omap_sysinfo { 41 char *board_string; 42}; 43extern const struct omap_sysinfo sysinfo; 44 45void gpmc_init(void); 46void watchdog_init(void); 47u32 get_device_type(void); 48void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); 49void set_muxconf_regs(void); 50u32 wait_on_value(u32, u32, void *, u32); 51void sdelay(unsigned long); 52void setup_early_clocks(void); 53void prcm_init(void); 54void do_board_detect(void); 55void bypass_dpll(u32 const base); 56void freq_update_core(void); 57u32 get_sys_clk_freq(void); 58u32 omap4_ddr_clk(void); 59void cancel_out(u32 *num, u32 *den, u32 den_limit); 60void sdram_init(void); 61u32 omap_sdram_size(void); 62u32 cortex_rev(void); 63void save_omap_boot_params(void); 64void init_omap_revision(void); 65void do_io_settings(void); 66void sri2c_init(void); 67int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); 68u32 warm_reset(void); 69void force_emif_self_refresh(void); 70void setup_warmreset_time(void); 71 72#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 73 74#endif 75