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7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6ul_pins.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/iomux-v3.h>
16#include <asm/imx-common/boot_mode.h>
17#include <asm/imx-common/mxc_i2c.h>
18#include <asm/io.h>
19#include <common.h>
20#include <fsl_esdhc.h>
21#include <i2c.h>
22#include <miiphy.h>
23#include <mmc.h>
24#include <netdev.h>
25#include <usb.h>
26#include <usb/ehci-ci.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33
34#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
36 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
41 PAD_CTL_ODE)
42
43#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
44 PAD_CTL_SPEED_HIGH | \
45 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
46
47#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
48 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
49
50#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
52#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
53 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
54
55#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
57 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
58 PAD_CTL_SRE_FAST)
59
60#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
61
62static struct i2c_pads_info i2c_pad_info1 = {
63 .scl = {
64 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
65 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
66 .gp = IMX_GPIO_NR(1, 2),
67 },
68 .sda = {
69 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
70 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
71 .gp = IMX_GPIO_NR(1, 3),
72 },
73};
74
75static struct i2c_pads_info i2c_pad_info2 = {
76 .scl = {
77 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
78 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
79 .gp = IMX_GPIO_NR(1, 0),
80 },
81 .sda = {
82 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
83 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
84 .gp = IMX_GPIO_NR(1, 1),
85 },
86};
87
88static struct i2c_pads_info i2c_pad_info4 = {
89 .scl = {
90 .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
91 .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
92 .gp = IMX_GPIO_NR(1, 20),
93 },
94 .sda = {
95 .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
96 .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
97 .gp = IMX_GPIO_NR(1, 21),
98 },
99};
100
101int dram_init(void)
102{
103 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
104
105 return 0;
106}
107
108static iomux_v3_cfg_t const uart1_pads[] = {
109 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
110 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
111};
112
113static iomux_v3_cfg_t const uart4_pads[] = {
114 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
115 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
116};
117
118static iomux_v3_cfg_t const uart5_pads[] = {
119 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
120 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
121 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
122 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
123};
124
125static iomux_v3_cfg_t const uart8_pads[] = {
126 MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
127 MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
128 MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
129 MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
130};
131
132static void setup_iomux_uart(void)
133{
134 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
135 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
136 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
137 imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
138}
139
140
141static iomux_v3_cfg_t const usdhc2_pads[] = {
142 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152
153
154
155
156 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
157};
158
159static struct fsl_esdhc_cfg usdhc_cfg = {
160 .esdhc_base = USDHC2_BASE_ADDR,
161 .max_bus_width = 8,
162};
163
164#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
165
166int board_mmc_getcd(struct mmc *mmc)
167{
168
169 return 1;
170}
171
172int board_mmc_init(bd_t *bis)
173{
174 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
175
176 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
177
178 return fsl_esdhc_initialize(bis, &usdhc_cfg);
179}
180
181#define USB_OTHERREGS_OFFSET 0x800
182#define UCTRL_PWR_POL (1 << 9)
183
184static iomux_v3_cfg_t const usb_otg_pads[] = {
185
186 MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
187 MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
188
189 MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
190 MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
191};
192
193static void setup_usb(void)
194{
195 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
196 ARRAY_SIZE(usb_otg_pads));
197}
198
199int board_usb_phy_mode(int port)
200{
201 if (port == 1)
202 return USB_INIT_HOST;
203 else
204 return usb_phy_mode(port);
205}
206
207int board_ehci_hcd_init(int port)
208{
209 u32 *usbnc_usb_ctrl;
210
211 if (port > 1)
212 return -EINVAL;
213
214 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
215 port * 4);
216
217
218 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
219
220 return 0;
221}
222
223static iomux_v3_cfg_t const fec1_pads[] = {
224 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
225 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
230 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
234
235
236 MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
237
238 MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
239};
240
241#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
242
243int board_eth_init(bd_t *bis)
244{
245 int ret;
246
247 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
248
249
250 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
251 if (!ret)
252 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
253 mdelay(10);
254 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
255 mdelay(10);
256
257 return cpu_eth_init(bis);
258}
259
260static int setup_fec(int fec_id)
261{
262 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
263 int ret;
264
265
266
267
268
269 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
270 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
271
272 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
273 if (ret)
274 return ret;
275
276 enable_enet_clk(1);
277
278 return 0;
279}
280
281int board_phy_config(struct phy_device *phydev)
282{
283 if (phydev->drv->config)
284 phydev->drv->config(phydev);
285
286 return 0;
287}
288
289int board_early_init_f(void)
290{
291 setup_iomux_uart();
292
293 return 0;
294}
295
296int board_init(void)
297{
298
299 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
300
301 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
302 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
303 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
304
305 setup_fec(CONFIG_FEC_ENET_DEV);
306
307 setup_usb();
308
309 return 0;
310}
311
312static const struct boot_mode board_boot_modes[] = {
313
314 {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
315 { NULL, 0 },
316};
317
318int board_late_init(void)
319{
320 add_board_boot_modes(board_boot_modes);
321 setenv("board_name", "xpress");
322
323 return 0;
324}
325
326int checkboard(void)
327{
328 puts("Board: CCV-EVA xPress\n");
329
330 return 0;
331}
332
