LXR uboot/drivers/block/ftide020.c

   1/*
   2 * Faraday FTIDE020 ATA Controller (AHB)
   3 *
   4 * (C) Copyright 2011 Andes Technology
   5 * Greentime Hu <greentime@andestech.com>
   6 * Macpaul Lin <macpaul@andestech.com>
   7 * Kuo-Wei Chou <kwchou@andestech.com>
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11/* ftide020.c - ide support functions for the FTIDE020_S controller */
  12
  13#include <config.h>
  14#include <common.h>
  15#include <ata.h>
  16#include <ide.h>
  17#include <asm/io.h>
  18#include <api_public.h>
  19
  20#include "ftide020.h"
  21
  22/* base address */
  23#define FTIDE_BASE      CONFIG_SYS_ATA_BASE_ADDR
  24
  25/*
  26 * data address - The CMD and DATA use the same FIFO in FTIDE020_S
  27 *   FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET
  28 *              = &ftide020->rw_fifo
  29 */
  30#define FTIDE_DATA      (&ftide020->rw_fifo)
  31
  32/* command and data I/O macros */
  33/* 0x0 - DATA FIFO */
  34#define WRITE_DATA(x)   outl((x), &ftide020->rw_fifo)   /* 0x00 */
  35#define READ_DATA()     inl(&ftide020->rw_fifo)         /* 0x00 */
  36/* 0x04 - R: Status Reg, W: CMD_FIFO */
  37#define WRITE_CMD(x)    outl((x), &ftide020->cmd_fifo)  /* 0x04 */
  38#define READ_STATUS()   inl(&ftide020->cmd_fifo)        /* 0x04 */
  39
  40void ftide_set_device(int cx8, int dev)
  41{
  42        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  43
  44        WRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev);
  45}
  46
  47unsigned char ide_read_register(int dev, unsigned int port)
  48{
  49        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  50
  51        ftide_set_device(0, dev);
  52        WRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) |
  53                IDE_REG_DA_WRITE(port));
  54
  55        return READ_DATA() & 0xff;
  56}
  57
  58void ide_write_register(int dev, unsigned int port, unsigned char val)
  59{
  60        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  61
  62        ftide_set_device(0, dev);
  63        WRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) |
  64                IDE_REG_DA_WRITE(port) | val);
  65}
  66
  67void ide_write_data(int dev, const ulong *sect_buf, int words)
  68{
  69        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  70
  71        ftide_set_device(0, dev);
  72        WRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1));
  73
  74        /* block write */
  75        outsl(FTIDE_DATA, sect_buf, words);
  76}
  77
  78void ide_read_data(int dev, ulong *sect_buf, int words)
  79{
  80        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  81
  82        ftide_set_device(0, dev);
  83        WRITE_CMD(READ_DATA_CMD | ((words << 2) - 1));
  84
  85        /* block read */
  86        insl(FTIDE_DATA, sect_buf, words);
  87}
  88
  89void ftide_dfifo_ready(ulong *time)
  90{
  91        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
  92
  93        while (!(READ_STATUS() & STATUS_RFE)) {
  94                if (*time-- == 0)
  95                        break;
  96
  97                udelay(100);
  98        }
  99}
 100
 101extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 102
 103/* Reset_IDE_controller */
 104static void reset_ide_controller(void)
 105{
 106        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
 107        unsigned int val;
 108
 109        val = inl(&ftide020->cr);
 110
 111        val |= CONTROL_RST;
 112        outl(val, &ftide020->cr);
 113
 114        /* wait until reset OK, this is poor HW design */
 115        mdelay(50);
 116        val &= ~(CONTROL_RST);
 117        outl(val, &ftide020->cr);
 118
 119        mdelay(50);
 120        val |= CONTROL_SRST;
 121        outl(val, &ftide020->cr);
 122
 123        /* wait until reset OK, this is poor HW design */
 124        mdelay(50);
 125        val &= ~(CONTROL_SRST);
 126        outl(val, &ftide020->cr);
 127
 128        /* IORDY enable for PIO, for 2 device */
 129        val |= (CONTROL_IRE0 | CONTROL_IRE1);
 130        outl(val, &ftide020->cr);
 131}
 132
 133/* IDE clock frequence */
 134uint ftide_clock_freq(void)
 135{
 136        /*
 137         * todo: To aquire dynamic system frequency is dependend on the power
 138         * management unit which the ftide020 is connected to. In current,
 139         * there are only few PMU supports in u-boot.
 140         * So this function is wait for future enhancement.
 141         */
 142        return 100;
 143}
 144
 145/* Calculate Timing Registers */
 146static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4)
 147{
 148        unsigned int val, ahb_ns = 8;
 149        u8 TEOC, T1, T2, T4;
 150
 151        T1 = (u8) (t1 / ahb_ns);
 152        if ((T1 * ahb_ns) == t1)
 153                T1--;
 154
 155        T2 = (u8) (t2 / ahb_ns);
 156        if ((T2 * ahb_ns) == t2)
 157                T2--;
 158
 159        T4 = (u8) (t4 / ahb_ns);
 160        if ((T4 * ahb_ns) == t4)
 161                T4--;
 162
 163        TEOC = (u8) (t0 / ahb_ns);
 164        if ((TEOC * ahb_ns) == t0)
 165                TEOC--;
 166
 167        TEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0);
 168
 169        /*
 170         * Here the fields in data timing registers in PIO mode
 171         * is accessed the same way as command timing registers.
 172         */
 173        val =   DT_REG_PIO_T1(T1)       |
 174                DT_REG_PIO_T2(T2)       |
 175                DT_REG_PIO_T4(T4)       |
 176                DT_REG_PIO_TEOC(TEOC);
 177
 178        return val;
 179}
 180
 181/* Set Timing Register */
 182static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode)
 183{
 184        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
 185        u16 t0, t1, t2, t4;
 186        u8 tcyc, tcvs, tmli, tenv, tack, trp;
 187        unsigned int val, sysclk = 8;
 188
 189        if (id >= TATOL_TIMING)
 190                return 0;
 191
 192        sysclk = ftide_clock_freq();
 193        switch (id) {
 194        case CMD_TIMING:
 195                if (mode < REG_MODE) {
 196                        t0 = REG_ACCESS_TIMING[REG_T0][mode];
 197                        t1 = REG_ACCESS_TIMING[REG_T1][mode];
 198                        t2 = REG_ACCESS_TIMING[REG_T2][mode];
 199                        t4 = REG_ACCESS_TIMING[REG_T4][mode];
 200
 201                        val = timing_cal(t0, t1, t2, t4);
 202                        outl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0));
 203                        return 1;
 204                } else
 205                        return 0;
 206        case PIO_TIMING:
 207                if (mode < PIO_MODE) {
 208                        t0 = PIO_ACCESS_TIMING[PIO_T0][mode];
 209                        t1 = PIO_ACCESS_TIMING[PIO_T1][mode];
 210                        t2 = PIO_ACCESS_TIMING[PIO_T2][mode];
 211                        t4 = PIO_ACCESS_TIMING[PIO_T4][mode];
 212
 213                        val = timing_cal(t0, t1, t2, t4);
 214
 215                        outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
 216                        return 1;
 217                } else
 218                        return 0;
 219        case DMA_TIMING:
 220                if (mode < UDMA_MODE) {
 221                        /*
 222                         * 0.999 is ceiling
 223                         * for tcyc, tcvs, tmli, tenv, trp, tack
 224                         */
 225                        tcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \
 226                                                * sysclk) + 9990) / 10000);
 227                        tcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \
 228                                                * sysclk) + 9990) / 10000);
 229                        tmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \
 230                                                * sysclk) + 9990) / 10000);
 231                        tenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \
 232                                                * sysclk) + 9990) / 10000);
 233                        trp  = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \
 234                                                * sysclk) + 9990) / 10000);
 235                        tack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \
 236                                                 * sysclk) + 9990) / 10000);
 237
 238                        val  =  DT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) |
 239                                DT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) |
 240                                DT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) |
 241                                DT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) |
 242                                DT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) |
 243                                DT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0);
 244
 245                        outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
 246                        return 1;
 247                } else
 248                        return 0;
 249        default:
 250                return 0;
 251        }
 252}
 253
 254static void ftide_read_hwrev(void)
 255{
 256        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
 257        unsigned int rev;
 258
 259        rev = inl(&ftide020->revision);
 260}
 261
 262static int ftide_controller_probe(void)
 263{
 264        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
 265        unsigned int bak;
 266
 267        bak = inl(&ftide020->ctrd1);
 268
 269        /* probing by using shorter setup time */
 270        outl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1);
 271        if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) {
 272                outl(bak, &ftide020->ctrd1);
 273                return 0;
 274        }
 275
 276        /* probing by using longer setup time */
 277        outl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1);
 278        if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) {
 279                outl(bak, &ftide020->ctrd1);
 280                return 0;
 281        }
 282
 283        outl(bak, &ftide020->ctrd1);
 284
 285        return 1;
 286}
 287
 288/* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */
 289int ide_preinit(void)
 290{
 291        static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
 292        int status;
 293        unsigned int val;
 294        int i;
 295
 296        status = 1;
 297        for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++)
 298                ide_bus_offset[i] = -ATA_STATUS;
 299
 300        /* auto-detect IDE controller */
 301        if (ftide_controller_probe()) {
 302                printf("FTIDE020_S\n");
 303        } else {
 304                printf("FTIDE020_S ATA controller not found.\n");
 305                return API_ENODEV;
 306        }
 307
 308        /* check HW IP revision */
 309        ftide_read_hwrev();
 310
 311        /* set FIFO threshold */
 312        outl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr);
 313
 314        /* set Device_0 PIO_4 timing */
 315        set_mode_timing(0, CMD_TIMING, REG_MODE4);
 316        set_mode_timing(0, PIO_TIMING, PIO_MODE4);
 317
 318        /* set Device_1 PIO_4 timing */
 319        set_mode_timing(1, CMD_TIMING, REG_MODE4);
 320        set_mode_timing(1, PIO_TIMING, PIO_MODE4);
 321
 322        /* from E-bios */
 323        /* little endian */
 324        outl(0x0, &ftide020->cr);
 325        mdelay(10);
 326
 327        outl(0x0fff0fff, &ftide020->ahbtr);
 328        mdelay(10);
 329
 330        /* Enable controller Interrupt */
 331        val = inl(&ftide020->cr);
 332
 333        /* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */
 334        val |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE);
 335        outl(val, &ftide020->cr);
 336
 337        status = 0;
 338
 339        return status;
 340}
 341
 342void ide_set_reset(int flag)
 343{
 344        debug("ide_set_reset()\n");
 345        reset_ide_controller();
 346        return;
 347}
 348