LXR uboot/drivers/net/bfin

   1/*
   2 * Driver for Blackfin On-Chip MAC device
   3 *
   4 * Copyright (c) 2005-2008 Analog Device, Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#include <common.h>
  10#include <config.h>
  11#include <net.h>
  12#include <netdev.h>
  13#include <command.h>
  14#include <malloc.h>
  15#include <miiphy.h>
  16#include <linux/mdio.h>
  17#include <linux/mii.h>
  18
  19#include <asm/blackfin.h>
  20#include <asm/clock.h>
  21#include <asm/portmux.h>
  22#include <asm/mach-common/bits/dma.h>
  23#include <asm/mach-common/bits/emac.h>
  24#include <asm/mach-common/bits/pll.h>
  25
  26#include "bfin_mac.h"
  27
  28#ifndef CONFIG_PHY_ADDR
  29# define CONFIG_PHY_ADDR 1
  30#endif
  31#ifndef CONFIG_PHY_CLOCK_FREQ
  32# define CONFIG_PHY_CLOCK_FREQ 2500000
  33#endif
  34
  35#ifdef CONFIG_POST
  36#include <post.h>
  37#endif
  38
  39#define RXBUF_BASE_ADDR         0xFF900000
  40#define TXBUF_BASE_ADDR         0xFF800000
  41#define TX_BUF_CNT              1
  42
  43#define TOUT_LOOP               1000000
  44
  45static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
  46static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
  47static u16 txIdx;               /* index of the current RX buffer */
  48static u16 rxIdx;               /* index of the current TX buffer */
  49
  50/* DMAx_CONFIG values at DMA Restart */
  51static const union {
  52        u16 data;
  53        ADI_DMA_CONFIG_REG reg;
  54} txdmacfg = {
  55        .reg = {
  56                .b_DMA_EN  = 1, /* enabled */
  57                .b_WNR     = 0, /* read from memory */
  58                .b_WDSIZE  = 2, /* wordsize is 32 bits */
  59                .b_DMA2D   = 0,
  60                .b_RESTART = 0,
  61                .b_DI_SEL  = 0,
  62                .b_DI_EN   = 0, /* no interrupt */
  63                .b_NDSIZE  = 5, /* 5 half words is desc size */
  64                .b_FLOW    = 7  /* large desc flow */
  65        },
  66};
  67
  68static int bfin_miiphy_wait(void)
  69{
  70        /* poll the STABUSY bit */
  71        while (bfin_read_EMAC_STAADD() & STABUSY)
  72                continue;
  73        return 0;
  74}
  75
  76static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  77{
  78        ushort val = 0;
  79        if (bfin_miiphy_wait())
  80                return 1;
  81        bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
  82        if (bfin_miiphy_wait())
  83                return 1;
  84        val = bfin_read_EMAC_STADAT();
  85        return val;
  86}
  87
  88static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
  89                             int reg, u16 val)
  90{
  91        if (bfin_miiphy_wait())
  92                return 1;
  93        bfin_write_EMAC_STADAT(val);
  94        bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
  95        return 0;
  96}
  97
  98int bfin_EMAC_initialize(bd_t *bis)
  99{
 100        struct eth_device *dev;
 101        dev = malloc(sizeof(*dev));
 102        if (dev == NULL)
 103                hang();
 104
 105        memset(dev, 0, sizeof(*dev));
 106        strcpy(dev->name, "bfin_mac");
 107
 108        dev->iobase = 0;
 109        dev->priv = 0;
 110        dev->init = bfin_EMAC_init;
 111        dev->halt = bfin_EMAC_halt;
 112        dev->send = bfin_EMAC_send;
 113        dev->recv = bfin_EMAC_recv;
 114        dev->write_hwaddr = bfin_EMAC_setup_addr;
 115
 116        eth_register(dev);
 117
 118#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 119        int retval;
 120        struct mii_dev *mdiodev = mdio_alloc();
 121        if (!mdiodev)
 122                return -ENOMEM;
 123        strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 124        mdiodev->read = bfin_miiphy_read;
 125        mdiodev->write = bfin_miiphy_write;
 126
 127        retval = mdio_register(mdiodev);
 128        if (retval < 0)
 129                return retval;
 130
 131        dev->priv = mdiodev;
 132#endif
 133
 134        return 0;
 135}
 136
 137static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
 138{
 139        int i;
 140        int result = 0;
 141
 142        if (length <= 0) {
 143                printf("Ethernet: bad packet size: %d\n", length);
 144                goto out;
 145        }
 146
 147        if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
 148                printf("Ethernet: tx DMA error\n");
 149                goto out;
 150        }
 151
 152        for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
 153                if (i > TOUT_LOOP) {
 154                        puts("Ethernet: tx time out\n");
 155                        goto out;
 156                }
 157        }
 158        txbuf[txIdx]->FrmData->NoBytes = length;
 159        memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
 160        txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
 161        bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
 162        bfin_write_DMA2_CONFIG(txdmacfg.data);
 163        bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
 164
 165        for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
 166                if (i > TOUT_LOOP) {
 167                        puts("Ethernet: tx error\n");
 168                        goto out;
 169                }
 170        }
 171        result = txbuf[txIdx]->StatusWord;
 172        txbuf[txIdx]->StatusWord = 0;
 173        if ((txIdx + 1) >= TX_BUF_CNT)
 174                txIdx = 0;
 175        else
 176                txIdx++;
 177 out:
 178        debug("BFIN EMAC send: length = %d\n", length);
 179        return result;
 180}
 181
 182static int bfin_EMAC_recv(struct eth_device *dev)
 183{
 184        int length = 0;
 185
 186        for (;;) {
 187                if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
 188                        length = -1;
 189                        break;
 190                }
 191                if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
 192                        printf("Ethernet: rx dma overrun\n");
 193                        break;
 194                }
 195                if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
 196                        printf("Ethernet: rx error\n");
 197                        break;
 198                }
 199                length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
 200                if (length <= 4) {
 201                        printf("Ethernet: bad frame\n");
 202                        break;
 203                }
 204
 205                debug("%s: len = %d\n", __func__, length - 4);
 206
 207                net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
 208                net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 209                bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
 210                rxbuf[rxIdx]->StatusWord = 0x00000000;
 211                if ((rxIdx + 1) >= PKTBUFSRX)
 212                        rxIdx = 0;
 213                else
 214                        rxIdx++;
 215        }
 216
 217        return length;
 218}
 219
 220/**************************************************************
 221 *
 222 * Ethernet Initialization Routine
 223 *
 224 *************************************************************/
 225
 226/* MDC = SCLK / MDC_freq / 2 - 1 */
 227#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
 228
 229#ifndef CONFIG_BFIN_MAC_PINS
 230# ifdef CONFIG_RMII
 231#  define CONFIG_BFIN_MAC_PINS P_RMII0
 232# else
 233#  define CONFIG_BFIN_MAC_PINS P_MII0
 234# endif
 235#endif
 236
 237static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
 238{
 239        const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
 240        int phydat;
 241        size_t count;
 242        struct mii_dev *mdiodev = dev->priv;
 243
 244        /* Enable PHY output */
 245        bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
 246
 247        /* Set all the pins to peripheral mode */
 248        peripheral_request_list(pins, "bfin_mac");
 249
 250        /* Odd word alignment for Receive Frame DMA word */
 251        /* Configure checksum support and rcve frame word alignment */
 252        bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
 253
 254        /* turn on auto-negotiation and wait for link to come up */
 255        bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
 256                          BMCR_ANENABLE);
 257        count = 0;
 258        while (1) {
 259                ++count;
 260                phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
 261                                          MDIO_DEVAD_NONE, MII_BMSR);
 262                if (phydat < 0)
 263                        return phydat;
 264                if (phydat & BMSR_LSTATUS)
 265                        break;
 266                if (count > 30000) {
 267                        printf("%s: link down, check cable\n", dev->name);
 268                        return -1;
 269                }
 270                udelay(100);
 271        }
 272
 273        /* see what kind of link we have */
 274        phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
 275                                  MII_LPA);
 276        if (phydat < 0)
 277                return phydat;
 278        if (phydat & LPA_DUPLEX)
 279                *opmode = FDMODE;
 280        else
 281                *opmode = 0;
 282
 283        bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
 284        bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
 285        bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
 286
 287        /* Initialize the TX DMA channel registers */
 288        bfin_write_DMA2_X_COUNT(0);
 289        bfin_write_DMA2_X_MODIFY(4);
 290        bfin_write_DMA2_Y_COUNT(0);
 291        bfin_write_DMA2_Y_MODIFY(0);
 292
 293        /* Initialize the RX DMA channel registers */
 294        bfin_write_DMA1_X_COUNT(0);
 295        bfin_write_DMA1_X_MODIFY(4);
 296        bfin_write_DMA1_Y_COUNT(0);
 297        bfin_write_DMA1_Y_MODIFY(0);
 298
 299        return 0;
 300}
 301
 302static int bfin_EMAC_setup_addr(struct eth_device *dev)
 303{
 304        bfin_write_EMAC_ADDRLO(
 305                dev->enetaddr[0] |
 306                dev->enetaddr[1] << 8 |
 307                dev->enetaddr[2] << 16 |
 308                dev->enetaddr[3] << 24
 309        );
 310        bfin_write_EMAC_ADDRHI(
 311                dev->enetaddr[4] |
 312                dev->enetaddr[5] << 8
 313        );
 314        return 0;
 315}
 316
 317static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
 318{
 319        u32 opmode;
 320        int dat;
 321        int i;
 322        debug("Eth_init: ......\n");
 323
 324        txIdx = 0;
 325        rxIdx = 0;
 326
 327        /* Initialize System Register */
 328        if (bfin_miiphy_init(dev, &dat) < 0)
 329                return -1;
 330
 331        /* Initialize EMAC address */
 332        bfin_EMAC_setup_addr(dev);
 333
 334        /* Initialize TX and RX buffer */
 335        for (i = 0; i < PKTBUFSRX; i++) {
 336                rxbuf[i] = SetupRxBuffer(i);
 337                if (i > 0) {
 338                        rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
 339                        if (i == (PKTBUFSRX - 1))
 340                                rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
 341                }
 342        }
 343        for (i = 0; i < TX_BUF_CNT; i++) {
 344                txbuf[i] = SetupTxBuffer(i);
 345                if (i > 0) {
 346                        txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
 347                        if (i == (TX_BUF_CNT - 1))
 348                                txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
 349                }
 350        }
 351
 352        /* Set RX DMA */
 353        bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
 354        bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
 355
 356        /* Wait MII done */
 357        bfin_miiphy_wait();
 358
 359        /* We enable only RX here */
 360        /* ASTP   : Enable Automatic Pad Stripping
 361           PR     : Promiscuous Mode for test
 362           PSF    : Receive frames with total length less than 64 bytes.
 363           FDMODE : Full Duplex Mode
 364           LB     : Internal Loopback for test
 365           RE     : Receiver Enable */
 366        if (dat == FDMODE)
 367                opmode = ASTP | FDMODE | PSF;
 368        else
 369                opmode = ASTP | PSF;
 370        opmode |= RE;
 371#ifdef CONFIG_RMII
 372        opmode |= TE | RMII;
 373#endif
 374        /* Turn on the EMAC */
 375        bfin_write_EMAC_OPMODE(opmode);
 376        return 0;
 377}
 378
 379static void bfin_EMAC_halt(struct eth_device *dev)
 380{
 381        debug("Eth_halt: ......\n");
 382        /* Turn off the EMAC */
 383        bfin_write_EMAC_OPMODE(0);
 384        /* Turn off the EMAC RX DMA */
 385        bfin_write_DMA1_CONFIG(0);
 386        bfin_write_DMA2_CONFIG(0);
 387}
 388
 389ADI_ETHER_BUFFER *SetupRxBuffer(int no)
 390{
 391        ADI_ETHER_FRAME_BUFFER *frmbuf;
 392        ADI_ETHER_BUFFER *buf;
 393        int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;   /* ensure a multi. of 4 */
 394        int total_size = nobytes_buffer + RECV_BUFSIZE;
 395
 396        buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
 397        frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
 398
 399        memset(buf, 0x00, nobytes_buffer);
 400        buf->FrmData = frmbuf;
 401        memset(frmbuf, 0xfe, RECV_BUFSIZE);
 402
 403        /* set up first desc to point to receive frame buffer */
 404        buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
 405        buf->Dma[0].START_ADDR = (u32) buf->FrmData;
 406        buf->Dma[0].CONFIG.b_DMA_EN = 1;        /* enabled */
 407        buf->Dma[0].CONFIG.b_WNR = 1;   /* Write to memory */
 408        buf->Dma[0].CONFIG.b_WDSIZE = 2;        /* wordsize is 32 bits */
 409        buf->Dma[0].CONFIG.b_NDSIZE = 5;        /* 5 half words is desc size. */
 410        buf->Dma[0].CONFIG.b_FLOW = 7;  /* large desc flow */
 411
 412        /* set up second desc to point to status word */
 413        buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
 414        buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
 415        buf->Dma[1].CONFIG.b_DMA_EN = 1;        /* enabled */
 416        buf->Dma[1].CONFIG.b_WNR = 1;   /* Write to memory */
 417        buf->Dma[1].CONFIG.b_WDSIZE = 2;        /* wordsize is 32 bits */
 418        buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
 419        buf->Dma[1].CONFIG.b_NDSIZE = 5;        /* must be 0 when FLOW is 0 */
 420        buf->Dma[1].CONFIG.b_FLOW = 7;  /* stop */
 421
 422        return buf;
 423}
 424
 425ADI_ETHER_BUFFER *SetupTxBuffer(int no)
 426{
 427        ADI_ETHER_FRAME_BUFFER *frmbuf;
 428        ADI_ETHER_BUFFER *buf;
 429        int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;   /* ensure a multi. of 4 */
 430        int total_size = nobytes_buffer + RECV_BUFSIZE;
 431
 432        buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
 433        frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
 434
 435        memset(buf, 0x00, nobytes_buffer);
 436        buf->FrmData = frmbuf;
 437        memset(frmbuf, 0x00, RECV_BUFSIZE);
 438
 439        /* set up first desc to point to receive frame buffer */
 440        buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
 441        buf->Dma[0].START_ADDR = (u32) buf->FrmData;
 442        buf->Dma[0].CONFIG.b_DMA_EN = 1;        /* enabled */
 443        buf->Dma[0].CONFIG.b_WNR = 0;   /* Read to memory */
 444        buf->Dma[0].CONFIG.b_WDSIZE = 2;        /* wordsize is 32 bits */
 445        buf->Dma[0].CONFIG.b_NDSIZE = 5;        /* 5 half words is desc size. */
 446        buf->Dma[0].CONFIG.b_FLOW = 7;  /* large desc flow */
 447
 448        /* set up second desc to point to status word */
 449        buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
 450        buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
 451        buf->Dma[1].CONFIG.b_DMA_EN = 1;        /* enabled */
 452        buf->Dma[1].CONFIG.b_WNR = 1;   /* Write to memory */
 453        buf->Dma[1].CONFIG.b_WDSIZE = 2;        /* wordsize is 32 bits */
 454        buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
 455        buf->Dma[1].CONFIG.b_NDSIZE = 0;        /* must be 0 when FLOW is 0 */
 456        buf->Dma[1].CONFIG.b_FLOW = 0;  /* stop */
 457
 458        return buf;
 459}
 460
 461#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
 462int ether_post_test(int flags)
 463{
 464        uchar buf[64];
 465        int i, value = 0;
 466        int length;
 467        uint addr;
 468
 469        printf("\n--------");
 470        bfin_EMAC_init(NULL, NULL);
 471        /* construct the package */
 472        addr = bfin_read_EMAC_ADDRLO();
 473        buf[0] = buf[6] = addr;
 474        buf[1] = buf[7] = addr >> 8;
 475        buf[2] = buf[8] = addr >> 16;
 476        buf[3] = buf[9] = addr >> 24;
 477        addr = bfin_read_EMAC_ADDRHI();
 478        buf[4] = buf[10] = addr;
 479        buf[5] = buf[11] = addr >> 8;
 480        buf[12] = 0x08;         /* Type: ARP */
 481        buf[13] = 0x06;
 482        buf[14] = 0x00;         /* Hardware type: Ethernet */
 483        buf[15] = 0x01;
 484        buf[16] = 0x08;         /* Protocal type: IP */
 485        buf[17] = 0x00;
 486        buf[18] = 0x06;         /* Hardware size    */
 487        buf[19] = 0x04;         /* Protocol size    */
 488        buf[20] = 0x00;         /* Opcode: request  */
 489        buf[21] = 0x01;
 490
 491        for (i = 0; i < 42; i++)
 492                buf[i + 22] = i;
 493        printf("--------Send 64 bytes......\n");
 494        bfin_EMAC_send(NULL, buf, 64);
 495        for (i = 0; i < 100; i++) {
 496                udelay(10000);
 497                if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
 498                        value = 1;
 499                        break;
 500                }
 501        }
 502        if (value == 0) {
 503                printf("--------EMAC can't receive any data\n");
 504                eth_halt();
 505                return -1;
 506        }
 507        length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
 508        for (i = 0; i < length; i++) {
 509                if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
 510                        printf("--------EMAC receive error data!\n");
 511                        eth_halt();
 512                        return -1;
 513                }
 514        }
 515        printf("--------receive %d bytes, matched\n", length);
 516        bfin_EMAC_halt(NULL);
 517        return 0;
 518}
 519#endif
 520