LXR uboot/drivers/spi/zynq

   1/*
   2 * (C) Copyright 2013 Xilinx, Inc.
   3 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
   4 *
   5 * Xilinx Zynq PS SPI controller driver (master mode only)
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <dm.h>
  12#include <malloc.h>
  13#include <spi.h>
  14#include <asm/io.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  19#define ZYNQ_SPI_CR_MSA_MASK            BIT(15) /* Manual start enb */
  20#define ZYNQ_SPI_CR_MCS_MASK            BIT(14) /* Manual chip select */
  21#define ZYNQ_SPI_CR_CS_MASK             GENMASK(13, 10) /* Chip select */
  22#define ZYNQ_SPI_CR_BAUD_MASK           GENMASK(5, 3)   /* Baud rate div */
  23#define ZYNQ_SPI_CR_CPHA_MASK           BIT(2)  /* Clock phase */
  24#define ZYNQ_SPI_CR_CPOL_MASK           BIT(1)  /* Clock polarity */
  25#define ZYNQ_SPI_CR_MSTREN_MASK         BIT(0)  /* Mode select */
  26#define ZYNQ_SPI_IXR_RXNEMPTY_MASK      BIT(4)  /* RX_FIFO_not_empty */
  27#define ZYNQ_SPI_IXR_TXOW_MASK          BIT(2)  /* TX_FIFO_not_full */
  28#define ZYNQ_SPI_IXR_ALL_MASK           GENMASK(6, 0)   /* All IXR bits */
  29#define ZYNQ_SPI_ENR_SPI_EN_MASK        BIT(0)  /* SPI Enable */
  30
  31#define ZYNQ_SPI_CR_BAUD_MAX            8       /* Baud rate divisor max val */
  32#define ZYNQ_SPI_CR_BAUD_SHIFT          3       /* Baud rate divisor shift */
  33#define ZYNQ_SPI_CR_SS_SHIFT            10      /* Slave select shift */
  34
  35#define ZYNQ_SPI_FIFO_DEPTH             128
  36#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
  37#define CONFIG_SYS_ZYNQ_SPI_WAIT        (CONFIG_SYS_HZ/100)     /* 10 ms */
  38#endif
  39
  40/* zynq spi register set */
  41struct zynq_spi_regs {
  42        u32 cr;         /* 0x00 */
  43        u32 isr;        /* 0x04 */
  44        u32 ier;        /* 0x08 */
  45        u32 idr;        /* 0x0C */
  46        u32 imr;        /* 0x10 */
  47        u32 enr;        /* 0x14 */
  48        u32 dr;         /* 0x18 */
  49        u32 txdr;       /* 0x1C */
  50        u32 rxdr;       /* 0x20 */
  51};
  52
  53
  54/* zynq spi platform data */
  55struct zynq_spi_platdata {
  56        struct zynq_spi_regs *regs;
  57        u32 frequency;          /* input frequency */
  58        u32 speed_hz;
  59};
  60
  61/* zynq spi priv */
  62struct zynq_spi_priv {
  63        struct zynq_spi_regs *regs;
  64        u8 cs;
  65        u8 mode;
  66        u8 fifo_depth;
  67        u32 freq;               /* required frequency */
  68};
  69
  70static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
  71{
  72        struct zynq_spi_platdata *plat = bus->platdata;
  73        const void *blob = gd->fdt_blob;
  74        int node = bus->of_offset;
  75
  76        plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
  77
  78        /* FIXME: Use 250MHz as a suitable default */
  79        plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  80                                        250000000);
  81        plat->speed_hz = plat->frequency / 2;
  82
  83        debug("%s: regs=%p max-frequency=%d\n", __func__,
  84              plat->regs, plat->frequency);
  85
  86        return 0;
  87}
  88
  89static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  90{
  91        struct zynq_spi_regs *regs = priv->regs;
  92        u32 confr;
  93
  94        /* Disable SPI */
  95        confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  96        writel(~confr, &regs->enr);
  97
  98        /* Disable Interrupts */
  99        writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
 100
 101        /* Clear RX FIFO */
 102        while (readl(&regs->isr) &
 103                        ZYNQ_SPI_IXR_RXNEMPTY_MASK)
 104                readl(&regs->rxdr);
 105
 106        /* Clear Interrupts */
 107        writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
 108
 109        /* Manual slave select and Auto start */
 110        confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
 111                ZYNQ_SPI_CR_MSTREN_MASK;
 112        confr &= ~ZYNQ_SPI_CR_MSA_MASK;
 113        writel(confr, &regs->cr);
 114
 115        /* Enable SPI */
 116        writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
 117}
 118
 119static int zynq_spi_probe(struct udevice *bus)
 120{
 121        struct zynq_spi_platdata *plat = dev_get_platdata(bus);
 122        struct zynq_spi_priv *priv = dev_get_priv(bus);
 123
 124        priv->regs = plat->regs;
 125        priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
 126
 127        /* init the zynq spi hw */
 128        zynq_spi_init_hw(priv);
 129
 130        return 0;
 131}
 132
 133static void spi_cs_activate(struct udevice *dev)
 134{
 135        struct udevice *bus = dev->parent;
 136        struct zynq_spi_priv *priv = dev_get_priv(bus);
 137        struct zynq_spi_regs *regs = priv->regs;
 138        u32 cr;
 139
 140        clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
 141        cr = readl(&regs->cr);
 142        /*
 143         * CS cal logic: CS[13:10]
 144         * xxx0 - cs0
 145         * xx01 - cs1
 146         * x011 - cs2
 147         */
 148        cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
 149        writel(cr, &regs->cr);
 150}
 151
 152static void spi_cs_deactivate(struct udevice *dev)
 153{
 154        struct udevice *bus = dev->parent;
 155        struct zynq_spi_priv *priv = dev_get_priv(bus);
 156        struct zynq_spi_regs *regs = priv->regs;
 157
 158        setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
 159}
 160
 161static int zynq_spi_claim_bus(struct udevice *dev)
 162{
 163        struct udevice *bus = dev->parent;
 164        struct zynq_spi_priv *priv = dev_get_priv(bus);
 165        struct zynq_spi_regs *regs = priv->regs;
 166
 167        writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
 168
 169        return 0;
 170}
 171
 172static int zynq_spi_release_bus(struct udevice *dev)
 173{
 174        struct udevice *bus = dev->parent;
 175        struct zynq_spi_priv *priv = dev_get_priv(bus);
 176        struct zynq_spi_regs *regs = priv->regs;
 177        u32 confr;
 178
 179        confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
 180        writel(~confr, &regs->enr);
 181
 182        return 0;
 183}
 184
 185static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
 186                            const void *dout, void *din, unsigned long flags)
 187{
 188        struct udevice *bus = dev->parent;
 189        struct zynq_spi_priv *priv = dev_get_priv(bus);
 190        struct zynq_spi_regs *regs = priv->regs;
 191        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 192        u32 len = bitlen / 8;
 193        u32 tx_len = len, rx_len = len, tx_tvl;
 194        const u8 *tx_buf = dout;
 195        u8 *rx_buf = din, buf;
 196        u32 ts, status;
 197
 198        debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
 199              bus->seq, slave_plat->cs, bitlen, len, flags);
 200
 201        if (bitlen % 8) {
 202                debug("spi_xfer: Non byte aligned SPI transfer\n");
 203                return -1;
 204        }
 205
 206        priv->cs = slave_plat->cs;
 207        if (flags & SPI_XFER_BEGIN)
 208                spi_cs_activate(dev);
 209
 210        while (rx_len > 0) {
 211                /* Write the data into TX FIFO - tx threshold is fifo_depth */
 212                tx_tvl = 0;
 213                while ((tx_tvl < priv->fifo_depth) && tx_len) {
 214                        if (tx_buf)
 215                                buf = *tx_buf++;
 216                        else
 217                                buf = 0;
 218                        writel(buf, &regs->txdr);
 219                        tx_len--;
 220                        tx_tvl++;
 221                }
 222
 223                /* Check TX FIFO completion */
 224                ts = get_timer(0);
 225                status = readl(&regs->isr);
 226                while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
 227                        if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
 228                                printf("spi_xfer: Timeout! TX FIFO not full\n");
 229                                return -1;
 230                        }
 231                        status = readl(&regs->isr);
 232                }
 233
 234                /* Read the data from RX FIFO */
 235                status = readl(&regs->isr);
 236                while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
 237                        buf = readl(&regs->rxdr);
 238                        if (rx_buf)
 239                                *rx_buf++ = buf;
 240                        status = readl(&regs->isr);
 241                        rx_len--;
 242                }
 243        }
 244
 245        if (flags & SPI_XFER_END)
 246                spi_cs_deactivate(dev);
 247
 248        return 0;
 249}
 250
 251static int zynq_spi_set_speed(struct udevice *bus, uint speed)
 252{
 253        struct zynq_spi_platdata *plat = bus->platdata;
 254        struct zynq_spi_priv *priv = dev_get_priv(bus);
 255        struct zynq_spi_regs *regs = priv->regs;
 256        uint32_t confr;
 257        u8 baud_rate_val = 0;
 258
 259        if (speed > plat->frequency)
 260                speed = plat->frequency;
 261
 262        /* Set the clock frequency */
 263        confr = readl(&regs->cr);
 264        if (speed == 0) {
 265                /* Set baudrate x8, if the freq is 0 */
 266                baud_rate_val = 0x2;
 267        } else if (plat->speed_hz != speed) {
 268                while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
 269                                ((plat->frequency /
 270                                (2 << baud_rate_val)) > speed))
 271                        baud_rate_val++;
 272                plat->speed_hz = speed / (2 << baud_rate_val);
 273        }
 274        confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
 275        confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
 276
 277        writel(confr, &regs->cr);
 278        priv->freq = speed;
 279
 280        debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
 281              priv->regs, priv->freq);
 282
 283        return 0;
 284}
 285
 286static int zynq_spi_set_mode(struct udevice *bus, uint mode)
 287{
 288        struct zynq_spi_priv *priv = dev_get_priv(bus);
 289        struct zynq_spi_regs *regs = priv->regs;
 290        uint32_t confr;
 291
 292        /* Set the SPI Clock phase and polarities */
 293        confr = readl(&regs->cr);
 294        confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
 295
 296        if (mode & SPI_CPHA)
 297                confr |= ZYNQ_SPI_CR_CPHA_MASK;
 298        if (mode & SPI_CPOL)
 299                confr |= ZYNQ_SPI_CR_CPOL_MASK;
 300
 301        writel(confr, &regs->cr);
 302        priv->mode = mode;
 303
 304        debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
 305
 306        return 0;
 307}
 308
 309static const struct dm_spi_ops zynq_spi_ops = {
 310        .claim_bus      = zynq_spi_claim_bus,
 311        .release_bus    = zynq_spi_release_bus,
 312        .xfer           = zynq_spi_xfer,
 313        .set_speed      = zynq_spi_set_speed,
 314        .set_mode       = zynq_spi_set_mode,
 315};
 316
 317static const struct udevice_id zynq_spi_ids[] = {
 318        { .compatible = "xlnx,zynq-spi-r1p6" },
 319        { .compatible = "cdns,spi-r1p6" },
 320        { }
 321};
 322
 323U_BOOT_DRIVER(zynq_spi) = {
 324        .name   = "zynq_spi",
 325        .id     = UCLASS_SPI,
 326        .of_match = zynq_spi_ids,
 327        .ops    = &zynq_spi_ops,
 328        .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
 329        .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
 330        .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
 331        .probe  = zynq_spi_probe,
 332};
 333