1/* 2 * Copyright (C) 2004 by Thomas Rathbone, HP Labs 3 * Copyright (C) 2005 by Ivan Kokshaysky 4 * Copyright (C) 2006 by SAN People 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef AT91_UDC_H 10#define AT91_UDC_H 11 12/* 13 * USB Device Port (UDP) registers. 14 * Based on AT91RM9200 datasheet revision E. 15 */ 16 17#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */ 18#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */ 19#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */ 20#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */ 21 22#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */ 23#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */ 24#define AT91_UDP_CONFG (1 << 1) /* Configured */ 25#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */ 26#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */ 27#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */ 28 29#define AT91_UDP_FADDR 0x08 /* Function Address Register */ 30#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */ 31#define AT91_UDP_FEN (1 << 8) /* Function Enable */ 32 33#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ 34#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ 35#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ 36 37#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ 38#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ 39#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ 40#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ 41#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */ 42#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ 43#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrupt Status */ 44#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status [AT91RM9200 only] */ 45 46#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ 47#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */ 48 49#define AT91_UDP_CSR(n) (0x30+((n)*4)) /* Endpoint Control/Status Registers 0-7 */ 50#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */ 51#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */ 52#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */ 53#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */ 54#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */ 55#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */ 56#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */ 57#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */ 58#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */ 59#define AT91_UDP_EPTYPE_CTRL (0 << 8) 60#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8) 61#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8) 62#define AT91_UDP_EPTYPE_INT_OUT (3 << 8) 63#define AT91_UDP_EPTYPE_ISO_IN (5 << 8) 64#define AT91_UDP_EPTYPE_BULK_IN (6 << 8) 65#define AT91_UDP_EPTYPE_INT_IN (7 << 8) 66#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */ 67#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */ 68#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */ 69 70#define AT91_UDP_FDR(n) (0x50+((n)*4)) /* Endpoint FIFO Data Registers 0-7 */ 71 72#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ 73#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */ 74#define AT91_UDP_TXVC_PUON (1 << 9) /* PullUp On [AT91SAM9260 only] */ 75 76/*-------------------------------------------------------------------------*/ 77 78/* 79 * controller driver data structures 80 */ 81 82#define NUM_ENDPOINTS 6 83 84/* 85 * hardware won't disable bus reset, or resume while the controller 86 * is suspended ... watching suspend helps keep the logic symmetric. 87 */ 88#define MINIMUS_INTERRUPTUS \ 89 (AT91_UDP_ENDBUSRES | AT91_UDP_RXRSM | AT91_UDP_RXSUSP) 90 91struct at91_ep { 92 struct usb_ep ep; 93 struct list_head queue; 94 struct at91_udc *udc; 95 void __iomem *creg; 96 97 unsigned maxpacket:16; 98 u8 int_mask; 99 unsigned is_pingpong:1; 100 101 unsigned stopped:1; 102 unsigned is_in:1; 103 unsigned is_iso:1; 104 unsigned fifo_bank:1; 105}; 106 107struct at91_udc_caps { 108 int (*init)(struct at91_udc *udc); 109 void (*pullup)(struct at91_udc *udc, int is_on); 110}; 111 112/* 113 * driver is non-SMP, and just blocks IRQs whenever it needs 114 * access protection for chip registers or driver state 115 */ 116struct at91_udc { 117 struct usb_gadget gadget; 118 struct at91_ep ep[NUM_ENDPOINTS]; 119 struct usb_gadget_driver *driver; 120 const struct at91_udc_caps *caps; 121 unsigned vbus:1; 122 unsigned enabled:1; 123 unsigned clocked:1; 124 unsigned suspended:1; 125 unsigned req_pending:1; 126 unsigned wait_for_addr_ack:1; 127 unsigned wait_for_config_ack:1; 128 unsigned selfpowered:1; 129 unsigned active_suspend:1; 130 u8 addr; 131 struct at91_udc_data board; 132 void __iomem *udp_baseaddr; 133 int udp_irq; 134 spinlock_t lock; 135 struct at91_matrix *matrix; 136}; 137 138static inline struct at91_udc *to_udc(struct usb_gadget *g) 139{ 140 return container_of(g, struct at91_udc, gadget); 141} 142 143struct at91_request { 144 struct usb_request req; 145 struct list_head queue; 146}; 147 148/*-------------------------------------------------------------------------*/ 149 150#ifdef VERBOSE_DEBUG 151# define VDBG DBG 152#else 153# define VDBG(stuff...) do{}while(0) 154#endif 155 156#ifdef PACKET_TRACE 157# define PACKET VDBG 158#else 159# define PACKET(stuff...) do{}while(0) 160#endif 161 162#define ERR(stuff...) debug("udc: " stuff) 163#define WARNING(stuff...) debug("udc: " stuff) 164#define INFO(stuff...) debug("udc: " stuff) 165#define DBG(stuff...) debug("udc: " stuff) 166 167#endif 168 169