LXR uboot/drivers/video/rockchip/rk

   1/*
   2 * Copyright (c) 2015 Google, Inc
   3 * Copyright 2014 Rockchip Inc.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <clk.h>
  10#include <display.h>
  11#include <dm.h>
  12#include <edid.h>
  13#include <regmap.h>
  14#include <syscon.h>
  15#include <video.h>
  16#include <asm/gpio.h>
  17#include <asm/hardware.h>
  18#include <asm/io.h>
  19#include <asm/arch/clock.h>
  20#include <asm/arch/cru_rk3288.h>
  21#include <asm/arch/grf_rk3288.h>
  22#include <asm/arch/edp_rk3288.h>
  23#include <asm/arch/hdmi_rk3288.h>
  24#include <asm/arch/vop_rk3288.h>
  25#include <dm/device-internal.h>
  26#include <dm/uclass-internal.h>
  27#include <dt-bindings/clock/rk3288-cru.h>
  28#include <power/regulator.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32struct rk_vop_priv {
  33        struct rk3288_vop *regs;
  34        struct rk3288_grf *grf;
  35};
  36
  37void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
  38                  int fb_bits_per_pixel, const struct display_timing *edid)
  39{
  40        u32 lb_mode;
  41        u32 rgb_mode;
  42        u32 hactive = edid->hactive.typ;
  43        u32 vactive = edid->vactive.typ;
  44
  45        writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
  46               &regs->win0_act_info);
  47
  48        writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
  49               V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
  50               &regs->win0_dsp_st);
  51
  52        writel(V_DSP_WIDTH(hactive - 1) |
  53                V_DSP_HEIGHT(vactive - 1),
  54                &regs->win0_dsp_info);
  55
  56        clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  57                        V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
  58
  59        switch (fb_bits_per_pixel) {
  60        case 16:
  61                rgb_mode = RGB565;
  62                writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
  63                break;
  64        case 24:
  65                rgb_mode = RGB888;
  66                writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
  67                break;
  68        case 32:
  69        default:
  70                rgb_mode = ARGB8888;
  71                writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
  72                break;
  73        }
  74
  75        if (hactive > 2560)
  76                lb_mode = LB_RGB_3840X2;
  77        else if (hactive > 1920)
  78                lb_mode = LB_RGB_2560X4;
  79        else if (hactive > 1280)
  80                lb_mode = LB_RGB_1920X5;
  81        else
  82                lb_mode = LB_RGB_1280X8;
  83
  84        clrsetbits_le32(&regs->win0_ctrl0,
  85                        M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  86                        V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
  87                        V_WIN0_EN(1));
  88
  89        writel(fbbase, &regs->win0_yrgb_mst);
  90        writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  91}
  92
  93void rkvop_mode_set(struct rk3288_vop *regs,
  94                    const struct display_timing *edid, enum vop_modes mode)
  95{
  96        u32 hactive = edid->hactive.typ;
  97        u32 vactive = edid->vactive.typ;
  98        u32 hsync_len = edid->hsync_len.typ;
  99        u32 hback_porch = edid->hback_porch.typ;
 100        u32 vsync_len = edid->vsync_len.typ;
 101        u32 vback_porch = edid->vback_porch.typ;
 102        u32 hfront_porch = edid->hfront_porch.typ;
 103        u32 vfront_porch = edid->vfront_porch.typ;
 104        uint flags;
 105        int mode_flags;
 106
 107        switch (mode) {
 108        case VOP_MODE_HDMI:
 109                clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 110                                V_HDMI_OUT_EN(1));
 111                break;
 112        case VOP_MODE_EDP:
 113        default:
 114                clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 115                                V_EDP_OUT_EN(1));
 116                break;
 117        case VOP_MODE_LVDS:
 118                clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 119                                V_RGB_OUT_EN(1));
 120                break;
 121        }
 122
 123        if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
 124                /* RGBaaa */
 125                mode_flags = 15;
 126        else
 127                /* RGB888 */
 128                mode_flags = 0;
 129
 130        flags = V_DSP_OUT_MODE(mode_flags) |
 131                V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
 132                V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
 133
 134        clrsetbits_le32(&regs->dsp_ctrl0,
 135                        M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
 136                        flags);
 137
 138        writel(V_HSYNC(hsync_len) |
 139               V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
 140                        &regs->dsp_htotal_hs_end);
 141
 142        writel(V_HEAP(hsync_len + hback_porch + hactive) |
 143               V_HASP(hsync_len + hback_porch),
 144               &regs->dsp_hact_st_end);
 145
 146        writel(V_VSYNC(vsync_len) |
 147               V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
 148               &regs->dsp_vtotal_vs_end);
 149
 150        writel(V_VAEP(vsync_len + vback_porch + vactive)|
 151               V_VASP(vsync_len + vback_porch),
 152               &regs->dsp_vact_st_end);
 153
 154        writel(V_HEAP(hsync_len + hback_porch + hactive) |
 155               V_HASP(hsync_len + hback_porch),
 156               &regs->post_dsp_hact_info);
 157
 158        writel(V_VAEP(vsync_len + vback_porch + vactive)|
 159               V_VASP(vsync_len + vback_porch),
 160               &regs->post_dsp_vact_info);
 161
 162        writel(0x01, &regs->reg_cfg_done); /* enable reg config */
 163}
 164
 165/**
 166 * rk_display_init() - Try to enable the given display device
 167 *
 168 * This function performs many steps:
 169 * - Finds the display device being referenced by @ep_node
 170 * - Puts the VOP's ID into its uclass platform data
 171 * - Probes the device to set it up
 172 * - Reads the EDID timing information
 173 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 174 * - Enables the display (the display device handles this and will do different
 175 *     things depending on the display type)
 176 * - Tells the uclass about the display resolution so that the console will
 177 *     appear correctly
 178 *
 179 * @dev:        VOP device that we want to connect to the display
 180 * @fbbase:     Frame buffer address
 181 * @l2bpp       Log2 of bits-per-pixels for the display
 182 * @ep_node:    Device tree node to process - this is the offset of an endpoint
 183 *              node within the VOP's 'port' list.
 184 * @return 0 if OK, -ve if something went wrong
 185 */
 186int rk_display_init(struct udevice *dev, ulong fbbase,
 187                    enum video_log2_bpp l2bpp, int ep_node)
 188{
 189        struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 190        const void *blob = gd->fdt_blob;
 191        struct rk_vop_priv *priv = dev_get_priv(dev);
 192        int vop_id, remote_vop_id;
 193        struct rk3288_vop *regs = priv->regs;
 194        struct display_timing timing;
 195        struct udevice *disp;
 196        int ret, remote, i, offset;
 197        struct display_plat *disp_uc_plat;
 198        struct clk clk;
 199
 200        vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
 201        debug("vop_id=%d\n", vop_id);
 202        remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
 203        if (remote < 0)
 204                return -EINVAL;
 205        remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
 206        debug("remote vop_id=%d\n", remote_vop_id);
 207
 208        for (i = 0, offset = remote; i < 3 && offset > 0; i++)
 209                offset = fdt_parent_offset(blob, offset);
 210        if (offset < 0) {
 211                debug("%s: Invalid remote-endpoint position\n", dev->name);
 212                return -EINVAL;
 213        }
 214
 215        ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
 216        if (ret) {
 217                debug("%s: device '%s' display not found (ret=%d)\n", __func__,
 218                      dev->name, ret);
 219                return ret;
 220        }
 221
 222        disp_uc_plat = dev_get_uclass_platdata(disp);
 223        debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
 224        if (display_in_use(disp)) {
 225                debug("   - device in use\n");
 226                return -EBUSY;
 227        }
 228
 229        disp_uc_plat->source_id = remote_vop_id;
 230        disp_uc_plat->src_dev = dev;
 231
 232        ret = device_probe(disp);
 233        if (ret) {
 234                debug("%s: device '%s' display won't probe (ret=%d)\n",
 235                      __func__, dev->name, ret);
 236                return ret;
 237        }
 238
 239        ret = display_read_timing(disp, &timing);
 240        if (ret) {
 241                debug("%s: Failed to read timings\n", __func__);
 242                return ret;
 243        }
 244
 245        ret = clk_get_by_index(dev, 1, &clk);
 246        if (!ret)
 247                ret = clk_set_rate(&clk, timing.pixelclock.typ);
 248        if (ret) {
 249                debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 250                return ret;
 251        }
 252
 253        rkvop_mode_set(regs, &timing, vop_id);
 254
 255        rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
 256
 257        ret = display_enable(disp, 1 << l2bpp, &timing);
 258        if (ret)
 259                return ret;
 260
 261        uc_priv->xsize = timing.hactive.typ;
 262        uc_priv->ysize = timing.vactive.typ;
 263        uc_priv->bpix = l2bpp;
 264        debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
 265
 266        return 0;
 267}
 268
 269static int rk_vop_probe(struct udevice *dev)
 270{
 271        struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 272        const void *blob = gd->fdt_blob;
 273        struct rk_vop_priv *priv = dev_get_priv(dev);
 274        struct udevice *reg;
 275        int ret, port, node;
 276
 277        /* Before relocation we don't need to do anything */
 278        if (!(gd->flags & GD_FLG_RELOC))
 279                return 0;
 280
 281        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 282        priv->regs = (struct rk3288_vop *)dev_get_addr(dev);
 283
 284        /* lcdc(vop) iodomain select 1.8V */
 285        rk_setreg(&priv->grf->io_vsel, 1 << 0);
 286
 287        /*
 288         * Try some common regulators. We should really get these from the
 289         * device tree somehow.
 290         */
 291        ret = regulator_autoset_by_name("vcc18_lcd", &reg);
 292        if (ret)
 293                debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
 294        ret = regulator_autoset_by_name("VCC18_LCD", &reg);
 295        if (ret)
 296                debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
 297        ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
 298        if (ret) {
 299                debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
 300                      __func__);
 301        }
 302        ret = regulator_autoset_by_name("vdd10_lcd", &reg);
 303        if (ret) {
 304                debug("%s: Cannot autoset regulator vdd10_lcd\n",
 305                      __func__);
 306        }
 307        ret = regulator_autoset_by_name("VDD10_LCD", &reg);
 308        if (ret) {
 309                debug("%s: Cannot autoset regulator VDD10_LCD\n",
 310                      __func__);
 311        }
 312        ret = regulator_autoset_by_name("vcc33_lcd", &reg);
 313        if (ret)
 314                debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);
 315
 316        /*
 317         * Try all the ports until we find one that works. In practice this
 318         * tries EDP first if available, then HDMI.
 319         *
 320         * Note that rockchip_vop_set_clk() always uses NPLL as the source
 321         * clock so it is currently not possible to use more than one display
 322         * device simultaneously.
 323         */
 324        port = fdt_subnode_offset(blob, dev->of_offset, "port");
 325        if (port < 0)
 326                return -EINVAL;
 327        for (node = fdt_first_subnode(blob, port);
 328             node > 0;
 329             node = fdt_next_subnode(blob, node)) {
 330                ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
 331                if (ret)
 332                        debug("Device failed: ret=%d\n", ret);
 333                if (!ret)
 334                        break;
 335        }
 336        video_set_flush_dcache(dev, 1);
 337
 338        return ret;
 339}
 340
 341static int rk_vop_bind(struct udevice *dev)
 342{
 343        struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 344
 345        plat->size = 1920 * 1080 * 2;
 346
 347        return 0;
 348}
 349
 350static const struct video_ops rk_vop_ops = {
 351};
 352
 353static const struct udevice_id rk_vop_ids[] = {
 354        { .compatible = "rockchip,rk3288-vop" },
 355        { }
 356};
 357
 358U_BOOT_DRIVER(rk_vop) = {
 359        .name   = "rk_vop",
 360        .id     = UCLASS_VIDEO,
 361        .of_match = rk_vop_ids,
 362        .ops    = &rk_vop_ops,
 363        .bind   = rk_vop_bind,
 364        .probe  = rk_vop_probe,
 365        .priv_auto_alloc_size   = sizeof(struct rk_vop_priv),
 366};
 367