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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_NAND_FSL_IFC
15
16#ifdef CONFIG_SPIFLASH
17#define CONFIG_RAMBOOT_SPIFLASH
18#define CONFIG_SYS_RAMBOOT
19#define CONFIG_SYS_EXTRA_ENV_RELOC
20#define CONFIG_SYS_TEXT_BASE 0x11000000
21#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
22#endif
23
24#ifdef CONFIG_NAND
25#define CONFIG_SPL_INIT_MINIMAL
26#define CONFIG_SPL_NAND_BOOT
27#define CONFIG_SPL_FLUSH_IMAGE
28#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29
30#define CONFIG_SYS_TEXT_BASE 0x00201000
31#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
32#define CONFIG_SPL_MAX_SIZE 8192
33#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
34#define CONFIG_SPL_RELOC_STACK 0x00100000
35#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
36#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
37#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
39#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
40#endif
41
42#ifdef CONFIG_SPL_BUILD
43#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
44#else
45#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
46#endif
47
48
49#define CONFIG_FSL_IFC
50#define CONFIG_FSL_CAAM
51
52#define CONFIG_TSEC_ENET
53#define CONFIG_ENV_OVERWRITE
54
55#define CONFIG_DDR_CLK_FREQ 66666666
56#if defined(CONFIG_SYS_CLK_100)
57#define CONFIG_SYS_CLK_FREQ 100000000
58#else
59#define CONFIG_SYS_CLK_FREQ 66666666
60#endif
61
62#define CONFIG_HWCONFIG
63
64
65
66#define CONFIG_L2_CACHE
67#define CONFIG_BTB
68
69#define CONFIG_SYS_MEMTEST_START 0x01000000
70#define CONFIG_SYS_MEMTEST_END 0x01ffffff
71
72
73#undef CONFIG_SYS_DDR_RAW_TIMING
74#undef CONFIG_DDR_SPD
75#define CONFIG_SYS_SPD_BUS_NUM 0
76#define SPD_EEPROM_ADDRESS 0x52
77
78#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
79
80#ifndef __ASSEMBLY__
81extern unsigned long get_sdram_size(void);
82#endif
83#define CONFIG_SYS_SDRAM_SIZE get_sdram_size()
84#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
86
87#define CONFIG_DIMM_SLOTS_PER_CTLR 1
88#define CONFIG_CHIP_SELECTS_PER_CTRL 1
89
90#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
91#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
92#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
93
94#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
95#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
96#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
97#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
98
99#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
100#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
101#define CONFIG_SYS_DDR_RCW_1 0x00000000
102#define CONFIG_SYS_DDR_RCW_2 0x00000000
103#define CONFIG_SYS_DDR_CONTROL 0xC70C0000
104#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
105#define CONFIG_SYS_DDR_TIMING_4 0x00000001
106#define CONFIG_SYS_DDR_TIMING_5 0x02401400
107
108#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
109#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
110#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
111#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
112#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
113#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
114#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
115#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
116#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
117
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121
122
123#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
124#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
125
126#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
127
128
129#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
130#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
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150
151#define CONFIG_SYS_NO_FLASH
152
153
154#define CONFIG_SYS_NAND_BASE 0xff800000
155#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
156
157#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
158 | CSPR_PORT_SIZE_8 \
159 | CSPR_MSEL_NAND \
160 | CSPR_V)
161#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
162
163#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
164 | CSOR_NAND_ECC_DEC_EN \
165 | CSOR_NAND_ECC_MODE_4 \
166 | CSOR_NAND_RAL_2 \
167 | CSOR_NAND_PGS_2K \
168 | CSOR_NAND_SPRZ_64 \
169 | CSOR_NAND_PB(64))
170
171
172#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
173 | FTIM0_NAND_TWP(0x05) \
174 | FTIM0_NAND_TWCHT(0x02) \
175 | FTIM0_NAND_TWH(0x04))
176#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
177 | FTIM1_NAND_TWBE(0x1E) \
178 | FTIM1_NAND_TRR(0x07) \
179 | FTIM1_NAND_TRP(0x05))
180#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
181 | FTIM2_NAND_TREH(0x04) \
182 | FTIM2_NAND_TWHRE(0x11))
183#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
184
185#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
186#define CONFIG_SYS_MAX_NAND_DEVICE 1
187#define CONFIG_CMD_NAND
188#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
189
190#define CONFIG_SYS_NAND_DDR_LAW 11
191
192
193#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
194#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
195#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
196#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
197#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
198#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
199#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
200
201#define CONFIG_BOARD_EARLY_INIT_F
202
203#define CONFIG_SYS_INIT_RAM_LOCK
204#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
205#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
206
207#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
208 - GENERATED_GBL_DATA_SIZE)
209#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210
211#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
212#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
213
214
215#define CONFIG_CONS_INDEX 1
216#undef CONFIG_SERIAL_SOFTWARE_FIFO
217#define CONFIG_SYS_NS16550_SERIAL
218#define CONFIG_SYS_NS16550_REG_SIZE 1
219#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220#ifdef CONFIG_SPL_BUILD
221#define CONFIG_NS16550_MIN_FUNCTIONS
222#endif
223
224#define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
226
227#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228
229#define CONFIG_SYS_I2C
230#define CONFIG_SYS_I2C_FSL
231#define CONFIG_SYS_FSL_I2C_SPEED 400000
232#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
234
235
236#define CONFIG_CMD_EEPROM
237#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
238#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
239#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
240
241
242#ifdef CONFIG_FSL_ESPI
243#define CONFIG_SF_DEFAULT_SPEED 10000000
244#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
245#endif
246
247#if defined(CONFIG_TSEC_ENET)
248
249#define CONFIG_MII
250#define CONFIG_MII_DEFAULT_TSEC 1
251#define CONFIG_TSEC1 1
252#define CONFIG_TSEC1_NAME "eTSEC1"
253#define CONFIG_TSEC2 1
254#define CONFIG_TSEC2_NAME "eTSEC2"
255
256#define TSEC1_PHY_ADDR 0
257#define TSEC2_PHY_ADDR 3
258
259#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
260#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
261
262#define TSEC1_PHYIDX 0
263
264#define TSEC2_PHYIDX 0
265
266#define CONFIG_ETHPRIME "eTSEC1"
267
268#define CONFIG_PHY_GIGE
269
270#endif
271
272
273
274
275#if defined(CONFIG_RAMBOOT_SPIFLASH)
276#define CONFIG_ENV_IS_IN_SPI_FLASH
277#define CONFIG_ENV_SPI_BUS 0
278#define CONFIG_ENV_SPI_CS 0
279#define CONFIG_ENV_SPI_MAX_HZ 10000000
280#define CONFIG_ENV_SPI_MODE 0
281#define CONFIG_ENV_OFFSET 0x100000
282#define CONFIG_ENV_SECT_SIZE 0x10000
283#define CONFIG_ENV_SIZE 0x2000
284#elif defined(CONFIG_NAND)
285#define CONFIG_ENV_IS_IN_NAND
286#define CONFIG_SYS_EXTRA_ENV_RELOC
287#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
288#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
289#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
290#elif defined(CONFIG_SYS_RAMBOOT)
291#define CONFIG_ENV_IS_NOWHERE
292#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
293#define CONFIG_ENV_SIZE 0x2000
294#endif
295
296#define CONFIG_LOADS_ECHO
297#define CONFIG_SYS_LOADS_BAUD_CHANGE
298
299
300
301
302#define CONFIG_CMD_ERRATA
303#define CONFIG_CMD_IRQ
304#define CONFIG_DOS_PARTITION
305#define CONFIG_CMD_REGINFO
306
307
308
309
310#define CONFIG_SYS_LONGHELP
311#define CONFIG_CMDLINE_EDITING
312#define CONFIG_AUTO_COMPLETE
313#define CONFIG_SYS_LOAD_ADDR 0x2000000
314
315#if defined(CONFIG_CMD_KGDB)
316#define CONFIG_SYS_CBSIZE 1024
317#else
318#define CONFIG_SYS_CBSIZE 1024
319#endif
320#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
321
322#define CONFIG_SYS_MAXARGS 16
323#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
324
325
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327
328
329
330#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
331#define CONFIG_SYS_BOOTM_LEN (64 << 20)
332
333#if defined(CONFIG_CMD_KGDB)
334#define CONFIG_KGDB_BAUDRATE 230400
335#endif
336
337
338#ifdef CONFIG_FSL_CAAM
339#define CONFIG_CMD_HASH
340#define CONFIG_SHA_HW_ACCEL
341#endif
342
343#define CONFIG_USB_EHCI
344
345#ifdef CONFIG_USB_EHCI
346#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
347#define CONFIG_USB_EHCI_FSL
348#define CONFIG_HAS_FSL_DR_USB
349#endif
350
351
352
353
354#define CONFIG_MTD_DEVICE
355#define CONFIG_MTD_PARTITIONS
356#define CONFIG_CMD_MTDPARTS
357#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
358#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
359 "8m(kernel),512k(dtb),-(fs)"
360
361
362
363
364
365#if defined(CONFIG_TSEC_ENET)
366#define CONFIG_HAS_ETH0
367#endif
368
369#define CONFIG_HOSTNAME BSC9131rdb
370#define CONFIG_ROOTPATH "/opt/nfsroot"
371#define CONFIG_BOOTFILE "uImage"
372#define CONFIG_UBOOTPATH "u-boot.bin"
373
374#define CONFIG_BAUDRATE 115200
375
376#define CONFIG_EXTRA_ENV_SETTINGS \
377 "netdev=eth0\0" \
378 "uboot=" CONFIG_UBOOTPATH "\0" \
379 "loadaddr=1000000\0" \
380 "bootfile=uImage\0" \
381 "consoledev=ttyS0\0" \
382 "ramdiskaddr=2000000\0" \
383 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
384 "fdtaddr=1e00000\0" \
385 "fdtfile=bsc9131rdb.dtb\0" \
386 "bdev=sda1\0" \
387 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
388 "bootm_size=0x37000000\0" \
389 "othbootargs=ramdisk_size=600000 " \
390 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
391 "usbext2boot=setenv bootargs root=/dev/ram rw " \
392 "console=$consoledev,$baudrate $othbootargs; " \
393 "usb start;" \
394 "ext2load usb 0:4 $loadaddr $bootfile;" \
395 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
396 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
397 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
398
399#define CONFIG_RAMBOOTCOMMAND \
400 "setenv bootargs root=/dev/ram rw " \
401 "console=$consoledev,$baudrate $othbootargs; " \
402 "tftp $ramdiskaddr $ramdiskfile;" \
403 "tftp $loadaddr $bootfile;" \
404 "tftp $fdtaddr $fdtfile;" \
405 "bootm $loadaddr $ramdiskaddr $fdtaddr"
406
407#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
408
409#endif
410