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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifdef CONFIG_SPIFLASH
15#define CONFIG_RAMBOOT_SPIFLASH
16#define CONFIG_SYS_TEXT_BASE 0x11000000
17#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
18#endif
19
20#ifdef CONFIG_NAND
21#ifdef CONFIG_TPL_BUILD
22#define CONFIG_SPL_NAND_BOOT
23#define CONFIG_SPL_FLUSH_IMAGE
24#define CONFIG_SPL_NAND_INIT
25#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
26#define CONFIG_SPL_COMMON_INIT_DDR
27#define CONFIG_SPL_MAX_SIZE (128 << 10)
28#define CONFIG_SPL_TEXT_BASE 0xf8f81000
29#define CONFIG_SYS_MPC85XX_NO_RESETVEC
30#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
31#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
32#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
33#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
34#elif defined(CONFIG_SPL_BUILD)
35#define CONFIG_SPL_INIT_MINIMAL
36#define CONFIG_SPL_NAND_MINIMAL
37#define CONFIG_SPL_FLUSH_IMAGE
38#define CONFIG_SPL_TEXT_BASE 0xff800000
39#define CONFIG_SPL_MAX_SIZE 8192
40#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
41#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
42#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
43#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
44#endif
45#define CONFIG_SPL_PAD_TO 0x20000
46#define CONFIG_TPL_PAD_TO 0x20000
47#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
48#define CONFIG_SYS_TEXT_BASE 0x11001000
49#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
50#endif
51
52#ifndef CONFIG_SYS_TEXT_BASE
53#define CONFIG_SYS_TEXT_BASE 0xeff40000
54#endif
55
56#ifndef CONFIG_RESET_VECTOR_ADDRESS
57#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
58#endif
59
60#ifdef CONFIG_SPL_BUILD
61#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
62#else
63#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
64#endif
65
66#ifdef CONFIG_SPL_BUILD
67#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68#endif
69
70
71#define CONFIG_FSL_IFC
72#define CONFIG_FSL_CAAM
73#define CONFIG_SYS_HAS_SERDES
74
75#ifdef CONFIG_PCI
76#define CONFIG_PCIE1
77#define CONFIG_FSL_PCI_INIT
78#define CONFIG_PCI_INDIRECT_BRIDGE
79#define CONFIG_FSL_PCIE_RESET
80#define CONFIG_SYS_PCI_64BIT
81
82#define CONFIG_CMD_PCI
83
84
85
86
87
88
89#define CONFIG_SYS_PCIE1_NAME "Slot 1"
90#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
91#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
92#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
93#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
94#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
95#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
96#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
97#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
98
99#define CONFIG_PCI_SCAN_SHOW
100#define CONFIG_DOS_PARTITION
101#endif
102
103#define CONFIG_TSEC_ENET
104#define CONFIG_ENV_OVERWRITE
105
106#define CONFIG_DDR_CLK_FREQ 100000000
107#define CONFIG_SYS_CLK_FREQ 66666666
108
109#define CONFIG_HWCONFIG
110
111
112
113
114#define CONFIG_L2_CACHE
115#define CONFIG_BTB
116
117#define CONFIG_ADDR_STREAMING
118
119#define CONFIG_ENABLE_36BIT_PHYS
120
121#define CONFIG_ADDR_MAP 1
122#define CONFIG_SYS_NUM_ADDR_MAP 16
123
124#define CONFIG_SYS_MEMTEST_START 0x00200000
125#define CONFIG_SYS_MEMTEST_END 0x00400000
126#define CONFIG_PANIC_HANG
127
128
129#define CONFIG_DDR_SPD
130#define CONFIG_SYS_SPD_BUS_NUM 0
131#define SPD_EEPROM_ADDRESS 0x50
132#define CONFIG_SYS_DDR_RAW_TIMING
133
134
135#define CONFIG_DDR_ECC
136#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
137#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
138
139#define CONFIG_SYS_SDRAM_SIZE 512
140#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
141#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142
143#define CONFIG_DIMM_SLOTS_PER_CTLR 1
144#define CONFIG_CHIP_SELECTS_PER_CTRL 1
145
146#define CONFIG_SYS_CCSRBAR 0xffe00000
147#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
148
149
150#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
151#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
152 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
153#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
154
155#ifdef CONFIG_SPL_BUILD
156#define CONFIG_SYS_NO_FLASH
157#endif
158
159
160
161
162
163#define CONFIG_SYS_FLASH_BASE 0xec000000
164#define CONFIG_SYS_MAX_FLASH_SECT 512
165
166#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
167
168#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
169#define CONFIG_SYS_MAX_FLASH_BANKS 1
170
171#define CONFIG_SYS_FLASH_QUIET_TEST
172#define CONFIG_FLASH_SHOW_PROGRESS 45
173#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
174#define CONFIG_SYS_FLASH_WRITE_TOUT 500
175
176
177#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
182#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
183
184#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
185 FTIM0_NOR_TEADC(0x5) | \
186 FTIM0_NOR_TEAHC(0x5))
187#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
188 FTIM1_NOR_TRAD_NOR(0x1A) |\
189 FTIM1_NOR_TSEQRAD_NOR(0x13))
190#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
191 FTIM2_NOR_TCH(0x4) | \
192 FTIM2_NOR_TWPH(0x0E) | \
193 FTIM2_NOR_TWP(0x1c))
194#define CONFIG_SYS_NOR_FTIM3 0x0
195
196
197#define CONFIG_FLASH_CFI_DRIVER
198#define CONFIG_SYS_FLASH_CFI
199#define CONFIG_SYS_FLASH_EMPTY_INFO
200#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
201
202
203#define CONFIG_NAND_FSL_IFC
204#define CONFIG_SYS_NAND_BASE 0xff800000
205#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
206
207#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
208
209#define CONFIG_SYS_MAX_NAND_DEVICE 1
210#define CONFIG_CMD_NAND
211#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
212
213
214#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
215 | CSPR_PORT_SIZE_8 \
216 | CSPR_MSEL_NAND \
217 | CSPR_V)
218#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
219#define CONFIG_SYS_NAND_OOBSIZE 0x00000280
220#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
221 | CSOR_NAND_ECC_DEC_EN \
222 | CSOR_NAND_ECC_MODE_4 \
223 | CSOR_NAND_RAL_3 \
224 | CSOR_NAND_PGS_8K \
225 | CSOR_NAND_SPRZ_CSOR_EXT \
226 | CSOR_NAND_PB(128))
227#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
228 FTIM0_NAND_TWP(0x0c) | \
229 FTIM0_NAND_TWCHT(0x08) | \
230 FTIM0_NAND_TWH(0x06))
231#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
232 FTIM1_NAND_TWBE(0x1d) | \
233 FTIM1_NAND_TRR(0x08) | \
234 FTIM1_NAND_TRP(0x0c))
235#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
236 FTIM2_NAND_TREH(0x0a) | \
237 FTIM2_NAND_TWHRE(0x18))
238#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
239
240#define CONFIG_SYS_NAND_DDR_LAW 11
241
242
243#ifdef CONFIG_NAND
244#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
245#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
246#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
247#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
248#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
249#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
250#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
251#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
252#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
253#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
254#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
255#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
256#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
257#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
258#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
259#else
260#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
261#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
262#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
263#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
264#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
265#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
266#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
267#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
268#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
269#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
270#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
271#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
272#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
273#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
274#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
275#endif
276
277
278#define CONFIG_SYS_CPLD_BASE 0xffdf0000
279#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
280 | CONFIG_SYS_CPLD_BASE)
281
282#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
283 | CSPR_PORT_SIZE_8 \
284 | CSPR_MSEL_GPCM \
285 | CSPR_V)
286#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
287#define CONFIG_SYS_CSOR2 0x0
288
289#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
290 FTIM0_GPCM_TEADC(0x0e) | \
291 FTIM0_GPCM_TEAHC(0x0e))
292#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
293 FTIM1_GPCM_TRAD(0x1f))
294#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
295 FTIM2_GPCM_TCH(0x8) | \
296 FTIM2_GPCM_TWP(0x1f))
297#define CONFIG_SYS_CS2_FTIM3 0x0
298
299#if defined(CONFIG_RAMBOOT_SPIFLASH)
300#define CONFIG_SYS_RAMBOOT
301#define CONFIG_SYS_EXTRA_ENV_RELOC
302#endif
303
304#define CONFIG_BOARD_EARLY_INIT_R
305
306#define CONFIG_SYS_INIT_RAM_LOCK
307#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
308#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
309
310#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
311 - GENERATED_GBL_DATA_SIZE)
312#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
313
314#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
315#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
316
317
318
319
320#if defined(CONFIG_SPL_BUILD)
321#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
322#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
323#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
324#define CONFIG_SYS_L2_SIZE (256 << 10)
325#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
326#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
327#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
328#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
329#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
330#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
331#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
332#elif defined(CONFIG_NAND)
333#ifdef CONFIG_TPL_BUILD
334#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
335#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
336#define CONFIG_SYS_L2_SIZE (256 << 10)
337#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
338#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
339#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
340#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
341#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
342#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
343#else
344#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
345#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
346#define CONFIG_SYS_L2_SIZE (256 << 10)
347#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
348#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
349#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
350#endif
351#endif
352#endif
353
354
355#define CONFIG_CONS_INDEX 1
356#define CONFIG_SYS_NS16550_SERIAL
357#define CONFIG_SYS_NS16550_REG_SIZE 1
358#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
359
360#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
361#define CONFIG_NS16550_MIN_FUNCTIONS
362#endif
363
364#define CONFIG_SYS_BAUDRATE_TABLE \
365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
366
367#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
368#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
369
370#define CONFIG_SYS_I2C
371#define CONFIG_SYS_I2C_FSL
372#define CONFIG_SYS_FSL_I2C_SPEED 400000
373#define CONFIG_SYS_FSL_I2C2_SPEED 400000
374#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
375#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
376#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
377#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
378
379
380
381#define CONFIG_CMD_EEPROM
382#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
383#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
384#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
385
386
387#define CONFIG_SF_DEFAULT_SPEED 10000000
388#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
389
390#ifdef CONFIG_TSEC_ENET
391#define CONFIG_MII
392#define CONFIG_MII_DEFAULT_TSEC 1
393#define CONFIG_TSEC1 1
394#define CONFIG_TSEC1_NAME "eTSEC1"
395#define CONFIG_TSEC2 1
396#define CONFIG_TSEC2_NAME "eTSEC2"
397
398
399#define TSEC1_PHY_ADDR 0
400#define TSEC2_PHY_ADDR 2
401
402#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
403#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
404
405#define CONFIG_ETHPRIME "eTSEC1"
406
407#define CONFIG_PHY_GIGE
408#endif
409
410
411
412
413#if defined(CONFIG_SYS_RAMBOOT)
414#if defined(CONFIG_RAMBOOT_SPIFLASH)
415#define CONFIG_ENV_IS_IN_SPI_FLASH
416#define CONFIG_ENV_SPI_BUS 0
417#define CONFIG_ENV_SPI_CS 0
418#define CONFIG_ENV_SPI_MAX_HZ 10000000
419#define CONFIG_ENV_SPI_MODE 0
420#define CONFIG_ENV_OFFSET 0x100000
421#define CONFIG_ENV_SECT_SIZE 0x10000
422#define CONFIG_ENV_SIZE 0x2000
423#endif
424#elif defined(CONFIG_NAND)
425#define CONFIG_ENV_IS_IN_NAND
426#ifdef CONFIG_TPL_BUILD
427#define CONFIG_ENV_SIZE 0x2000
428#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
429#else
430#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
431#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
432#endif
433#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
434#else
435#define CONFIG_ENV_IS_IN_FLASH
436#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
437#define CONFIG_ENV_SIZE 0x2000
438#define CONFIG_ENV_SECT_SIZE 0x20000
439#endif
440
441#define CONFIG_LOADS_ECHO
442#define CONFIG_SYS_LOADS_BAUD_CHANGE
443
444
445
446
447#define CONFIG_CMD_ERRATA
448#define CONFIG_CMD_IRQ
449#define CONFIG_CMD_REGINFO
450
451
452#ifdef CONFIG_FSL_CAAM
453#define CONFIG_CMD_HASH
454#define CONFIG_SHA_HW_ACCEL
455#endif
456
457
458
459
460#define CONFIG_SYS_LONGHELP
461#define CONFIG_CMDLINE_EDITING
462#define CONFIG_AUTO_COMPLETE
463#define CONFIG_SYS_LOAD_ADDR 0x2000000
464
465#define CONFIG_SYS_CBSIZE 256
466#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
467
468#define CONFIG_SYS_MAXARGS 16
469#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
470
471
472
473
474
475
476#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
477#define CONFIG_SYS_BOOTM_LEN (64 << 20)
478
479
480
481
482
483#ifdef CONFIG_TSEC_ENET
484#define CONFIG_HAS_ETH0
485#define CONFIG_HAS_ETH1
486#endif
487
488#define CONFIG_ROOTPATH "/opt/nfsroot"
489#define CONFIG_BOOTFILE "uImage"
490#define CONFIG_UBOOTPATH u-boot.bin
491
492
493#define CONFIG_LOADADDR 1000000
494
495
496#define CONFIG_BAUDRATE 115200
497
498#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
499
500#define CONFIG_EXTRA_ENV_SETTINGS \
501 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
502 "netdev=eth0\0" \
503 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
504 "loadaddr=1000000\0" \
505 "consoledev=ttyS0\0" \
506 "ramdiskaddr=2000000\0" \
507 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
508 "fdtaddr=1e00000\0" \
509 "fdtfile=name/of/device-tree.dtb\0" \
510 "othbootargs=ramdisk_size=600000\0" \
511
512#define CONFIG_RAMBOOTCOMMAND \
513 "setenv bootargs root=/dev/ram rw " \
514 "console=$consoledev,$baudrate $othbootargs; " \
515 "tftp $ramdiskaddr $ramdiskfile;" \
516 "tftp $loadaddr $bootfile;" \
517 "tftp $fdtaddr $fdtfile;" \
518 "bootm $loadaddr $ramdiskaddr $fdtaddr"
519
520#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
521
522#include <asm/fsl_secure_boot.h>
523
524#endif
525