LXR uboot/include/configs/bf518f-ezbrd.h

   1/*
   2 * U-Boot - Configuration file for BF518F EZBrd board
   3 */
   4
   5#ifndef __CONFIG_BF518F_EZBRD_H__
   6#define __CONFIG_BF518F_EZBRD_H__
   7
   8#include <asm/config-pre.h>
   9
  10/*
  11 * Processor Settings
  12 */
  13#define CONFIG_BFIN_CPU             bf518-0.0
  14#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
  15
  16/*
  17 * Clock Settings
  18 *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  19 *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  20 */
  21/* CONFIG_CLKIN_HZ is any value in Hz                                   */
  22#define CONFIG_CLKIN_HZ                 25000000
  23/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  24/*                                                1 = CLKIN / 2         */
  25#define CONFIG_CLKIN_HALF               0
  26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  27/*                                                1 = bypass PLL        */
  28#define CONFIG_PLL_BYPASS               0
  29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  30/* Values can range from 0-63 (where 0 means 64)                        */
  31#define CONFIG_VCO_MULT                 16
  32/* CCLK_DIV controls the core clock divider                             */
  33/* Values can be 1, 2, 4, or 8 ONLY                                     */
  34#define CONFIG_CCLK_DIV                 1
  35/* SCLK_DIV controls the system clock divider                           */
  36/* Values can range from 1-15                                           */
  37#define CONFIG_SCLK_DIV                 5
  38
  39/*
  40 * Memory Settings
  41 */
  42/* This board has a 64meg MT48H32M16 */
  43#define CONFIG_MEM_ADD_WDTH     10
  44#define CONFIG_MEM_SIZE         64
  45
  46#define CONFIG_EBIU_SDRRC_VAL   0x0096
  47#define CONFIG_EBIU_SDGCTL_VAL  (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
  48
  49#define CONFIG_EBIU_AMGCTL_VAL  (AMCKEN | AMBEN_ALL)
  50#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
  51#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
  52
  53#define CONFIG_SYS_MONITOR_LEN  (512 * 1024)
  54#define CONFIG_SYS_MALLOC_LEN   (384 * 1024)
  55
  56/*
  57 * Network Settings
  58 */
  59#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
  60#define ADI_CMDS_NETWORK        1
  61#define CONFIG_BFIN_MAC
  62#define CONFIG_BFIN_MAC_PINS \
  63        { \
  64        P_MII0_ETxD0, \
  65        P_MII0_ETxD1, \
  66        P_MII0_ETxD2, \
  67        P_MII0_ETxD3, \
  68        P_MII0_ETxEN, \
  69        P_MII0_TxCLK, \
  70        P_MII0_PHYINT, \
  71        P_MII0_COL, \
  72        P_MII0_ERxD0, \
  73        P_MII0_ERxD1, \
  74        P_MII0_ERxD2, \
  75        P_MII0_ERxD3, \
  76        P_MII0_ERxDV, \
  77        P_MII0_ERxCLK, \
  78        P_MII0_CRS, \
  79        P_MII0_MDC, \
  80        P_MII0_MDIO, \
  81        0 }
  82#define CONFIG_NETCONSOLE       1
  83#endif
  84#define CONFIG_HOSTNAME         bf518f-ezbrd
  85#define CONFIG_PHY_ADDR         3
  86
  87/*
  88 * Flash Settings
  89 */
  90#define CONFIG_FLASH_CFI_DRIVER
  91#define CONFIG_SYS_FLASH_BASE           0x20000000
  92#define CONFIG_SYS_FLASH_CFI
  93#define CONFIG_SYS_FLASH_PROTECTION
  94#define CONFIG_SYS_MAX_FLASH_BANKS      1
  95#define CONFIG_SYS_MAX_FLASH_SECT       71
  96
  97/*
  98 * SPI Settings
  99 */
 100#define CONFIG_BFIN_SPI
 101#define CONFIG_ENV_SPI_MAX_HZ   30000000
 102#define CONFIG_SF_DEFAULT_SPEED 30000000
 103
 104/*
 105 * Env Storage Settings
 106 */
 107#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 108#define CONFIG_ENV_IS_IN_SPI_FLASH
 109#define CONFIG_ENV_OFFSET       0x10000
 110#define CONFIG_ENV_SIZE         0x2000
 111#define CONFIG_ENV_SECT_SIZE    0x10000
 112#else
 113#define CONFIG_ENV_IS_IN_FLASH
 114#define CONFIG_ENV_OFFSET       0x4000
 115#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 116#define CONFIG_ENV_SIZE         0x2000
 117#define CONFIG_ENV_SECT_SIZE    0x2000
 118#endif
 119#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 120
 121/*
 122 * I2C Settings
 123 */
 124#define CONFIG_SYS_I2C
 125#define CONFIG_SYS_I2C_ADI
 126
 127/*
 128 * SDH Settings
 129 */
 130#if !defined(__ADSPBF512__)
 131#define CONFIG_GENERIC_MMC
 132#define CONFIG_BFIN_SDH
 133#endif
 134
 135/*
 136 * Misc Settings
 137 */
 138#define CONFIG_BOARD_EARLY_INIT_F
 139#define CONFIG_MISC_INIT_R
 140#define CONFIG_RTC_BFIN
 141#define CONFIG_UART_CONSOLE     0
 142
 143/*
 144 * Pull in common ADI header for remaining command/environment setup
 145 */
 146#include <configs/bfin_adi_common.h>
 147
 148#endif
 149