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17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20
21#define CONFIG_SOCRATES 1
22
23#define CONFIG_SYS_TEXT_BASE 0xfff80000
24
25#define CONFIG_PCI_INDIRECT_BRIDGE
26
27#define CONFIG_TSEC_ENET
28
29#define CONFIG_MISC_INIT_R 1
30#define CONFIG_BOARD_EARLY_INIT_R 1
31
32
33
34
35#define CONFIG_ENABLE_36BIT_PHYS 1
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51#ifndef CONFIG_SYS_CLK_FREQ
52#define CONFIG_SYS_CLK_FREQ 66666666
53#endif
54
55
56
57
58#define CONFIG_L2_CACHE
59#define CONFIG_BTB
60
61#define CONFIG_SYS_INIT_DBCR DBCR_IDM
62
63#undef CONFIG_SYS_DRAM_TEST
64#define CONFIG_SYS_MEMTEST_START 0x00400000
65#define CONFIG_SYS_MEMTEST_END 0x00C00000
66
67#define CONFIG_SYS_CCSRBAR 0xE0000000
68#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
69
70
71#undef CONFIG_FSL_DDR_INTERACTIVE
72#define CONFIG_SPD_EEPROM
73#define CONFIG_DDR_SPD
74
75#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
76#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77
78#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
79#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
80#define CONFIG_VERY_BIG_RAM
81
82#define CONFIG_DIMM_SLOTS_PER_CTLR 1
83#define CONFIG_CHIP_SELECTS_PER_CTRL 2
84
85
86#define SPD_EEPROM_ADDRESS 0x50
87
88#define CONFIG_DDR_DEFAULT_CL 30
89
90
91#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
92#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
93#define CONFIG_SYS_DDR_TIMING_0 0x00260802
94#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
95#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
96#define CONFIG_SYS_DDR_MODE 0x00480432
97#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
98#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
99#define CONFIG_SYS_DDR_CONFIG 0xC3008000
100#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
101#define CONFIG_SYS_SDRAM_SIZE 256
102
103
104
105
106#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000
107
108#define CONFIG_SYS_FLASH0 0xFE000000
109#define CONFIG_SYS_FLASH1 0xFC000000
110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
111
112#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1
113#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE
114
115#define CONFIG_SYS_BR0_PRELIM 0xfe001001
116#define CONFIG_SYS_OR0_PRELIM 0xfe000030
117#define CONFIG_SYS_BR1_PRELIM 0xfc001001
118#define CONFIG_SYS_OR1_PRELIM 0xfe000030
119
120#define CONFIG_SYS_FLASH_CFI
121#define CONFIG_FLASH_CFI_DRIVER
122
123#define CONFIG_SYS_MAX_FLASH_BANKS 2
124#define CONFIG_SYS_MAX_FLASH_SECT 256
125#undef CONFIG_SYS_FLASH_CHECKSUM
126#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500
128
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
130
131#define CONFIG_SYS_LBC_LCRR 0x00030004
132#define CONFIG_SYS_LBC_LBCR 0x00000000
133#define CONFIG_SYS_LBC_LSRT 0x20000000
134#define CONFIG_SYS_LBC_MRTPR 0x20000000
135
136#define CONFIG_SYS_INIT_RAM_LOCK 1
137#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
138#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
139
140#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
142
143#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
144#define CONFIG_SYS_MALLOC_LEN (4 << 20)
145
146
147#define CONFIG_SYS_FPGA_BASE 0xc0000000
148#define CONFIG_SYS_FPGA_SIZE 0x00100000
149#define CONFIG_SYS_HMI_BASE 0xc0010000
150#define CONFIG_SYS_BR3_PRELIM 0xc0001881
151#define CONFIG_SYS_OR3_PRELIM 0xfff00000
152
153#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
154#define CONFIG_SYS_MAX_NAND_DEVICE 1
155#define CONFIG_CMD_NAND
156
157
158#define CONFIG_SYS_LIME_BASE 0xc8000000
159#define CONFIG_SYS_LIME_SIZE 0x04000000
160#define CONFIG_SYS_BR2_PRELIM 0xc80018a1
161#define CONFIG_SYS_OR2_PRELIM 0xfc000000
162
163#define CONFIG_VIDEO_MB862xx
164#define CONFIG_VIDEO_MB862xx_ACCEL
165#define CONFIG_VIDEO_LOGO
166#define CONFIG_VIDEO_BMP_LOGO
167#define VIDEO_FB_16BPP_PIXEL_SWAP
168#define VIDEO_FB_16BPP_WORD_SWAP
169#define CONFIG_SPLASH_SCREEN
170#define CONFIG_VIDEO_BMP_GZIP
171#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
172
173
174#define CONFIG_SYS_MB862xx_CCF 0x10000
175
176#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
177
178
179
180#define CONFIG_CONS_INDEX 1
181#define CONFIG_SYS_NS16550_SERIAL
182#define CONFIG_SYS_NS16550_REG_SIZE 1
183#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
184
185#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
187
188#define CONFIG_BAUDRATE 115200
189
190#define CONFIG_SYS_BAUDRATE_TABLE \
191 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
192
193#define CONFIG_CMDLINE_EDITING 1
194#define CONFIG_AUTO_COMPLETE 1
195
196
197
198
199#define CONFIG_SYS_I2C
200#define CONFIG_SYS_I2C_FSL
201#define CONFIG_SYS_FSL_I2C_SPEED 102124
202#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
203#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
204#define CONFIG_SYS_FSL_I2C2_SPEED 102124
205#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
206#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
207
208
209#define CONFIG_RTC_RX8025
210#define CONFIG_SYS_I2C_RTC_ADDR 0x32
211
212
213#define CONFIG_SYS_I2C_W83782G_ADDR 0x28
214
215
216
217#define CONFIG_DTT_LM75 1
218#define CONFIG_DTT_SENSORS {4}
219#define CONFIG_SYS_DTT_MAX_TEMP 125
220#define CONFIG_SYS_DTT_LOW_TEMP -55
221#define CONFIG_SYS_DTT_HYSTERESIS 3
222#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
223
224
225
226
227
228#define CONFIG_SYS_PCI_PHYS 0x80000000
229
230
231#define CONFIG_PCI_CLK_FREQ 33000000
232#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
233#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
234#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
235#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
236#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
237#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
238
239#if defined(CONFIG_PCI)
240#undef CONFIG_PCI_SCAN_SHOW
241#endif
242
243#define CONFIG_MII 1
244#define CONFIG_TSEC1 1
245#define CONFIG_TSEC1_NAME "TSEC0"
246#define CONFIG_TSEC3 1
247#define CONFIG_TSEC3_NAME "TSEC1"
248#undef CONFIG_MPC85XX_FEC
249
250#define TSEC1_PHY_ADDR 0
251#define TSEC3_PHY_ADDR 1
252
253#define TSEC1_PHYIDX 0
254#define TSEC3_PHYIDX 0
255#define TSEC1_FLAGS TSEC_GIGABIT
256#define TSEC3_FLAGS TSEC_GIGABIT
257
258
259#define CONFIG_ETHPRIME "TSEC0"
260#define CONFIG_PHY_GIGE 1
261
262#define CONFIG_HAS_ETH0
263#define CONFIG_HAS_ETH1
264
265
266
267
268#define CONFIG_ENV_IS_IN_FLASH 1
269#define CONFIG_ENV_SECT_SIZE 0x20000
270#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
271#define CONFIG_ENV_SIZE 0x4000
272#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
273#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
274
275#define CONFIG_LOADS_ECHO 1
276#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
277
278#define CONFIG_TIMESTAMP
279
280
281
282
283#define CONFIG_BOOTP_BOOTFILESIZE
284#define CONFIG_BOOTP_BOOTPATH
285#define CONFIG_BOOTP_GATEWAY
286#define CONFIG_BOOTP_HOSTNAME
287
288
289
290
291#define CONFIG_CMD_BMP
292#define CONFIG_CMD_DATE
293#define CONFIG_CMD_DTT
294#undef CONFIG_CMD_EEPROM
295#define CONFIG_CMD_SDRAM
296#define CONFIG_CMD_REGINFO
297
298#if defined(CONFIG_PCI)
299 #define CONFIG_CMD_PCI
300#endif
301
302#undef CONFIG_WATCHDOG
303
304
305
306
307#define CONFIG_SYS_LONGHELP
308#define CONFIG_SYS_LOAD_ADDR 0x2000000
309
310#if defined(CONFIG_CMD_KGDB)
311 #define CONFIG_SYS_CBSIZE 1024
312#else
313 #define CONFIG_SYS_CBSIZE 256
314#endif
315
316#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
317#define CONFIG_SYS_MAXARGS 16
318#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
319
320
321
322
323
324
325#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
326
327#if defined(CONFIG_CMD_KGDB)
328#define CONFIG_KGDB_BAUDRATE 230400
329#endif
330
331#define CONFIG_LOADADDR 200000
332
333
334#define CONFIG_PREBOOT "echo;" \
335 "echo Welcome on the ABB Socrates Board;" \
336 "echo"
337
338#undef CONFIG_BOOTARGS
339
340#define CONFIG_EXTRA_ENV_SETTINGS \
341 "netdev=eth0\0" \
342 "consdev=ttyS0\0" \
343 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
344 "bootfile=/home/tftp/syscon3/uImage\0" \
345 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
346 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
347 "uboot_addr=FFFA0000\0" \
348 "kernel_addr=FE000000\0" \
349 "fdt_addr=FE1E0000\0" \
350 "ramdisk_addr=FE200000\0" \
351 "fdt_addr_r=B00000\0" \
352 "kernel_addr_r=200000\0" \
353 "ramdisk_addr_r=400000\0" \
354 "rootpath=/opt/eldk/ppc_85xxDP\0" \
355 "ramargs=setenv bootargs root=/dev/ram rw\0" \
356 "nfsargs=setenv bootargs root=/dev/nfs rw " \
357 "nfsroot=$serverip:$rootpath\0" \
358 "addcons=setenv bootargs $bootargs " \
359 "console=$consdev,$baudrate\0" \
360 "addip=setenv bootargs $bootargs " \
361 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
362 ":$hostname:$netdev:off panic=1\0" \
363 "boot_nor=run ramargs addcons;" \
364 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
365 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
366 "tftp ${fdt_addr_r} ${fdt_file}; " \
367 "run nfsargs addip addcons;" \
368 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
369 "update_uboot=tftp 100000 ${uboot_file};" \
370 "protect off fffa0000 ffffffff;" \
371 "era fffa0000 ffffffff;" \
372 "cp.b 100000 fffa0000 ${filesize};" \
373 "setenv filesize;saveenv\0" \
374 "update_kernel=tftp 100000 ${bootfile};" \
375 "era fe000000 fe1dffff;" \
376 "cp.b 100000 fe000000 ${filesize};" \
377 "setenv filesize;saveenv\0" \
378 "update_fdt=tftp 100000 ${fdt_file};" \
379 "era fe1e0000 fe1fffff;" \
380 "cp.b 100000 fe1e0000 ${filesize};" \
381 "setenv filesize;saveenv\0" \
382 "update_initrd=tftp 100000 ${initrd_file};" \
383 "era fe200000 fe9fffff;" \
384 "cp.b 100000 fe200000 ${filesize};" \
385 "setenv filesize;saveenv\0" \
386 "clean_data=era fea00000 fff5ffff\0" \
387 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
388 "load_usb=usb start;" \
389 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
390 "boot_usb=run load_usb usbargs addcons;" \
391 "bootm ${kernel_addr_r} - ${fdt_addr};" \
392 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
393 ""
394#define CONFIG_BOOTCOMMAND "run boot_nor"
395
396
397
398
399#define CONFIG_USB_OHCI_NEW 1
400#define CONFIG_PCI_OHCI 1
401#define CONFIG_PCI_OHCI_DEVNO 3
402#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
403#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
404#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
405#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
406#define CONFIG_DOS_PARTITION 1
407
408#endif
409