1/* 2 * WORK Microwave work_92105 board configuration file 3 * 4 * (C) Copyright 2014 DENX Software Engineering GmbH 5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __CONFIG_WORK_92105_H__ 11#define __CONFIG_WORK_92105_H__ 12 13/* SoC and board defines */ 14#include <linux/sizes.h> 15#include <asm/arch/cpu.h> 16 17/* 18 * Define work_92105 machine type by hand -- done only for compatibility 19 * with original board code 20 */ 21#define MACH_TYPE_WORK_92105 736 22#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105 23 24#define CONFIG_SYS_ICACHE_OFF 25#define CONFIG_SYS_DCACHE_OFF 26#if !defined(CONFIG_SPL_BUILD) 27#define CONFIG_SKIP_LOWLEVEL_INIT 28#endif 29#define CONFIG_BOARD_EARLY_INIT_F 30#define CONFIG_BOARD_EARLY_INIT_R 31 32/* generate LPC32XX-specific SPL image */ 33#define CONFIG_LPC32XX_SPL 34 35/* 36 * Memory configurations 37 */ 38#define CONFIG_NR_DRAM_BANKS 1 39#define CONFIG_SYS_MALLOC_LEN SZ_1M 40#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 41#define CONFIG_SYS_SDRAM_SIZE SZ_128M 42#define CONFIG_SYS_TEXT_BASE 0x80100000 43#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 45 46#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 47 48#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ 49 - GENERATED_GBL_DATA_SIZE) 50 51/* 52 * Serial Driver 53 */ 54#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ 55#define CONFIG_BAUDRATE 115200 56 57/* 58 * Ethernet Driver 59 */ 60 61#define CONFIG_PHY_SMSC 62#define CONFIG_LPC32XX_ETH 63#define CONFIG_PHYLIB 64#define CONFIG_PHY_ADDR 0 65#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ 67 68/* 69 * I2C driver 70 */ 71 72#define CONFIG_SYS_I2C_LPC32XX 73#define CONFIG_SYS_I2C 74#define CONFIG_SYS_I2C_SPEED 350000 75 76/* 77 * I2C EEPROM 78 */ 79 80#define CONFIG_CMD_EEPROM 81#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 82#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 83 84/* 85 * I2C RTC 86 */ 87 88#define CONFIG_CMD_DATE 89#define CONFIG_RTC_DS1374 90 91/* 92 * I2C Temperature Sensor (DTT) 93 */ 94 95#define CONFIG_CMD_DTT 96#define CONFIG_DTT_SENSORS { 0, 1 } 97#define CONFIG_DTT_DS620 98 99/* 100 * U-Boot General Configurations 101 */ 102#define CONFIG_SYS_LONGHELP 103#define CONFIG_SYS_CBSIZE 1024 104#define CONFIG_SYS_PBSIZE \ 105 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 106#define CONFIG_SYS_MAXARGS 16 107#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 108 109#define CONFIG_AUTO_COMPLETE 110#define CONFIG_CMDLINE_EDITING 111#define CONFIG_DOS_PARTITION 112 113/* 114 * No NOR 115 */ 116 117#define CONFIG_SYS_NO_FLASH 118 119/* 120 * NAND chip timings for FIXME: which one? 121 */ 122 123#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 124#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 125#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 126#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 127#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 128#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 129#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 130 131/* 132 * NAND 133 */ 134 135/* driver configuration */ 136#define CONFIG_SYS_NAND_SELF_INIT 137#define CONFIG_SYS_MAX_NAND_DEVICE 1 138#define CONFIG_SYS_MAX_NAND_CHIPS 1 139#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE 140#define CONFIG_NAND_LPC32XX_MLC 141 142#define CONFIG_CMD_NAND 143 144/* 145 * GPIO 146 */ 147 148#define CONFIG_LPC32XX_GPIO 149 150/* 151 * SSP/SPI/DISPLAY 152 */ 153 154#define CONFIG_LPC32XX_SSP 155#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 156#define CONFIG_CMD_MAX6957 157#define CONFIG_CMD_HD44760 158/* 159 * Environment 160 */ 161 162#define CONFIG_ENV_IS_IN_NAND 1 163#define CONFIG_ENV_SIZE 0x00020000 164#define CONFIG_ENV_OFFSET 0x00100000 165#define CONFIG_ENV_OFFSET_REDUND 0x00120000 166#define CONFIG_ENV_ADDR 0x80000100 167 168/* 169 * Boot Linux 170 */ 171#define CONFIG_CMDLINE_TAG 172#define CONFIG_SETUP_MEMORY_TAGS 173#define CONFIG_INITRD_TAG 174 175#define CONFIG_BOOTFILE "uImage" 176#define CONFIG_BOOTARGS "console=ttyS2,115200n8" 177#define CONFIG_LOADADDR 0x80008000 178 179/* 180 * SPL 181 */ 182 183/* SPL will be executed at offset 0 */ 184#define CONFIG_SPL_TEXT_BASE 0x00000000 185/* SPL will use SRAM as stack */ 186#define CONFIG_SPL_STACK 0x0000FFF8 187#define CONFIG_SPL_BOARD_INIT 188/* Use the framework and generic lib */ 189#define CONFIG_SPL_FRAMEWORK 190/* SPL will use serial */ 191/* SPL will load U-Boot from NAND offset 0x40000 */ 192#define CONFIG_SPL_NAND_DRIVERS 193#define CONFIG_SPL_NAND_BASE 194#define CONFIG_SPL_NAND_BOOT 195#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 196#define CONFIG_SPL_PAD_TO 0x20000 197/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 198#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ 199#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 200#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 201 202/* 203 * Include SoC specific configuration 204 */ 205#include <asm/arch/config.h> 206 207#endif /* __CONFIG_WORK_92105_H__*/ 208