1/* 2 * (C) Copyright 2011 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * 5 * (C) Copyright 2015 6 * Kamil Lulko, <kamil.lulko@gmail.com> 7 * 8 * Copyright 2015 ATS Advanced Telematics Systems GmbH 9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#ifndef _MACH_STM32_H_ 15#define _MACH_STM32_H_ 16 17/* 18 * Peripheral memory map 19 */ 20#define STM32_PERIPH_BASE 0x40000000 21#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) 22#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) 23#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000) 24 25#define STM32_BUS_MASK 0xFFFF0000 26 27#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) 28#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) 29#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) 30#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) 31#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) 32#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) 33#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) 34 35/* 36 * Register maps 37 */ 38struct stm32_des_regs { 39 u16 flash_size; 40 u16 pad1; 41 u32 pad2; 42 u32 uid0; 43 u32 uid1; 44 u32 uid2; 45}; 46 47struct stm32_rcc_regs { 48 u32 cr; /* RCC clock control */ 49 u32 cfgr; /* RCC clock configuration */ 50 u32 cir; /* RCC clock interrupt */ 51 u32 apb2rstr; /* RCC APB2 peripheral reset */ 52 u32 apb1rstr; /* RCC APB1 peripheral reset */ 53 u32 ahbenr; /* RCC AHB peripheral clock enable */ 54 u32 apb2enr; /* RCC APB2 peripheral clock enable */ 55 u32 apb1enr; /* RCC APB1 peripheral clock enable */ 56 u32 bdcr; /* RCC Backup domain control */ 57 u32 csr; /* RCC clock control & status */ 58}; 59 60struct stm32_pwr_regs { 61 u32 cr; 62 u32 csr; 63}; 64 65struct stm32_flash_regs { 66 u32 acr; 67 u32 keyr; 68 u32 optkeyr; 69 u32 sr; 70 u32 cr; 71 u32 ar; 72 u32 rsvd1; /* Reserved */ 73 u32 obr; 74 u32 wrpr; 75 u32 rsvd2[8]; /* Reserved */ 76 u32 keyr2; 77 u32 rsvd3; 78 u32 sr2; 79 u32 cr2; 80 u32 ar2; 81}; 82 83/* Per bank register set for XL devices */ 84struct stm32_flash_bank_regs { 85 u32 keyr; 86 u32 rsvd; /* Reserved */ 87 u32 sr; 88 u32 cr; 89 u32 ar; 90}; 91 92/* 93 * Registers access macros 94 */ 95#define STM32_DES_BASE (0x1ffff7e0) 96#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE) 97 98#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000) 99#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) 100 101#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) 102#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) 103 104#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000) 105#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) 106 107#define STM32_FLASH_SR_BSY (1 << 0) 108 109#define STM32_FLASH_CR_PG (1 << 0) 110#define STM32_FLASH_CR_PER (1 << 1) 111#define STM32_FLASH_CR_STRT (1 << 6) 112#define STM32_FLASH_CR_LOCK (1 << 7) 113 114enum clock { 115 CLOCK_CORE, 116 CLOCK_AHB, 117 CLOCK_APB1, 118 CLOCK_APB2 119}; 120 121int configure_clocks(void); 122unsigned long clock_get(enum clock clck); 123 124#endif /* _MACH_STM32_H_ */ 125