LXR uboot/arch/blackfin/cpu/cpu.c

   1/*
   2 * U-Boot - cpu.c CPU specific functions
   3 *
   4 * Copyright (c) 2005-2008 Analog Devices Inc.
   5 *
   6 * (C) Copyright 2000-2004
   7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8 *
   9 * Licensed under the GPL-2 or later.
  10 */
  11
  12#include <common.h>
  13#include <command.h>
  14#include <serial.h>
  15#include <version.h>
  16#include <i2c.h>
  17
  18#include <asm/blackfin.h>
  19#include <asm/cplb.h>
  20#include <asm/clock.h>
  21#include <asm/mach-common/bits/core.h>
  22#include <asm/mach-common/bits/ebiu.h>
  23#include <asm/mach-common/bits/trace.h>
  24
  25#include "cpu.h"
  26#include "initcode.h"
  27#include "exports.h"
  28
  29ulong bfin_poweron_retx;
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
  33void bfin_core1_start(void)
  34{
  35#ifdef BF561_FAMILY
  36        /* Enable core 1 */
  37        bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
  38#else
  39        /* Enable core 1 */
  40        bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
  41        bfin_write32(RCU0_CRCTL, 0);
  42
  43        bfin_write32(RCU0_CRCTL, 0x2);
  44
  45        /* Check if core 1 starts */
  46        while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
  47                continue;
  48
  49        bfin_write32(RCU0_CRCTL, 0);
  50
  51        /* flag to notify cces core 1 application */
  52        bfin_write32(SDU0_MSG_SET, (1 << 19));
  53#endif
  54}
  55#endif
  56
  57__attribute__((always_inline))
  58static inline void serial_early_puts(const char *s)
  59{
  60#ifdef CONFIG_DEBUG_EARLY_SERIAL
  61        serial_puts("Early: ");
  62        serial_puts(s);
  63#endif
  64}
  65
  66static int global_board_data_init(void)
  67{
  68#ifndef CONFIG_SYS_GBL_DATA_ADDR
  69# define CONFIG_SYS_GBL_DATA_ADDR 0
  70#endif
  71#ifndef CONFIG_SYS_BD_INFO_ADDR
  72# define CONFIG_SYS_BD_INFO_ADDR 0
  73#endif
  74
  75        bd_t *bd;
  76
  77        if (CONFIG_SYS_GBL_DATA_ADDR) {
  78                gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
  79                memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
  80        } else {
  81                static gd_t _bfin_gd;
  82                gd = &_bfin_gd;
  83        }
  84        if (CONFIG_SYS_BD_INFO_ADDR) {
  85                bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
  86                memset(bd, 0, GENERATED_BD_INFO_SIZE);
  87        } else {
  88                static bd_t _bfin_bd;
  89                bd = &_bfin_bd;
  90        }
  91
  92        gd->bd = bd;
  93
  94        bd->bi_r_version = version_string;
  95        bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
  96        bd->bi_board_name = CONFIG_SYS_BOARD;
  97        bd->bi_vco = get_vco();
  98        bd->bi_cclk = get_cclk();
  99        bd->bi_sclk = get_sclk();
 100        bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 101        bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
 102
 103        gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
 104
 105        return 0;
 106}
 107
 108static void display_global_data(void)
 109{
 110        bd_t *bd;
 111
 112#ifndef CONFIG_DEBUG_EARLY_SERIAL
 113        return;
 114#endif
 115
 116        bd = gd->bd;
 117        printf(" gd: %p\n", gd);
 118        printf(" |-flags: %lx\n", gd->flags);
 119        printf(" |-board_type: %lx\n", gd->arch.board_type);
 120        printf(" |-baudrate: %u\n", gd->baudrate);
 121        printf(" |-have_console: %lx\n", gd->have_console);
 122        printf(" |-ram_size: %lx\n", gd->ram_size);
 123        printf(" |-env_addr: %lx\n", gd->env_addr);
 124        printf(" |-env_valid: %lx\n", gd->env_valid);
 125        printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
 126        printf(" \\-bd: %p\n", gd->bd);
 127        printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
 128        printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
 129        printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
 130        printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
 131        printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
 132        printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
 133}
 134
 135#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
 136#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
 137#if defined(__ADSPBF60x__)
 138#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
 139#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
 140#else
 141#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
 142#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
 143#endif
 144void init_cplbtables(void)
 145{
 146        uint32_t *ICPLB_ADDR, *ICPLB_DATA;
 147        uint32_t *DCPLB_ADDR, *DCPLB_DATA;
 148        uint32_t extern_memory;
 149        size_t i;
 150
 151        void icplb_add(uint32_t addr, uint32_t data)
 152        {
 153                bfin_write32(ICPLB_ADDR + i, addr);
 154                bfin_write32(ICPLB_DATA + i, data);
 155        }
 156        void dcplb_add(uint32_t addr, uint32_t data)
 157        {
 158                bfin_write32(DCPLB_ADDR + i, addr);
 159                bfin_write32(DCPLB_DATA + i, data);
 160        }
 161
 162        /* populate a few common entries ... we'll let
 163         * the memory map and cplb exception handler do
 164         * the rest of the work.
 165         */
 166        i = 0;
 167        ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
 168        ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
 169        DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
 170        DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
 171
 172        icplb_add(0xFFA00000, L1_IMEMORY);
 173        dcplb_add(0xFF800000, L1_DMEMORY);
 174        ++i;
 175#if defined(__ADSPBF60x__)
 176        icplb_add(0x0, 0x0);
 177        dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
 178                CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
 179        ++i;
 180#endif
 181
 182        if (CONFIG_MEM_SIZE) {
 183                uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
 184                uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN - 1;
 185                mbase &= CPLB_PAGE_MASK;
 186                mend &= CPLB_PAGE_MASK;
 187
 188                icplb_add(mbase, SDRAM_IKERNEL);
 189                dcplb_add(mbase, SDRAM_DKERNEL);
 190                ++i;
 191
 192                /*
 193                 * If the monitor crosses a 4 meg boundary, we'll need
 194                 * to lock two entries for it.  We assume it doesn't
 195                 * cross two 4 meg boundaries ...
 196                 */
 197                if (mbase != mend) {
 198                        icplb_add(mend, SDRAM_IKERNEL);
 199                        dcplb_add(mend, SDRAM_DKERNEL);
 200                        ++i;
 201                }
 202        }
 203
 204#ifndef __ADSPBF60x__
 205        icplb_add(0x20000000, SDRAM_INON_CHBL);
 206        dcplb_add(0x20000000, SDRAM_EBIU);
 207        ++i;
 208#endif
 209
 210        /* Add entries for the rest of external RAM up to the bootrom */
 211        extern_memory = 0;
 212
 213#ifdef CONFIG_DEBUG_NULL_PTR
 214        icplb_add(extern_memory,
 215                  (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
 216        dcplb_add(extern_memory,
 217                  (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
 218        ++i;
 219        icplb_add(extern_memory, SDRAM_IKERNEL);
 220        dcplb_add(extern_memory, SDRAM_DKERNEL);
 221        extern_memory += CPLB_PAGE_SIZE;
 222        ++i;
 223#endif
 224
 225        while (i < 16 && extern_memory <
 226                (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
 227                icplb_add(extern_memory, SDRAM_IGENERIC);
 228                dcplb_add(extern_memory, SDRAM_DGENERIC);
 229                extern_memory += CPLB_EX_PAGE_SIZE;
 230                ++i;
 231        }
 232        while (i < 16) {
 233                icplb_add(0, 0);
 234                dcplb_add(0, 0);
 235                ++i;
 236        }
 237}
 238
 239int print_cpuinfo(void)
 240{
 241        char buf[32];
 242
 243        printf("CPU:   ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
 244               gd->bd->bi_cpu,
 245               bfin_revid(),
 246               get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
 247
 248        printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
 249        printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
 250#if defined(__ADSPBF60x__)
 251        printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
 252        printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
 253        printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
 254#else
 255        printf("System: %s MHz\n", strmhz(buf, get_sclk()));
 256#endif
 257
 258        return 0;
 259}
 260
 261int exception_init(void)
 262{
 263        bfin_write_EVT3(trap);
 264        return 0;
 265}
 266
 267int irq_init(void)
 268{
 269#ifdef SIC_IMASK0
 270        bfin_write_SIC_IMASK0(0);
 271        bfin_write_SIC_IMASK1(0);
 272# ifdef SIC_IMASK2
 273        bfin_write_SIC_IMASK2(0);
 274# endif
 275#elif defined(SICA_IMASK0)
 276        bfin_write_SICA_IMASK0(0);
 277        bfin_write_SICA_IMASK1(0);
 278#elif defined(SIC_IMASK)
 279        bfin_write_SIC_IMASK(0);
 280#endif
 281        /* Set up a dummy NMI handler if needed.  */
 282        if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
 283                bfin_write_EVT2(evt_nmi);       /* NMI */
 284        bfin_write_EVT5(evt_default);   /* hardware error */
 285        bfin_write_EVT6(evt_default);   /* core timer */
 286        bfin_write_EVT7(evt_default);
 287        bfin_write_EVT8(evt_default);
 288        bfin_write_EVT9(evt_default);
 289        bfin_write_EVT10(evt_default);
 290        bfin_write_EVT11(evt_default);
 291        bfin_write_EVT12(evt_default);
 292        bfin_write_EVT13(evt_default);
 293        bfin_write_EVT14(evt_default);
 294        bfin_write_EVT15(evt_default);
 295        bfin_write_ILAT(0);
 296        CSYNC();
 297        /* enable hardware error irq */
 298        irq_flags = 0x3f;
 299        local_irq_enable();
 300        return 0;
 301}
 302
 303__attribute__ ((__noreturn__))
 304void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 305{
 306#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
 307        /* Build a NOP slide over the LDR jump block.  Whee! */
 308        char nops[0xC];
 309        serial_early_puts("NOP Slide\n");
 310        memset(nops, 0x00, sizeof(nops));
 311        memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
 312#endif
 313
 314        if (!loaded_from_ldr) {
 315                /* Relocate sections into L1 if the LDR didn't do it -- don't
 316                 * check length because the linker script does the size
 317                 * checking at build time.
 318                 */
 319                serial_early_puts("L1 Relocate\n");
 320                extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
 321                memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
 322                extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
 323                memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
 324        }
 325
 326        /*
 327         * Make sure our async settings are committed.  Some bootroms
 328         * (like the BF537) will reset some registers on us after it
 329         * has finished loading the LDR.  Or if we're booting over
 330         * JTAG, the initcode never got a chance to run.  Or if we
 331         * aren't booting from parallel flash, the initcode skipped
 332         * this step completely.
 333         */
 334        program_async_controller(NULL);
 335
 336        /* Save RETX so we can pass it while booting Linux */
 337        bfin_poweron_retx = bootflag;
 338
 339#ifdef CONFIG_DEBUG_DUMP
 340        /* Turn on hardware trace buffer */
 341        bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
 342#endif
 343
 344#ifndef CONFIG_PANIC_HANG
 345        /* Reset upon a double exception rather than just hanging.
 346         * Do not do bfin_read on SWRST as that will reset status bits.
 347         */
 348# ifdef SWRST
 349        bfin_write_SWRST(DOUBLE_FAULT);
 350# endif
 351#endif
 352
 353#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
 354        bfin_core1_start();
 355#endif
 356
 357        serial_early_puts("Init global data\n");
 358        global_board_data_init();
 359
 360        board_init_f(0);
 361
 362        /* should not be reached */
 363        while (1);
 364}
 365
 366int arch_cpu_init(void)
 367{
 368        serial_early_puts("Init CPLB tables\n");
 369        init_cplbtables();
 370
 371        serial_early_puts("Exceptions setup\n");
 372        exception_init();
 373
 374#ifndef CONFIG_ICACHE_OFF
 375        serial_early_puts("Turn on ICACHE\n");
 376        icache_enable();
 377#endif
 378#ifndef CONFIG_DCACHE_OFF
 379        serial_early_puts("Turn on DCACHE\n");
 380        dcache_enable();
 381#endif
 382
 383#ifdef DEBUG
 384        if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
 385                hang();
 386#endif
 387
 388        /* Initialize */
 389        serial_early_puts("IRQ init\n");
 390        irq_init();
 391
 392        return 0;
 393}
 394
 395int arch_misc_init(void)
 396{
 397#if defined(CONFIG_SYS_I2C)
 398        i2c_reloc_fixup();
 399#endif
 400
 401        display_global_data();
 402
 403        if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
 404                puts("\nLog buffer from operating system:\n");
 405                bfin_os_log_dump();
 406                puts("\n");
 407        }
 408
 409        return 0;
 410}
 411
 412int interrupt_init(void)
 413{
 414        return 0;
 415}
 416