1/* 2 * (C) Copyright 2002 3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __ASM_PROCESSOR_H_ 9#define __ASM_PROCESSOR_H_ 1 10 11#define X86_GDT_ENTRY_SIZE 8 12 13#define X86_GDT_ENTRY_NULL 0 14#define X86_GDT_ENTRY_UNUSED 1 15#define X86_GDT_ENTRY_32BIT_CS 2 16#define X86_GDT_ENTRY_32BIT_DS 3 17#define X86_GDT_ENTRY_32BIT_FS 4 18#define X86_GDT_ENTRY_16BIT_CS 5 19#define X86_GDT_ENTRY_16BIT_DS 6 20#define X86_GDT_ENTRY_16BIT_FLAT_CS 7 21#define X86_GDT_ENTRY_16BIT_FLAT_DS 8 22#define X86_GDT_NUM_ENTRIES 9 23 24#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) 25 26/* Length of the public header on Intel microcode blobs */ 27#define UCODE_HEADER_LEN 0x30 28 29#ifndef __ASSEMBLY__ 30 31/* 32 * This register is documented in (for example) the Intel Atom Processor E3800 33 * Product Family Datasheet in "PCU - Power Management Controller (PMC)". 34 * 35 * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. 36 * 37 * The naming follows Intel's naming. 38 */ 39#define IO_PORT_RESET 0xcf9 40 41enum { 42 SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ 43 RST_CPU = 1 << 2, /* initiate reset */ 44 FULL_RST = 1 << 3, /* full power cycle */ 45}; 46 47/** 48 * x86_full_reset() - reset everything: perform a full power cycle 49 */ 50void x86_full_reset(void); 51 52static inline __attribute__((always_inline)) void cpu_hlt(void) 53{ 54 asm("hlt"); 55} 56 57static inline ulong cpu_get_sp(void) 58{ 59 ulong result; 60 61 asm volatile( 62 "mov %%esp, %%eax" 63 : "=a" (result)); 64 return result; 65} 66 67#endif /* __ASSEMBLY__ */ 68 69#endif 70