LXR uboot/board/davinci/da8xxevm/omapl138

   1/*
   2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3 *
   4 * Based on da850evm.c. Original Copyrights follow:
   5 *
   6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
   7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#include <common.h>
  13#include <i2c.h>
  14#include <net.h>
  15#include <netdev.h>
  16#include <spi.h>
  17#include <spi_flash.h>
  18#include <asm/arch/hardware.h>
  19#include <asm/ti-common/davinci_nand.h>
  20#include <asm/io.h>
  21#include <linux/errno.h>
  22#include <asm/arch/davinci_misc.h>
  23#ifdef CONFIG_DAVINCI_MMC
  24#include <mmc.h>
  25#include <asm/arch/sdmmc_defs.h>
  26#endif
  27
  28DECLARE_GLOBAL_DATA_PTR;
  29
  30#define pinmux(x)       (&davinci_syscfg_regs->pinmux[x])
  31
  32#ifdef CONFIG_DAVINCI_MMC
  33/* MMC0 pin muxer settings */
  34const struct pinmux_config mmc0_pins[] = {
  35        /* GP0[11] is required for SD to work on Rev 3 EVMs */
  36        { pinmux(0),  8, 4 },   /* GP0[11] */
  37        { pinmux(10), 2, 0 },   /* MMCSD0_CLK */
  38        { pinmux(10), 2, 1 },   /* MMCSD0_CMD */
  39        { pinmux(10), 2, 2 },   /* MMCSD0_DAT_0 */
  40        { pinmux(10), 2, 3 },   /* MMCSD0_DAT_1 */
  41        { pinmux(10), 2, 4 },   /* MMCSD0_DAT_2 */
  42        { pinmux(10), 2, 5 },   /* MMCSD0_DAT_3 */
  43        /* LCDK supports only 4-bit mode, remaining pins are not configured */
  44};
  45#endif
  46
  47/* UART pin muxer settings */
  48static const struct pinmux_config uart_pins[] = {
  49        { pinmux(0), 4, 6 },
  50        { pinmux(0), 4, 7 },
  51        { pinmux(4), 2, 4 },
  52        { pinmux(4), 2, 5 }
  53};
  54
  55#ifdef CONFIG_DRIVER_TI_EMAC
  56static const struct pinmux_config emac_pins[] = {
  57        { pinmux(2), 8, 1 },
  58        { pinmux(2), 8, 2 },
  59        { pinmux(2), 8, 3 },
  60        { pinmux(2), 8, 4 },
  61        { pinmux(2), 8, 5 },
  62        { pinmux(2), 8, 6 },
  63        { pinmux(2), 8, 7 },
  64        { pinmux(3), 8, 0 },
  65        { pinmux(3), 8, 1 },
  66        { pinmux(3), 8, 2 },
  67        { pinmux(3), 8, 3 },
  68        { pinmux(3), 8, 4 },
  69        { pinmux(3), 8, 5 },
  70        { pinmux(3), 8, 6 },
  71        { pinmux(3), 8, 7 },
  72        { pinmux(4), 8, 0 },
  73        { pinmux(4), 8, 1 }
  74};
  75#endif /* CONFIG_DRIVER_TI_EMAC */
  76
  77/* I2C pin muxer settings */
  78static const struct pinmux_config i2c_pins[] = {
  79        { pinmux(4), 2, 2 },
  80        { pinmux(4), 2, 3 }
  81};
  82
  83#ifdef CONFIG_NAND_DAVINCI
  84const struct pinmux_config nand_pins[] = {
  85        { pinmux(7), 1, 1 },
  86        { pinmux(7), 1, 2 },
  87        { pinmux(7), 1, 4 },
  88        { pinmux(7), 1, 5 },
  89        { pinmux(8), 1, 0 },
  90        { pinmux(8), 1, 1 },
  91        { pinmux(8), 1, 2 },
  92        { pinmux(8), 1, 3 },
  93        { pinmux(8), 1, 4 },
  94        { pinmux(8), 1, 5 },
  95        { pinmux(8), 1, 6 },
  96        { pinmux(8), 1, 7 },
  97        { pinmux(9), 1, 0 },
  98        { pinmux(9), 1, 1 },
  99        { pinmux(9), 1, 2 },
 100        { pinmux(9), 1, 3 },
 101        { pinmux(9), 1, 4 },
 102        { pinmux(9), 1, 5 },
 103        { pinmux(9), 1, 6 },
 104        { pinmux(9), 1, 7 },
 105        { pinmux(12), 1, 5 },
 106        { pinmux(12), 1, 6 }
 107};
 108
 109#endif
 110
 111#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 112#define HAS_RMII 1
 113#else
 114#define HAS_RMII 0
 115#endif
 116
 117const struct pinmux_resource pinmuxes[] = {
 118        PINMUX_ITEM(uart_pins),
 119        PINMUX_ITEM(i2c_pins),
 120#ifdef CONFIG_NAND_DAVINCI
 121        PINMUX_ITEM(nand_pins),
 122#endif
 123};
 124
 125const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
 126
 127const struct lpsc_resource lpsc[] = {
 128        { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
 129        { DAVINCI_LPSC_SPI1 },  /* Serial Flash */
 130        { DAVINCI_LPSC_EMAC },  /* image download */
 131        { DAVINCI_LPSC_UART2 }, /* console */
 132        { DAVINCI_LPSC_GPIO },
 133#ifdef CONFIG_DAVINCI_MMC
 134        { DAVINCI_LPSC_MMC_SD },
 135#endif
 136};
 137
 138const int lpsc_size = ARRAY_SIZE(lpsc);
 139
 140#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
 141#define CONFIG_DA850_EVM_MAX_CPU_CLK    456000000
 142#endif
 143
 144/*
 145 * get_board_rev() - setup to pass kernel board revision information
 146 * Returns:
 147 * bit[0-3]     Maximum cpu clock rate supported by onboard SoC
 148 *              0000b - 300 MHz
 149 *              0001b - 372 MHz
 150 *              0010b - 408 MHz
 151 *              0011b - 456 MHz
 152 */
 153u32 get_board_rev(void)
 154{
 155        return 0;
 156}
 157
 158int board_early_init_f(void)
 159{
 160        /*
 161         * Power on required peripherals
 162         * ARM does not have access by default to PSC0 and PSC1
 163         * assuming here that the DSP bootloader has set the IOPU
 164         * such that PSC access is available to ARM
 165         */
 166        if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
 167                return 1;
 168
 169        return 0;
 170}
 171
 172int board_init(void)
 173{
 174#ifndef CONFIG_USE_IRQ
 175        irq_init();
 176#endif
 177
 178        /* arch number of the board */
 179        gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
 180
 181        /* address of boot parameters */
 182        gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
 183
 184
 185        /* setup the SUSPSRC for ARM to control emulation suspend */
 186        writel(readl(&davinci_syscfg_regs->suspsrc) &
 187               ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
 188                 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
 189                 DAVINCI_SYSCFG_SUSPSRC_UART2),
 190               &davinci_syscfg_regs->suspsrc);
 191
 192        /* configure pinmux settings */
 193        if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
 194                return 1;
 195
 196#ifdef CONFIG_NAND_DAVINCI
 197        /*
 198         * NAND CS setup - cycle counts based on da850evm NAND timings in the
 199         * Linux kernel @ 25MHz EMIFA
 200         */
 201        writel((DAVINCI_ABCR_WSETUP(15) |
 202                DAVINCI_ABCR_WSTROBE(63) |
 203                DAVINCI_ABCR_WHOLD(7) |
 204                DAVINCI_ABCR_RSETUP(15) |
 205                DAVINCI_ABCR_RSTROBE(63) |
 206                DAVINCI_ABCR_RHOLD(7) |
 207                DAVINCI_ABCR_TA(3) |
 208                DAVINCI_ABCR_ASIZE_16BIT),
 209               &davinci_emif_regs->ab2cr); /* CS3 */
 210#endif
 211
 212
 213#ifdef CONFIG_DAVINCI_MMC
 214        if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
 215                return 1;
 216#endif
 217
 218#ifdef CONFIG_DRIVER_TI_EMAC
 219        if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
 220                return 1;
 221        davinci_emac_mii_mode_sel(HAS_RMII);
 222#endif /* CONFIG_DRIVER_TI_EMAC */
 223
 224        /* enable the console UART */
 225        writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 226                DAVINCI_UART_PWREMU_MGMT_UTRST),
 227               &davinci_uart2_ctrl_regs->pwremu_mgmt);
 228
 229        return 0;
 230}
 231
 232#ifdef CONFIG_DRIVER_TI_EMAC
 233
 234/*
 235 * Initializes on-board ethernet controllers.
 236 */
 237int board_eth_init(bd_t *bis)
 238{
 239        if (!davinci_emac_initialize()) {
 240                printf("Error: Ethernet init failed!\n");
 241                return -1;
 242        }
 243
 244        return 0;
 245}
 246
 247#endif /* CONFIG_DRIVER_TI_EMAC */
 248
 249#define CFG_MAC_ADDR_SPI_BUS    0
 250#define CFG_MAC_ADDR_SPI_CS     0
 251#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
 252#define CFG_MAC_ADDR_SPI_MODE   SPI_MODE_3
 253
 254#define CFG_MAC_ADDR_OFFSET     (flash->size - SZ_64K)
 255
 256static int  get_mac_addr(u8 *addr)
 257{
 258        /* Need to find a way to get MAC ADDRESS */
 259        return 0;
 260}
 261
 262void dsp_lpsc_on(unsigned domain, unsigned int id)
 263{
 264        dv_reg_p mdstat, mdctl, ptstat, ptcmd;
 265        struct davinci_psc_regs *psc_regs;
 266
 267        psc_regs = davinci_psc0_regs;
 268        mdstat = &psc_regs->psc0.mdstat[id];
 269        mdctl = &psc_regs->psc0.mdctl[id];
 270        ptstat = &psc_regs->ptstat;
 271        ptcmd = &psc_regs->ptcmd;
 272
 273        while (*ptstat & (0x1 << domain))
 274                ;
 275
 276        if ((*mdstat & 0x1f) == 0x03)
 277                return;                 /* Already on and enabled */
 278
 279        *mdctl |= 0x03;
 280
 281        *ptcmd = 0x1 << domain;
 282
 283        while (*ptstat & (0x1 << domain))
 284                ;
 285        while ((*mdstat & 0x1f) != 0x03)
 286                ;               /* Probably an overkill... */
 287}
 288
 289static void dspwake(void)
 290{
 291        unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
 292
 293        /* if the device is ARM only, return */
 294        if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
 295                return;
 296
 297        if (!strcmp(getenv("dspwake"), "no"))
 298                return;
 299
 300        *resetvect++ = 0x1E000; /* DSP Idle */
 301        /* clear out the next 10 words as NOP */
 302        memset(resetvect, 0, sizeof(unsigned) * 10);
 303
 304        /* setup the DSP reset vector */
 305        REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
 306
 307        dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
 308        REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
 309}
 310
 311#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 312/**
 313 * rmii_hw_init
 314 *
 315 */
 316int rmii_hw_init(void)
 317{
 318        return 0;
 319}
 320#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
 321
 322int misc_init_r(void)
 323{
 324        uint8_t tmp[20], addr[10];
 325
 326
 327        if (getenv("ethaddr") == NULL) {
 328                /* Read Ethernet MAC address from EEPROM */
 329                if (dvevm_read_mac_address(addr)) {
 330                        /* Set Ethernet MAC address from EEPROM */
 331                        davinci_sync_env_enetaddr(addr);
 332                } else {
 333                        get_mac_addr(addr);
 334                }
 335
 336                if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
 337                        sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
 338                                addr[0], addr[1], addr[2], addr[3], addr[4],
 339                                addr[5]);
 340
 341                        setenv("ethaddr", (char *)tmp);
 342                } else {
 343                        printf("Invalid MAC address read.\n");
 344                }
 345        }
 346
 347#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 348        /* Select RMII fucntion through the expander */
 349        if (rmii_hw_init())
 350                printf("RMII hardware init failed!!!\n");
 351#endif
 352
 353        dspwake();
 354
 355        return 0;
 356}
 357
 358#ifdef CONFIG_DAVINCI_MMC
 359static struct davinci_mmc mmc_sd0 = {
 360        .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
 361        .host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
 362        .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
 363        .version = MMC_CTLR_VERSION_2,
 364};
 365
 366int board_mmc_init(bd_t *bis)
 367{
 368        mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
 369
 370        /* Add slot-0 to mmc subsystem */
 371        return davinci_mmc_init(bis, &mmc_sd0);
 372}
 373#endif
 374