LXR uboot/board/freescale/t102xqds/t102xqds.c

   1/*
   2 * Copyright 2014 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <command.h>
   9#include <i2c.h>
  10#include <netdev.h>
  11#include <linux/compiler.h>
  12#include <asm/mmu.h>
  13#include <asm/processor.h>
  14#include <asm/cache.h>
  15#include <asm/immap_85xx.h>
  16#include <asm/fsl_law.h>
  17#include <asm/fsl_serdes.h>
  18#include <asm/fsl_liodn.h>
  19#include <fm_eth.h>
  20#include <hwconfig.h>
  21#include "../common/qixis.h"
  22#include "t102xqds.h"
  23#include "t102xqds_qixis.h"
  24#include "../common/sleep.h"
  25
  26DECLARE_GLOBAL_DATA_PTR;
  27
  28int checkboard(void)
  29{
  30        char buf[64];
  31        struct cpu_type *cpu = gd->arch.cpu;
  32        static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  33        int clock;
  34        u8 sw = QIXIS_READ(arch);
  35
  36        printf("Board: %sQDS, ", cpu->name);
  37        printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  38        printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  39
  40#ifdef CONFIG_SDCARD
  41        puts("SD/MMC\n");
  42#elif CONFIG_SPIFLASH
  43        puts("SPI\n");
  44#else
  45        sw = QIXIS_READ(brdcfg[0]);
  46        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  47
  48        if (sw < 0x8)
  49                printf("vBank: %d\n", sw);
  50        else if (sw == 0x8)
  51                puts("PromJet\n");
  52        else if (sw == 0x9)
  53                puts("NAND\n");
  54        else if (sw == 0x15)
  55                printf("IFC Card\n");
  56        else
  57                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  58#endif
  59
  60        printf("FPGA: v%d (%s), build %d",
  61               (int)QIXIS_READ(scver), qixis_read_tag(buf),
  62               (int)qixis_read_minor());
  63        /* the timestamp string contains "\n" at the end */
  64        printf(" on %s", qixis_read_time(buf));
  65
  66        puts("SERDES Reference: ");
  67        sw = QIXIS_READ(brdcfg[2]);
  68        clock = (sw >> 6) & 3;
  69        printf("Clock1=%sMHz ", freq[clock]);
  70        clock = (sw >> 4) & 3;
  71        printf("Clock2=%sMHz\n", freq[clock]);
  72
  73        return 0;
  74}
  75
  76int select_i2c_ch_pca9547(u8 ch)
  77{
  78        int ret;
  79
  80        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81        if (ret) {
  82                puts("PCA: failed to select proper channel\n");
  83                return ret;
  84        }
  85
  86        return 0;
  87}
  88
  89static int board_mux_lane_to_slot(void)
  90{
  91        ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  92        u32 srds_prtcl_s1;
  93        u8 brdcfg9;
  94
  95        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  96                                FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  97        srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  98
  99
 100        brdcfg9 = QIXIS_READ(brdcfg[9]);
 101        QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
 102
 103        switch (srds_prtcl_s1) {
 104        case 0:
 105                /* SerDes1 is not enabled */
 106                break;
 107        case 0xd5:
 108        case 0x5b:
 109        case 0x6b:
 110        case 0x77:
 111        case 0x6f:
 112        case 0x7f:
 113                QIXIS_WRITE(brdcfg[12], 0x8c);
 114                break;
 115        case 0x40:
 116                QIXIS_WRITE(brdcfg[12], 0xfc);
 117                break;
 118        case 0xd6:
 119        case 0x5a:
 120        case 0x6a:
 121        case 0x56:
 122                QIXIS_WRITE(brdcfg[12], 0x88);
 123                break;
 124        case 0x47:
 125                QIXIS_WRITE(brdcfg[12], 0xcc);
 126                break;
 127        case 0x46:
 128                QIXIS_WRITE(brdcfg[12], 0xc8);
 129                break;
 130        case 0x95:
 131        case 0x99:
 132                brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
 133                QIXIS_WRITE(brdcfg[9], brdcfg9);
 134                QIXIS_WRITE(brdcfg[12], 0x8c);
 135                break;
 136        case 0x116:
 137                QIXIS_WRITE(brdcfg[12], 0x00);
 138                break;
 139        case 0x115:
 140        case 0x119:
 141        case 0x129:
 142        case 0x12b:
 143                /* Aurora, PCIe, SGMII, SATA */
 144                QIXIS_WRITE(brdcfg[12], 0x04);
 145                break;
 146        default:
 147                printf("WARNING: unsupported for SerDes Protocol %d\n",
 148                       srds_prtcl_s1);
 149                return -1;
 150        }
 151
 152        return 0;
 153}
 154
 155#ifdef CONFIG_ARCH_T1024
 156static void board_mux_setup(void)
 157{
 158        u8 brdcfg15;
 159
 160        brdcfg15 = QIXIS_READ(brdcfg[15]);
 161        brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
 162
 163        if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 164                /* Route QE_TDM multiplexed signals to TDM Riser slot */
 165                QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
 166                QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
 167                QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 168                            ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
 169        } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
 170                /* to UCC (ProfiBus) interface */
 171                QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
 172        } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
 173                /* to DVI (HDMI) encoder */
 174                QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
 175        } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
 176                /* to DFP (LCD) encoder */
 177                QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
 178                            BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
 179        }
 180
 181        if (hwconfig_arg_cmp("adaptor", "sdxc"))
 182                /* Route SPI_CS multiplexed signals to SD slot */
 183                QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 184                            ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
 185}
 186#endif
 187
 188void board_retimer_ds125df111_init(void)
 189{
 190        u8 reg;
 191
 192        /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
 193        reg = I2C_MUX_CH7;
 194        i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
 195        reg = I2C_MUX_CH5;
 196        i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 197
 198        /* Access to Control/Shared register */
 199        reg = 0x0;
 200        i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 201
 202        /* Read device revision and ID */
 203        i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 204        debug("Retimer version id = 0x%x\n", reg);
 205
 206        /* Enable Broadcast */
 207        reg = 0x0c;
 208        i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 209
 210        /* Reset Channel Registers */
 211        i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 212        reg |= 0x4;
 213        i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 214
 215        /* Enable override divider select and Enable Override Output Mux */
 216        i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 217        reg |= 0x24;
 218        i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 219
 220        /* Select VCO Divider to full rate (000) */
 221        i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 222        reg &= 0x8f;
 223        i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 224
 225        /* Select active PFD MUX input as re-timed data (001) */
 226        i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 227        reg &= 0x3f;
 228        reg |= 0x20;
 229        i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 230
 231        /* Set data rate as 10.3125 Gbps */
 232        reg = 0x0;
 233        i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 234        reg = 0xb2;
 235        i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 236        reg = 0x90;
 237        i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 238        reg = 0xb3;
 239        i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 240        reg = 0xcd;
 241        i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 242}
 243
 244int board_early_init_f(void)
 245{
 246#if defined(CONFIG_DEEP_SLEEP)
 247        if (is_warm_boot())
 248                fsl_dp_disable_console();
 249#endif
 250
 251        return 0;
 252}
 253
 254int board_early_init_r(void)
 255{
 256#ifdef CONFIG_SYS_FLASH_BASE
 257        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 258        int flash_esel = find_tlb_idx((void *)flashbase, 1);
 259
 260        /*
 261         * Remap Boot flash + PROMJET region to caching-inhibited
 262         * so that flash can be erased properly.
 263         */
 264
 265        /* Flush d-cache and invalidate i-cache of any FLASH data */
 266        flush_dcache();
 267        invalidate_icache();
 268
 269        if (flash_esel == -1) {
 270                /* very unlikely unless something is messed up */
 271                puts("Error: Could not find TLB for FLASH BASE\n");
 272                flash_esel = 2; /* give our best effort to continue */
 273        } else {
 274                /* invalidate existing TLB entry for flash + promjet */
 275                disable_tlb(flash_esel);
 276        }
 277
 278        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 279                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 280                0, flash_esel, BOOKE_PAGESZ_256M, 1);
 281#endif
 282        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 283        board_mux_lane_to_slot();
 284        board_retimer_ds125df111_init();
 285
 286        /* Increase IO drive strength to address FCS error on RGMII */
 287        out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
 288
 289        return 0;
 290}
 291
 292unsigned long get_board_sys_clk(void)
 293{
 294        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 295
 296        switch (sysclk_conf & 0x0F) {
 297        case QIXIS_SYSCLK_64:
 298                return 64000000;
 299        case QIXIS_SYSCLK_83:
 300                return 83333333;
 301        case QIXIS_SYSCLK_100:
 302                return 100000000;
 303        case QIXIS_SYSCLK_125:
 304                return 125000000;
 305        case QIXIS_SYSCLK_133:
 306                return 133333333;
 307        case QIXIS_SYSCLK_150:
 308                return 150000000;
 309        case QIXIS_SYSCLK_160:
 310                return 160000000;
 311        case QIXIS_SYSCLK_166:
 312                return 166666666;
 313        }
 314        return 66666666;
 315}
 316
 317unsigned long get_board_ddr_clk(void)
 318{
 319        u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 320
 321        switch ((ddrclk_conf & 0x30) >> 4) {
 322        case QIXIS_DDRCLK_100:
 323                return 100000000;
 324        case QIXIS_DDRCLK_125:
 325                return 125000000;
 326        case QIXIS_DDRCLK_133:
 327                return 133333333;
 328        }
 329        return 66666666;
 330}
 331
 332#define NUM_SRDS_PLL    2
 333int misc_init_r(void)
 334{
 335#ifdef CONFIG_ARCH_T1024
 336        board_mux_setup();
 337#endif
 338        return 0;
 339}
 340
 341void fdt_fixup_spi_mux(void *blob)
 342{
 343        int nodeoff = 0;
 344
 345        if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 346                while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 347                        "eon,en25s64")) >= 0) {
 348                        fdt_del_node(blob, nodeoff);
 349                }
 350        } else {
 351                /* remove tdm node */
 352                while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 353                        "maxim,ds26522")) >= 0) {
 354                        fdt_del_node(blob, nodeoff);
 355                }
 356        }
 357}
 358
 359int ft_board_setup(void *blob, bd_t *bd)
 360{
 361        phys_addr_t base;
 362        phys_size_t size;
 363
 364        ft_cpu_setup(blob, bd);
 365
 366        base = getenv_bootm_low();
 367        size = getenv_bootm_size();
 368
 369        fdt_fixup_memory(blob, (u64)base, (u64)size);
 370
 371#ifdef CONFIG_PCI
 372        pci_of_setup(blob, bd);
 373#endif
 374
 375        fdt_fixup_liodn(blob);
 376
 377#ifdef CONFIG_HAS_FSL_DR_USB
 378        fsl_fdt_fixup_dr_usb(blob, bd);
 379#endif
 380
 381#ifdef CONFIG_SYS_DPAA_FMAN
 382        fdt_fixup_fman_ethernet(blob);
 383        fdt_fixup_board_enet(blob);
 384#endif
 385        fdt_fixup_spi_mux(blob);
 386
 387        return 0;
 388}
 389
 390void qixis_dump_switch(void)
 391{
 392        int i, nr_of_cfgsw;
 393
 394        QIXIS_WRITE(cms[0], 0x00);
 395        nr_of_cfgsw = QIXIS_READ(cms[1]);
 396
 397        puts("DIP switch settings dump:\n");
 398        for (i = 1; i <= nr_of_cfgsw; i++) {
 399                QIXIS_WRITE(cms[0], i);
 400                printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 401        }
 402}
 403