LXR uboot/board/xilinx/zynq/board.c

   1/*
   2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <fdtdec.h>
   9#include <fpga.h>
  10#include <mmc.h>
  11#include <zynqpl.h>
  12#include <asm/arch/hardware.h>
  13#include <asm/arch/sys_proto.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  18    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  19static xilinx_desc fpga;
  20
  21/* It can be done differently */
  22static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
  23static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  24static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
  25static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
  26static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  27static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  28static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  29static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  30static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  31static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  32#endif
  33
  34int board_init(void)
  35{
  36#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
  37        unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL;
  38#endif
  39#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  40    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  41        u32 idcode;
  42
  43        idcode = zynq_slcr_get_idcode();
  44
  45        switch (idcode) {
  46        case XILINX_ZYNQ_7007S:
  47                fpga = fpga007s;
  48                break;
  49        case XILINX_ZYNQ_7010:
  50                fpga = fpga010;
  51                break;
  52        case XILINX_ZYNQ_7012S:
  53                fpga = fpga012s;
  54                break;
  55        case XILINX_ZYNQ_7014S:
  56                fpga = fpga014s;
  57                break;
  58        case XILINX_ZYNQ_7015:
  59                fpga = fpga015;
  60                break;
  61        case XILINX_ZYNQ_7020:
  62                fpga = fpga020;
  63                break;
  64        case XILINX_ZYNQ_7030:
  65                fpga = fpga030;
  66                break;
  67        case XILINX_ZYNQ_7035:
  68                fpga = fpga035;
  69                break;
  70        case XILINX_ZYNQ_7045:
  71                fpga = fpga045;
  72                break;
  73        case XILINX_ZYNQ_7100:
  74                fpga = fpga100;
  75                break;
  76        }
  77#endif
  78
  79#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  80    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  81        fpga_init();
  82        fpga_add(fpga_xilinx, &fpga);
  83#endif
  84#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
  85        if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1))
  86                puts("I2C:EEPROM selection failed\n");
  87#endif
  88        return 0;
  89}
  90
  91int board_late_init(void)
  92{
  93        switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  94        case ZYNQ_BM_QSPI:
  95                setenv("modeboot", "qspiboot");
  96                break;
  97        case ZYNQ_BM_NAND:
  98                setenv("modeboot", "nandboot");
  99                break;
 100        case ZYNQ_BM_NOR:
 101                setenv("modeboot", "norboot");
 102                break;
 103        case ZYNQ_BM_SD:
 104                setenv("modeboot", "sdboot");
 105                break;
 106        case ZYNQ_BM_JTAG:
 107                setenv("modeboot", "jtagboot");
 108                break;
 109        default:
 110                setenv("modeboot", "");
 111                break;
 112        }
 113
 114        return 0;
 115}
 116
 117#ifdef CONFIG_DISPLAY_BOARDINFO
 118int checkboard(void)
 119{
 120        puts("Board: Xilinx Zynq\n");
 121        return 0;
 122}
 123#endif
 124
 125int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 126{
 127#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 128    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
 129        if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 130                        CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 131                        ethaddr, 6))
 132                printf("I2C EEPROM MAC address read failed\n");
 133#endif
 134
 135        return 0;
 136}
 137
 138#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 139void dram_init_banksize(void)
 140{
 141        fdtdec_setup_memory_banksize();
 142}
 143
 144int dram_init(void)
 145{
 146        if (fdtdec_setup_memory_size() != 0)
 147                return -EINVAL;
 148
 149        zynq_ddrc_init();
 150
 151        return 0;
 152}
 153#else
 154int dram_init(void)
 155{
 156        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 157
 158        zynq_ddrc_init();
 159
 160        return 0;
 161}
 162#endif
 163