1/* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7#ifndef _DDR3_TRAINING_IP_STATIC_H_ 8#define _DDR3_TRAINING_IP_STATIC_H_ 9 10#include "ddr3_training_ip_def.h" 11#include "ddr3_training_ip.h" 12 13struct trip_delay_element { 14 u32 dqs_delay; /* DQS delay (m_sec) */ 15 u32 ck_delay; /* CK Delay (m_sec) */ 16}; 17 18struct hws_tip_static_config_info { 19 u32 silicon_delay; 20 struct trip_delay_element *package_trace_arr; 21 struct trip_delay_element *board_trace_arr; 22}; 23 24int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq); 25int ddr3_tip_init_static_config_db( 26 u32 dev_num, struct hws_tip_static_config_info *static_config_info); 27int ddr3_tip_init_specific_reg_config(u32 dev_num, 28 struct reg_data *reg_config_arr); 29int ddr3_tip_static_phy_init_controller(u32 dev_num); 30 31#endif /* _DDR3_TRAINING_IP_STATIC_H_ */ 32