LXR uboot/drivers/i2c/zynq

   1/*
   2 * Driver for the Zynq-7000 PS I2C controller
   3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4 *
   5 * Author: Joe Hershberger <joe.hershberger@ni.com>
   6 * Copyright (c) 2012 Joe Hershberger.
   7 *
   8 * Copyright (c) 2012-2013 Xilinx, Michal Simek
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 *
  12 * NOTE: This driver should be converted to driver model before June 2017.
  13 * Please see doc/driver-model/i2c-howto.txt for instructions.
  14 */
  15
  16#include <common.h>
  17#include <asm/io.h>
  18#include <i2c.h>
  19#include <linux/errno.h>
  20#include <asm/arch/hardware.h>
  21
  22/* i2c register set */
  23struct zynq_i2c_registers {
  24        u32 control;
  25        u32 status;
  26        u32 address;
  27        u32 data;
  28        u32 interrupt_status;
  29        u32 transfer_size;
  30        u32 slave_mon_pause;
  31        u32 time_out;
  32        u32 interrupt_mask;
  33        u32 interrupt_enable;
  34        u32 interrupt_disable;
  35};
  36
  37/* Control register fields */
  38#define ZYNQ_I2C_CONTROL_RW             0x00000001
  39#define ZYNQ_I2C_CONTROL_MS             0x00000002
  40#define ZYNQ_I2C_CONTROL_NEA            0x00000004
  41#define ZYNQ_I2C_CONTROL_ACKEN          0x00000008
  42#define ZYNQ_I2C_CONTROL_HOLD           0x00000010
  43#define ZYNQ_I2C_CONTROL_SLVMON         0x00000020
  44#define ZYNQ_I2C_CONTROL_CLR_FIFO       0x00000040
  45#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT    8
  46#define ZYNQ_I2C_CONTROL_DIV_B_MASK     0x00003F00
  47#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT    14
  48#define ZYNQ_I2C_CONTROL_DIV_A_MASK     0x0000C000
  49
  50/* Status register values */
  51#define ZYNQ_I2C_STATUS_RXDV    0x00000020
  52#define ZYNQ_I2C_STATUS_TXDV    0x00000040
  53#define ZYNQ_I2C_STATUS_RXOVF   0x00000080
  54#define ZYNQ_I2C_STATUS_BA      0x00000100
  55
  56/* Interrupt register fields */
  57#define ZYNQ_I2C_INTERRUPT_COMP         0x00000001
  58#define ZYNQ_I2C_INTERRUPT_DATA         0x00000002
  59#define ZYNQ_I2C_INTERRUPT_NACK         0x00000004
  60#define ZYNQ_I2C_INTERRUPT_TO           0x00000008
  61#define ZYNQ_I2C_INTERRUPT_SLVRDY       0x00000010
  62#define ZYNQ_I2C_INTERRUPT_RXOVF        0x00000020
  63#define ZYNQ_I2C_INTERRUPT_TXOVF        0x00000040
  64#define ZYNQ_I2C_INTERRUPT_RXUNF        0x00000080
  65#define ZYNQ_I2C_INTERRUPT_ARBLOST      0x00000200
  66
  67#define ZYNQ_I2C_FIFO_DEPTH             16
  68#define ZYNQ_I2C_TRANSFERT_SIZE_MAX     255 /* Controller transfer limit */
  69
  70static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
  71{
  72        return adap->hwadapnr ?
  73                /* Zynq PS I2C1 */
  74                (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
  75                /* Zynq PS I2C0 */
  76                (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
  77}
  78
  79/* I2C init called by cmd_i2c when doing 'i2c reset'. */
  80static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
  81                          int slaveadd)
  82{
  83        struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
  84
  85        /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
  86        writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
  87                (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
  88
  89        /* Enable master mode, ack, and 7-bit addressing */
  90        setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
  91                ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
  92}
  93
  94#ifdef DEBUG
  95static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
  96{
  97        int int_status;
  98        int status;
  99        int_status = readl(&zynq_i2c->interrupt_status);
 100
 101        status = readl(&zynq_i2c->status);
 102        if (int_status || status) {
 103                debug("Status: ");
 104                if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
 105                        debug("COMP ");
 106                if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
 107                        debug("DATA ");
 108                if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
 109                        debug("NACK ");
 110                if (int_status & ZYNQ_I2C_INTERRUPT_TO)
 111                        debug("TO ");
 112                if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
 113                        debug("SLVRDY ");
 114                if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
 115                        debug("RXOVF ");
 116                if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
 117                        debug("TXOVF ");
 118                if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
 119                        debug("RXUNF ");
 120                if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
 121                        debug("ARBLOST ");
 122                if (status & ZYNQ_I2C_STATUS_RXDV)
 123                        debug("RXDV ");
 124                if (status & ZYNQ_I2C_STATUS_TXDV)
 125                        debug("TXDV ");
 126                if (status & ZYNQ_I2C_STATUS_RXOVF)
 127                        debug("RXOVF ");
 128                if (status & ZYNQ_I2C_STATUS_BA)
 129                        debug("BA ");
 130                debug("TS%d ", readl(&zynq_i2c->transfer_size));
 131                debug("\n");
 132        }
 133}
 134#endif
 135
 136/* Wait for an interrupt */
 137static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
 138{
 139        int timeout, int_status;
 140
 141        for (timeout = 0; timeout < 100; timeout++) {
 142                udelay(100);
 143                int_status = readl(&zynq_i2c->interrupt_status);
 144                if (int_status & mask)
 145                        break;
 146        }
 147#ifdef DEBUG
 148        zynq_i2c_debug_status(zynq_i2c);
 149#endif
 150        /* Clear interrupt status flags */
 151        writel(int_status & mask, &zynq_i2c->interrupt_status);
 152
 153        return int_status & mask;
 154}
 155
 156/*
 157 * I2C probe called by cmd_i2c when doing 'i2c probe'.
 158 * Begin read, nak data byte, end.
 159 */
 160static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
 161{
 162        struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 163
 164        /* Attempt to read a byte */
 165        setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 166                ZYNQ_I2C_CONTROL_RW);
 167        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 168        writel(0xFF, &zynq_i2c->interrupt_status);
 169        writel(dev, &zynq_i2c->address);
 170        writel(1, &zynq_i2c->transfer_size);
 171
 172        return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 173                ZYNQ_I2C_INTERRUPT_NACK) &
 174                ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 175}
 176
 177/*
 178 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 179 * Begin write, send address byte(s), begin read, receive data bytes, end.
 180 */
 181static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 182                         int alen, u8 *data, int length)
 183{
 184        u32 status;
 185        u32 i = 0;
 186        u8 *cur_data = data;
 187        struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 188
 189        /* Check the hardware can handle the requested bytes */
 190        if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
 191                return -EINVAL;
 192
 193        /* Write the register address */
 194        setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 195                ZYNQ_I2C_CONTROL_HOLD);
 196        /*
 197         * Temporarily disable restart (by clearing hold)
 198         * It doesn't seem to work.
 199         */
 200        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 201        writel(0xFF, &zynq_i2c->interrupt_status);
 202        if (alen) {
 203                clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 204                writel(dev, &zynq_i2c->address);
 205                while (alen--)
 206                        writel(addr >> (8 * alen), &zynq_i2c->data);
 207
 208                /* Wait for the address to be sent */
 209                if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 210                        /* Release the bus */
 211                        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 212                        return -ETIMEDOUT;
 213                }
 214                debug("Device acked address\n");
 215        }
 216
 217        setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 218                ZYNQ_I2C_CONTROL_RW);
 219        /* Start reading data */
 220        writel(dev, &zynq_i2c->address);
 221        writel(length, &zynq_i2c->transfer_size);
 222
 223        /* Wait for data */
 224        do {
 225                status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 226                        ZYNQ_I2C_INTERRUPT_DATA);
 227                if (!status) {
 228                        /* Release the bus */
 229                        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 230                        return -ETIMEDOUT;
 231                }
 232                debug("Read %d bytes\n",
 233                      length - readl(&zynq_i2c->transfer_size));
 234                for (; i < length - readl(&zynq_i2c->transfer_size); i++)
 235                        *(cur_data++) = readl(&zynq_i2c->data);
 236        } while (readl(&zynq_i2c->transfer_size) != 0);
 237        /* All done... release the bus */
 238        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 239
 240#ifdef DEBUG
 241        zynq_i2c_debug_status(zynq_i2c);
 242#endif
 243        return 0;
 244}
 245
 246/*
 247 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 248 * Begin write, send address byte(s), send data bytes, end.
 249 */
 250static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 251                          int alen, u8 *data, int length)
 252{
 253        u8 *cur_data = data;
 254        struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 255
 256        /* Write the register address */
 257        setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 258                ZYNQ_I2C_CONTROL_HOLD);
 259        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 260        writel(0xFF, &zynq_i2c->interrupt_status);
 261        writel(dev, &zynq_i2c->address);
 262        if (alen) {
 263                while (alen--)
 264                        writel(addr >> (8 * alen), &zynq_i2c->data);
 265                /* Start the tranfer */
 266                if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 267                        /* Release the bus */
 268                        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 269                        return -ETIMEDOUT;
 270                }
 271                debug("Device acked address\n");
 272        }
 273
 274        while (length--) {
 275                writel(*(cur_data++), &zynq_i2c->data);
 276                if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
 277                        if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 278                                /* Release the bus */
 279                                clrbits_le32(&zynq_i2c->control,
 280                                             ZYNQ_I2C_CONTROL_HOLD);
 281                                return -ETIMEDOUT;
 282                        }
 283                }
 284        }
 285
 286        /* All done... release the bus */
 287        clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 288        /* Wait for the address and data to be sent */
 289        if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
 290                return -ETIMEDOUT;
 291        return 0;
 292}
 293
 294static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
 295                        unsigned int speed)
 296{
 297        if (speed != 1000000)
 298                return -EINVAL;
 299
 300        return 0;
 301}
 302
 303#ifdef CONFIG_ZYNQ_I2C0
 304U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 305                         zynq_i2c_write, zynq_i2c_set_bus_speed,
 306                         CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 307                         0)
 308#endif
 309#ifdef CONFIG_ZYNQ_I2C1
 310U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
 311                         zynq_i2c_write, zynq_i2c_set_bus_speed,
 312                         CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
 313                         1)
 314#endif
 315