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5
6
7#include <common.h>
8#include <malloc.h>
9#include <asm/fsl_serdes.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13
14
15
16
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19
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25
26
27#include <pci.h>
28#include <asm/io.h>
29#include <asm/fsl_pci.h>
30
31#ifndef CONFIG_SYS_PCI_MEMORY_BUS
32#define CONFIG_SYS_PCI_MEMORY_BUS 0
33#endif
34
35#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
36#define CONFIG_SYS_PCI_MEMORY_PHYS 0
37#endif
38
39#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
40#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
41#endif
42
43
44
45
46
47static void set_inbound_window(volatile pit_t *pi,
48 struct pci_region *r,
49 u64 size)
50{
51 u32 sz = (__ilog2_u64(size) - 1);
52#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
53 u32 flag = 0;
54#else
55 u32 flag = PIWAR_LOCAL;
56#endif
57
58 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
59
60 out_be32(&pi->pitar, r->phys_start >> 12);
61 out_be32(&pi->piwbar, r->bus_start >> 12);
62#ifdef CONFIG_SYS_PCI_64BIT
63 out_be32(&pi->piwbear, r->bus_start >> 44);
64#else
65 out_be32(&pi->piwbear, 0);
66#endif
67 if (r->flags & PCI_REGION_PREFETCH)
68 flag |= PIWAR_PF;
69 out_be32(&pi->piwar, flag | sz);
70}
71
72int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
73{
74 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
75
76
77 memset(hose, 0, sizeof(struct pci_controller));
78
79 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
80
81 return fsl_is_pci_agent(hose);
82}
83
84static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
85 u64 out_lo, u8 pcie_cap,
86 volatile pit_t *pi)
87{
88 struct pci_region *r = hose->regions + hose->region_count;
89 u64 sz = min((u64)gd->ram_size, (1ull << 32));
90
91 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
92 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
93 pci_size_t pci_sz;
94
95
96 if (bus_start > out_lo) {
97 printf ("no space for inbound mapping of memory\n");
98 return 0;
99 }
100
101
102 if ((bus_start + sz) > out_lo) {
103 sz = out_lo - bus_start;
104 debug ("limiting size to %llx\n", sz);
105 }
106
107 pci_sz = 1ull << __ilog2_u64(sz);
108
109
110
111
112 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
113 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
114 (u64)bus_start, (u64)phys_start, (u64)sz);
115 pci_set_region(r, bus_start, phys_start, sz,
116 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
117 PCI_REGION_PREFETCH);
118
119
120
121
122
123 if (pci_sz != sz)
124 sz = 2ull << __ilog2_u64(sz);
125
126 set_inbound_window(pi--, r++, sz);
127 sz = 0;
128 } else {
129 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
130 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
131 pci_set_region(r, bus_start, phys_start, pci_sz,
132 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
133 PCI_REGION_PREFETCH);
134 set_inbound_window(pi--, r++, pci_sz);
135
136 sz -= pci_sz;
137 bus_start += pci_sz;
138 phys_start += pci_sz;
139
140 pci_sz = 1ull << __ilog2_u64(sz);
141 if (sz) {
142 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
143 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
144 pci_set_region(r, bus_start, phys_start, pci_sz,
145 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
146 PCI_REGION_PREFETCH);
147 set_inbound_window(pi--, r++, pci_sz);
148 sz -= pci_sz;
149 bus_start += pci_sz;
150 phys_start += pci_sz;
151 }
152 }
153
154#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
155
156
157
158
159 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
160
161 if (gd->ram_size > pci_sz)
162 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
163 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
164 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
165 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
166 (u64)pci_sz);
167 pci_set_region(r,
168 CONFIG_SYS_PCI64_MEMORY_BUS,
169 CONFIG_SYS_PCI_MEMORY_PHYS,
170 pci_sz,
171 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
172 PCI_REGION_PREFETCH);
173 set_inbound_window(pi--, r++, pci_sz);
174#else
175 pci_sz = 1ull << __ilog2_u64(sz);
176 if (sz) {
177 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
178 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
179 pci_set_region(r, bus_start, phys_start, pci_sz,
180 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
181 PCI_REGION_PREFETCH);
182 sz -= pci_sz;
183 bus_start += pci_sz;
184 phys_start += pci_sz;
185 set_inbound_window(pi--, r++, pci_sz);
186 }
187#endif
188
189#ifdef CONFIG_PHYS_64BIT
190 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
191 printf("Was not able to map all of memory via "
192 "inbound windows -- %lld remaining\n", sz);
193#endif
194
195 hose->region_count = r - hose->regions;
196
197 return 1;
198}
199
200#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
201static void fsl_pcie_boot_master(pit_t *pi)
202{
203
204 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
205 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
206 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
207 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
208 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
209 struct pci_region r_inbound;
210 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
211 - 1;
212 pci_set_region(&r_inbound,
213 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
214 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
215 sz_inbound,
216 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
217
218 set_inbound_window(pi--, &r_inbound,
219 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
220
221
222 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
223 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
224 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
225 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
226 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
227 pci_set_region(&r_inbound,
228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
230 sz_inbound,
231 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
232
233 set_inbound_window(pi--, &r_inbound,
234 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
235
236
237 debug("PCIEBOOT - MASTER: Inbound window for slave's "
238 "ucode and ENV; "
239 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
240 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
241 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
242 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
243 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
244 - 1;
245 pci_set_region(&r_inbound,
246 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
248 sz_inbound,
249 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
250
251 set_inbound_window(pi--, &r_inbound,
252 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
253}
254
255static void fsl_pcie_boot_master_release_slave(int port)
256{
257 unsigned long release_addr;
258
259
260 switch (port) {
261 case 1:
262 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
263 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
264 break;
265#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
266 case 2:
267 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
268 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
269 break;
270#endif
271#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
272 case 3:
273 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
274 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
275 break;
276#endif
277 default:
278 release_addr = 0;
279 break;
280 }
281 if (release_addr != 0) {
282 out_be32((void *)release_addr,
283 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
284 debug("PCIEBOOT - MASTER: "
285 "Release slave successfully! Now the slave should start up!\n");
286 } else {
287 debug("PCIEBOOT - MASTER: "
288 "Release slave failed!\n");
289 }
290}
291#endif
292
293void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
294{
295 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
296 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
297 u16 temp16;
298 u32 temp32;
299 u32 block_rev;
300 int enabled, r, inbound = 0;
301 u16 ltssm;
302 u8 temp8, pcie_cap;
303 int pcie_cap_pos;
304 int pci_dcr;
305 int pci_dsr;
306 int pci_lsr;
307
308#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
309 int pci_lcr;
310#endif
311
312 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
313 struct pci_region *reg = hose->regions + hose->region_count;
314 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
315
316
317 volatile pot_t *po = &pci->pot[1];
318 volatile pit_t *pi;
319
320 u64 out_hi = 0, out_lo = -1ULL;
321 u32 pcicsrbar, pcicsrbar_sz;
322
323 pci_setup_indirect(hose, cfg_addr, cfg_data);
324
325 block_rev = in_be32(&pci->block_rev1);
326 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
327 pi = &pci->pit[2];
328 } else {
329 pi = &pci->pit[3];
330 }
331
332
333 for (r = 0; r < hose->region_count; r++) {
334 unsigned long flags = hose->regions[r].flags;
335 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
336
337 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
338 if (flags != PCI_REGION_SYS_MEMORY) {
339 u64 start = hose->regions[r].bus_start;
340 u64 end = start + hose->regions[r].size;
341
342 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
343 out_be32(&po->potar, start >> 12);
344#ifdef CONFIG_SYS_PCI_64BIT
345 out_be32(&po->potear, start >> 44);
346#else
347 out_be32(&po->potear, 0);
348#endif
349 if (hose->regions[r].flags & PCI_REGION_IO) {
350 out_be32(&po->powar, POWAR_EN | sz |
351 POWAR_IO_READ | POWAR_IO_WRITE);
352 } else {
353 out_be32(&po->powar, POWAR_EN | sz |
354 POWAR_MEM_READ | POWAR_MEM_WRITE);
355 out_lo = min(start, out_lo);
356 out_hi = max(end, out_hi);
357 }
358 po++;
359 }
360 }
361 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
362
363
364 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
365 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
366 pcicsrbar_sz = ~pcicsrbar_sz + 1;
367
368 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
369 (out_lo > 0x100000000ull))
370 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
371 else
372 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
373 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
374
375 out_lo = min(out_lo, (u64)pcicsrbar);
376
377 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
378
379 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
380 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
381 hose->region_count++;
382
383
384 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
385 pci_dcr = pcie_cap_pos + 0x08;
386 pci_dsr = pcie_cap_pos + 0x0a;
387 pci_lsr = pcie_cap_pos + 0x12;
388
389 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
390
391#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
392
393 char *s = getenv("bootmaster");
394 char pcie[6];
395 sprintf(pcie, "PCIE%d", pci_info->pci_num);
396
397 if (s && (strcmp(s, pcie) == 0)) {
398 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
399 pci_info->pci_num);
400 fsl_pcie_boot_master((pit_t *)pi);
401 } else {
402
403 inbound = fsl_pci_setup_inbound_windows(hose,
404 out_lo, pcie_cap, pi);
405 }
406#else
407
408 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
409#endif
410
411 for (r = 0; r < hose->region_count; r++)
412 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
413 (u64)hose->regions[r].phys_start,
414 (u64)hose->regions[r].bus_start,
415 (u64)hose->regions[r].size,
416 hose->regions[r].flags);
417
418 pci_register_hose(hose);
419 pciauto_config_init(hose);
420 hose->current_busno = hose->first_busno;
421
422 out_be32(&pci->pedr, 0xffffffff);
423 out_be32(&pci->peer, ~0x20140);
424
425
426
427
428 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
429 temp32 |= 0xf000e;
430 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
431
432#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
433 pci_lcr = pcie_cap_pos + 0x10;
434 temp32 = 0;
435 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
436 temp32 &= ~0x03;
437 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
438 udelay(1);
439#endif
440 if (pcie_cap == PCI_CAP_ID_EXP) {
441 if (block_rev >= PEX_IP_BLK_REV_3_0) {
442#define PEX_CSR0_LTSSM_MASK 0xFC
443#define PEX_CSR0_LTSSM_SHIFT 2
444 ltssm = (in_be32(&pci->pex_csr0)
445 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
446 enabled = (ltssm == 0x11) ? 1 : 0;
447#ifdef CONFIG_FSL_PCIE_RESET
448 int i;
449
450 setbits_be32(&pci->pdb_stat, 0x08000000);
451 (void) in_be32(&pci->pdb_stat);
452 udelay(1000);
453
454 clrbits_be32(&pci->pdb_stat, 0x08000000);
455 asm("sync;isync");
456 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
457 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
458 <ssm);
459 udelay(1000);
460 }
461#endif
462 } else {
463
464
465 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
466 enabled = ltssm >= PCI_LTSSM_L0;
467
468#ifdef CONFIG_FSL_PCIE_RESET
469 if (ltssm == 1) {
470 int i;
471 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
472
473 setbits_be32(&pci->pdb_stat, 0x08000000);
474 (void) in_be32(&pci->pdb_stat);
475 udelay(100);
476 debug(" Asserting PCIe reset @%p = %x\n",
477 &pci->pdb_stat, in_be32(&pci->pdb_stat));
478
479 clrbits_be32(&pci->pdb_stat, 0x08000000);
480 asm("sync;isync");
481 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
482 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
483 <ssm);
484 udelay(1000);
485 debug("....PCIe link error. "
486 "LTSSM=0x%02x.\n", ltssm);
487 }
488 enabled = ltssm >= PCI_LTSSM_L0;
489
490
491
492
493 pci_hose_write_config_dword(hose, dev,
494 PCI_BASE_ADDRESS_0, pcicsrbar);
495 }
496#endif
497 }
498
499#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
500 if (enabled == 0) {
501 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
502 temp32 = in_be32(&srds_regs->srdspccr0);
503
504 if ((temp32 >> 28) == 3) {
505 int i;
506
507 out_be32(&srds_regs->srdspccr0, 2 << 28);
508 setbits_be32(&pci->pdb_stat, 0x08000000);
509 in_be32(&pci->pdb_stat);
510 udelay(100);
511 clrbits_be32(&pci->pdb_stat, 0x08000000);
512 asm("sync;isync");
513 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
514 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
515 udelay(1000);
516 }
517 enabled = ltssm >= PCI_LTSSM_L0;
518 }
519 }
520#endif
521 if (!enabled) {
522
523
524
525
526 if (fsl_is_pci_agent(hose))
527 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
528 else
529 printf("no link, regs @ 0x%lx\n", pci_info->regs);
530 hose->last_busno = hose->first_busno;
531 return;
532 }
533
534 out_be32(&pci->pme_msg_det, 0xffffffff);
535 out_be32(&pci->pme_msg_int_en, 0xffffffff);
536
537
538 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
539 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
540 (temp16 & 0xf), pci_info->regs);
541
542 hose->current_busno++;
543 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
544 }
545
546
547
548
549
550 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
551 hose->pci_prefetch, hose->pci_io);
552
553 if (inbound) {
554 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
555 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
556 temp16 | PCI_COMMAND_MEMORY);
557 }
558
559#ifndef CONFIG_PCI_NOSCAN
560 if (!fsl_is_pci_agent(hose)) {
561 debug(" Scanning PCI bus %02x\n",
562 hose->current_busno);
563 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
564 } else {
565 debug(" Not scanning PCI bus %02x. PI=%x\n",
566 hose->current_busno, temp8);
567 hose->last_busno = hose->current_busno;
568 }
569
570
571
572
573 if (pcie_cap == PCI_CAP_ID_EXP) {
574 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
575 }
576#else
577 hose->last_busno = hose->current_busno;
578#endif
579
580
581 if (pcie_cap == PCI_CAP_ID_EXP)
582 out_be32(&pci->pme_msg_det, 0xffffffff);
583 out_be32(&pci->pedr, 0xffffffff);
584
585 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
586 if (temp16) {
587 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
588 }
589
590 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
591 if (temp16) {
592 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
593 }
594}
595
596int fsl_is_pci_agent(struct pci_controller *hose)
597{
598 int pcie_cap_pos;
599 u8 pcie_cap;
600 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
601
602 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
603 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
604 if (pcie_cap == PCI_CAP_ID_EXP) {
605 u8 header_type;
606
607 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
608 &header_type);
609 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
610 } else {
611 u8 prog_if;
612
613 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
614
615
616
617
618 return (prog_if == FSL_PROG_IF_AGENT);
619 }
620}
621
622int fsl_pci_init_port(struct fsl_pci_info *pci_info,
623 struct pci_controller *hose, int busno)
624{
625 volatile ccsr_fsl_pci_t *pci;
626 struct pci_region *r;
627 pci_dev_t dev = PCI_BDF(busno,0,0);
628 int pcie_cap_pos;
629 u8 pcie_cap;
630
631 pci = (ccsr_fsl_pci_t *) pci_info->regs;
632
633
634
635
636 if (in_be32(&pci->pme_msg_det)) {
637 out_be32(&pci->pme_msg_det, 0xffffffff);
638 debug (" with errors. Clearing. Now 0x%08x",
639 pci->pme_msg_det);
640 }
641
642 r = hose->regions + hose->region_count;
643
644
645 pci_set_region(r++,
646 pci_info->mem_bus,
647 pci_info->mem_phys,
648 pci_info->mem_size,
649 PCI_REGION_MEM);
650
651
652 pci_set_region(r++,
653 pci_info->io_bus,
654 pci_info->io_phys,
655 pci_info->io_size,
656 PCI_REGION_IO);
657
658 hose->region_count = r - hose->regions;
659 hose->first_busno = busno;
660
661 fsl_pci_init(hose, pci_info);
662
663 if (fsl_is_pci_agent(hose)) {
664 fsl_pci_config_unlock(hose);
665 hose->last_busno = hose->first_busno;
666#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
667 } else {
668
669 char *s = getenv("bootmaster");
670 char pcie[6];
671 sprintf(pcie, "PCIE%d", pci_info->pci_num);
672
673 if (s && (strcmp(s, pcie) == 0))
674 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
675#endif
676 }
677
678 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
679 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
680 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
681 "e" : "", pci_info->pci_num,
682 hose->first_busno, hose->last_busno);
683 return(hose->last_busno + 1);
684}
685
686
687void fsl_pci_config_unlock(struct pci_controller *hose)
688{
689 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
690 int pcie_cap_pos;
691 u8 pcie_cap;
692 u16 pbfr;
693
694 if (!fsl_is_pci_agent(hose))
695 return;
696
697 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
698 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
699 if (pcie_cap != 0x0) {
700 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
701 u32 block_rev = in_be32(&pci->block_rev1);
702
703 if (block_rev >= PEX_IP_BLK_REV_3_0)
704 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
705 else
706 pci_hose_write_config_byte(hose, dev,
707 FSL_PCIE_CFG_RDY, 0x1);
708 } else {
709
710 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
711 pbfr &= ~0x20;
712 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
713 }
714}
715
716#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
717 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
718int fsl_configure_pcie(struct fsl_pci_info *info,
719 struct pci_controller *hose,
720 const char *connected, int busno)
721{
722 int is_endpoint;
723
724 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
725 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
726
727 is_endpoint = fsl_setup_hose(hose, info->regs);
728 printf("PCIe%u: %s", info->pci_num,
729 is_endpoint ? "Endpoint" : "Root Complex");
730 if (connected)
731 printf(" of %s", connected);
732 puts(", ");
733
734 return fsl_pci_init_port(info, hose, busno);
735}
736
737#if defined(CONFIG_FSL_CORENET)
738#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
739 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
740 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
741 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
742 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
743#else
744 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
745 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
746 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
747 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
748#endif
749 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
750#elif defined(CONFIG_MPC85xx)
751 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
752 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
753 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
754 #define _DEVDISR_PCIE4 0
755 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
756#elif defined(CONFIG_MPC86xx)
757 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
758 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
759 #define _DEVDISR_PCIE3 0
760 #define _DEVDISR_PCIE4 0
761 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
762 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
763#else
764#error "No defines for DEVDISR_PCIE"
765#endif
766
767
768static const char *__board_serdes_name(enum srds_prtcl device)
769{
770 switch (device) {
771#ifdef CONFIG_SYS_PCIE1_NAME
772 case PCIE1:
773 return CONFIG_SYS_PCIE1_NAME;
774#endif
775#ifdef CONFIG_SYS_PCIE2_NAME
776 case PCIE2:
777 return CONFIG_SYS_PCIE2_NAME;
778#endif
779#ifdef CONFIG_SYS_PCIE3_NAME
780 case PCIE3:
781 return CONFIG_SYS_PCIE3_NAME;
782#endif
783#ifdef CONFIG_SYS_PCIE4_NAME
784 case PCIE4:
785 return CONFIG_SYS_PCIE4_NAME;
786#endif
787 default:
788 return NULL;
789 }
790
791 return NULL;
792}
793
794__attribute__((weak, alias("__board_serdes_name"))) const char *
795board_serdes_name(enum srds_prtcl device);
796
797static u32 devdisr_mask[] = {
798 _DEVDISR_PCIE1,
799 _DEVDISR_PCIE2,
800 _DEVDISR_PCIE3,
801 _DEVDISR_PCIE4,
802};
803
804int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
805 struct fsl_pci_info *pci_info)
806{
807 struct pci_controller *hose;
808 int num = dev - PCIE1;
809
810 hose = calloc(1, sizeof(struct pci_controller));
811 if (!hose)
812 return busno;
813
814 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
815 busno = fsl_configure_pcie(pci_info, hose,
816 board_serdes_name(dev), busno);
817 } else {
818 printf("PCIe%d: disabled\n", num + 1);
819 }
820
821 return busno;
822}
823
824int fsl_pcie_init_board(int busno)
825{
826 struct fsl_pci_info pci_info;
827 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
828 u32 devdisr;
829 u32 *addr;
830
831#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
832 addr = &gur->devdisr3;
833#else
834 addr = &gur->devdisr;
835#endif
836 devdisr = in_be32(addr);
837
838#ifdef CONFIG_PCIE1
839 SET_STD_PCIE_INFO(pci_info, 1);
840 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
841#else
842 setbits_be32(addr, _DEVDISR_PCIE1);
843#endif
844
845#ifdef CONFIG_PCIE2
846 SET_STD_PCIE_INFO(pci_info, 2);
847 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
848#else
849 setbits_be32(addr, _DEVDISR_PCIE2);
850#endif
851
852#ifdef CONFIG_PCIE3
853 SET_STD_PCIE_INFO(pci_info, 3);
854 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
855#else
856 setbits_be32(addr, _DEVDISR_PCIE3);
857#endif
858
859#ifdef CONFIG_PCIE4
860 SET_STD_PCIE_INFO(pci_info, 4);
861 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
862#else
863 setbits_be32(addr, _DEVDISR_PCIE4);
864#endif
865
866 return busno;
867}
868#else
869int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
870 struct fsl_pci_info *pci_info)
871{
872 return busno;
873}
874
875int fsl_pcie_init_board(int busno)
876{
877 return busno;
878}
879#endif
880
881#ifdef CONFIG_OF_BOARD_SETUP
882#include <libfdt.h>
883#include <fdt_support.h>
884
885void ft_fsl_pci_setup(void *blob, const char *pci_compat,
886 unsigned long ctrl_addr)
887{
888 int off;
889 u32 bus_range[2];
890 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
891 struct pci_controller *hose;
892
893 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
894
895
896 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
897 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
898
899 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
900
901 if (off < 0)
902 return;
903
904
905 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
906 fdt_del_node(blob, off);
907 } else {
908 bus_range[0] = 0;
909 bus_range[1] = hose->last_busno - hose->first_busno;
910 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
911 fdt_pci_dma_ranges(blob, off, hose);
912 }
913}
914#endif
915
