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13#include <common.h>
14#include <pci.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/iomux.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/gpio.h>
19#include <asm/io.h>
20#include <linux/sizes.h>
21#include <errno.h>
22#include <asm/arch/sys_proto.h>
23
24#define PCI_ACCESS_READ 0
25#define PCI_ACCESS_WRITE 1
26
27#ifdef CONFIG_MX6SX
28#define MX6_DBI_ADDR 0x08ffc000
29#define MX6_IO_ADDR 0x08000000
30#define MX6_MEM_ADDR 0x08100000
31#define MX6_ROOT_ADDR 0x08f00000
32#else
33#define MX6_DBI_ADDR 0x01ffc000
34#define MX6_IO_ADDR 0x01000000
35#define MX6_MEM_ADDR 0x01100000
36#define MX6_ROOT_ADDR 0x01f00000
37#endif
38#define MX6_DBI_SIZE 0x4000
39#define MX6_IO_SIZE 0x100000
40#define MX6_MEM_SIZE 0xe00000
41#define MX6_ROOT_SIZE 0xfc000
42
43
44#define PL_OFFSET 0x700
45#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
46#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
47#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
48#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
49
50#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
51#define PCIE_PHY_CTRL_DATA_LOC 0
52#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
53#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
54#define PCIE_PHY_CTRL_WR_LOC 18
55#define PCIE_PHY_CTRL_RD_LOC 19
56
57#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
58#define PCIE_PHY_STAT_DATA_LOC 0
59#define PCIE_PHY_STAT_ACK_LOC 16
60
61
62#define PCIE_PHY_RX_ASIC_OUT 0x100D
63
64#define PHY_RX_OVRD_IN_LO 0x1005
65#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
66#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
67
68#define PCIE_PHY_PUP_REQ (1 << 7)
69
70
71#define PCIE_ATU_VIEWPORT 0x900
72#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
73#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
74#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
75#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
76#define PCIE_ATU_CR1 0x904
77#define PCIE_ATU_TYPE_MEM (0x0 << 0)
78#define PCIE_ATU_TYPE_IO (0x2 << 0)
79#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
80#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
81#define PCIE_ATU_CR2 0x908
82#define PCIE_ATU_ENABLE (0x1 << 31)
83#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
84#define PCIE_ATU_LOWER_BASE 0x90C
85#define PCIE_ATU_UPPER_BASE 0x910
86#define PCIE_ATU_LIMIT 0x914
87#define PCIE_ATU_LOWER_TARGET 0x918
88#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
89#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
90#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
91#define PCIE_ATU_UPPER_TARGET 0x91C
92
93
94
95
96static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
97{
98 u32 val;
99 u32 max_iterations = 10;
100 u32 wait_counter = 0;
101
102 do {
103 val = readl(dbi_base + PCIE_PHY_STAT);
104 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
105 wait_counter++;
106
107 if (val == exp_val)
108 return 0;
109
110 udelay(1);
111 } while (wait_counter < max_iterations);
112
113 return -ETIMEDOUT;
114}
115
116static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
117{
118 u32 val;
119 int ret;
120
121 val = addr << PCIE_PHY_CTRL_DATA_LOC;
122 writel(val, dbi_base + PCIE_PHY_CTRL);
123
124 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
125 writel(val, dbi_base + PCIE_PHY_CTRL);
126
127 ret = pcie_phy_poll_ack(dbi_base, 1);
128 if (ret)
129 return ret;
130
131 val = addr << PCIE_PHY_CTRL_DATA_LOC;
132 writel(val, dbi_base + PCIE_PHY_CTRL);
133
134 ret = pcie_phy_poll_ack(dbi_base, 0);
135 if (ret)
136 return ret;
137
138 return 0;
139}
140
141
142static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
143{
144 u32 val, phy_ctl;
145 int ret;
146
147 ret = pcie_phy_wait_ack(dbi_base, addr);
148 if (ret)
149 return ret;
150
151
152 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
153 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
154
155 ret = pcie_phy_poll_ack(dbi_base, 1);
156 if (ret)
157 return ret;
158
159 val = readl(dbi_base + PCIE_PHY_STAT);
160 *data = val & 0xffff;
161
162
163 writel(0x00, dbi_base + PCIE_PHY_CTRL);
164
165 ret = pcie_phy_poll_ack(dbi_base, 0);
166 if (ret)
167 return ret;
168
169 return 0;
170}
171
172static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
173{
174 u32 var;
175 int ret;
176
177
178
179 ret = pcie_phy_wait_ack(dbi_base, addr);
180 if (ret)
181 return ret;
182
183 var = data << PCIE_PHY_CTRL_DATA_LOC;
184 writel(var, dbi_base + PCIE_PHY_CTRL);
185
186
187 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
188 writel(var, dbi_base + PCIE_PHY_CTRL);
189
190 ret = pcie_phy_poll_ack(dbi_base, 1);
191 if (ret)
192 return ret;
193
194
195 var = data << PCIE_PHY_CTRL_DATA_LOC;
196 writel(var, dbi_base + PCIE_PHY_CTRL);
197
198
199 ret = pcie_phy_poll_ack(dbi_base, 0);
200 if (ret)
201 return ret;
202
203
204 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
205 writel(var, dbi_base + PCIE_PHY_CTRL);
206
207
208 ret = pcie_phy_poll_ack(dbi_base, 1);
209 if (ret)
210 return ret;
211
212
213 var = data << PCIE_PHY_CTRL_DATA_LOC;
214 writel(var, dbi_base + PCIE_PHY_CTRL);
215
216
217 ret = pcie_phy_poll_ack(dbi_base, 0);
218 if (ret)
219 return ret;
220
221 writel(0x0, dbi_base + PCIE_PHY_CTRL);
222
223 return 0;
224}
225
226static int imx6_pcie_link_up(void)
227{
228 u32 rc, ltssm;
229 int rx_valid, temp;
230
231
232 rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
233 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
234 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
235 return -EAGAIN;
236
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243
244 pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
245 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
246
247 if (rx_valid & 0x01)
248 return 0;
249
250 if (ltssm != 0x0d)
251 return 0;
252
253 printf("transition to gen2 is stuck, reset PHY!\n");
254
255 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
256 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
257 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
258
259 udelay(3000);
260
261 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
262 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
263 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
264
265 return 0;
266}
267
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270
271static int imx_pcie_regions_setup(void)
272{
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286 setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
287 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
288
289
290 setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
291 PCI_CLASS_BRIDGE_PCI << 16);
292
293
294 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
295
296 writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
297 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
298 writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
299
300 writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
301 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
302 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
303 writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
304
305 return 0;
306}
307
308
309
310
311static uint32_t get_bus_address(pci_dev_t d, int where)
312{
313 uint32_t va_address;
314
315
316 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
317
318 if (PCI_BUS(d) < 2)
319 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
320 else
321 writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
322
323 if (PCI_BUS(d) == 0) {
324 va_address = MX6_DBI_ADDR;
325 } else {
326 writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
327 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
328 }
329
330 va_address += (where & ~0x3);
331
332 return va_address;
333}
334
335static int imx_pcie_addr_valid(pci_dev_t d)
336{
337 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
338 return -EINVAL;
339 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
340 return -EINVAL;
341 return 0;
342}
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357static void imx_pcie_fix_dabt_handler(bool set)
358{
359 extern uint32_t *_data_abort;
360 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
361
362 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
363 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
364
365 static uint32_t data_abort_backup;
366
367 if (set) {
368 data_abort_backup = *data_abort_addr;
369 *data_abort_addr = data_abort_bounce_addr;
370 } else {
371 *data_abort_addr = data_abort_backup;
372 }
373}
374
375static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
376 int where, u32 *val)
377{
378 uint32_t va_address;
379 int ret;
380
381 ret = imx_pcie_addr_valid(d);
382 if (ret) {
383 *val = 0xffffffff;
384 return 0;
385 }
386
387 va_address = get_bus_address(d, where);
388
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396 imx_pcie_fix_dabt_handler(true);
397 writel(0xffffffff, val);
398 *val = readl(va_address);
399 imx_pcie_fix_dabt_handler(false);
400
401 return 0;
402}
403
404static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
405 int where, u32 val)
406{
407 uint32_t va_address = 0;
408 int ret;
409
410 ret = imx_pcie_addr_valid(d);
411 if (ret)
412 return ret;
413
414 va_address = get_bus_address(d, where);
415
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421 imx_pcie_fix_dabt_handler(true);
422 writel(val, va_address);
423 imx_pcie_fix_dabt_handler(false);
424
425 return 0;
426}
427
428
429
430
431static int imx6_pcie_assert_core_reset(void)
432{
433 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
434
435 if (is_mx6dqp())
436 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
437
438#if defined(CONFIG_MX6SX)
439 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
440
441
442 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
443
444 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
445
446 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
447#else
448 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
449 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
450#endif
451
452 return 0;
453}
454
455static int imx6_pcie_init_phy(void)
456{
457 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
458
459 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
460
461 clrsetbits_le32(&iomuxc_regs->gpr[12],
462 IOMUXC_GPR12_DEVICE_TYPE_MASK,
463 IOMUXC_GPR12_DEVICE_TYPE_RC);
464 clrsetbits_le32(&iomuxc_regs->gpr[12],
465 IOMUXC_GPR12_LOS_LEVEL_MASK,
466 IOMUXC_GPR12_LOS_LEVEL_9);
467
468#ifdef CONFIG_MX6SX
469 clrsetbits_le32(&iomuxc_regs->gpr[12],
470 IOMUXC_GPR12_RX_EQ_MASK,
471 IOMUXC_GPR12_RX_EQ_2);
472#endif
473
474 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
475 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
476 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
477 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
478 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
479 &iomuxc_regs->gpr[8]);
480
481 return 0;
482}
483
484__weak int imx6_pcie_toggle_power(void)
485{
486#ifdef CONFIG_PCIE_IMX_POWER_GPIO
487 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
488 mdelay(20);
489 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
490 mdelay(20);
491#endif
492 return 0;
493}
494
495__weak int imx6_pcie_toggle_reset(void)
496{
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525#ifdef CONFIG_PCIE_IMX_PERST_GPIO
526 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
527 mdelay(20);
528 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
529 mdelay(20);
530#else
531 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
532#endif
533 return 0;
534}
535
536static int imx6_pcie_deassert_core_reset(void)
537{
538 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
539
540 imx6_pcie_toggle_power();
541
542 enable_pcie_clock();
543
544 if (is_mx6dqp())
545 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
546
547
548
549
550
551 mdelay(50);
552
553#if defined(CONFIG_MX6SX)
554
555 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
556
557 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
558#else
559
560 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
561 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
562#endif
563
564 imx6_pcie_toggle_reset();
565
566 return 0;
567}
568
569static int imx_pcie_link_up(void)
570{
571 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
572 uint32_t tmp;
573 int count = 0;
574
575 imx6_pcie_assert_core_reset();
576 imx6_pcie_init_phy();
577 imx6_pcie_deassert_core_reset();
578
579 imx_pcie_regions_setup();
580
581
582
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585
586
587 tmp = readl(MX6_DBI_ADDR + 0x7c);
588 tmp &= ~0xf;
589 tmp |= 0x1;
590 writel(tmp, MX6_DBI_ADDR + 0x7c);
591
592
593 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
594
595 while (!imx6_pcie_link_up()) {
596 udelay(10);
597 count++;
598 if (count >= 4000) {
599#ifdef CONFIG_PCI_SCAN_SHOW
600 puts("PCI: pcie phy link never came up\n");
601#endif
602 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
603 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
604 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
605 return -EINVAL;
606 }
607 }
608
609 return 0;
610}
611
612void imx_pcie_init(void)
613{
614
615 static struct pci_controller pcc;
616 struct pci_controller *hose = &pcc;
617 int ret;
618
619 memset(&pcc, 0, sizeof(pcc));
620
621
622 pci_set_region(&hose->regions[0],
623 MX6_IO_ADDR, MX6_IO_ADDR,
624 MX6_IO_SIZE, PCI_REGION_IO);
625
626
627 pci_set_region(&hose->regions[1],
628 MX6_MEM_ADDR, MX6_MEM_ADDR,
629 MX6_MEM_SIZE, PCI_REGION_MEM);
630
631
632 pci_set_region(&hose->regions[2],
633 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
634 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
635
636 hose->region_count = 3;
637
638 pci_set_ops(hose,
639 pci_hose_read_config_byte_via_dword,
640 pci_hose_read_config_word_via_dword,
641 imx_pcie_read_config,
642 pci_hose_write_config_byte_via_dword,
643 pci_hose_write_config_word_via_dword,
644 imx_pcie_write_config);
645
646
647 ret = imx_pcie_link_up();
648
649 if (!ret) {
650 pci_register_hose(hose);
651 hose->last_busno = pci_hose_scan(hose);
652 }
653}
654
655
656void pci_init_board(void)
657{
658 imx_pcie_init();
659}
660