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12#ifndef __RK_SPI_H
13#define __RK_SPI_H
14
15struct rockchip_spi {
16 u32 ctrlr0;
17 u32 ctrlr1;
18 u32 enr;
19 u32 ser;
20 u32 baudr;
21 u32 txftlr;
22 u32 rxftlr;
23 u32 txflr;
24 u32 rxflr;
25 u32 sr;
26 u32 ipr;
27 u32 imr;
28 u32 isr;
29 u32 risr;
30 u32 icr;
31 u32 dmacr;
32 u32 dmatdlr;
33 u32 dmardlr;
34 u32 reserved[0xef];
35 u32 txdr[0x100];
36 u32 rxdr[0x100];
37};
38
39
40enum {
41 DFS_SHIFT = 0,
42 DFS_MASK = 3,
43 DFS_4BIT = 0,
44 DFS_8BIT,
45 DFS_16BIT,
46 DFS_RESV,
47
48 CFS_SHIFT = 2,
49 CFS_MASK = 0xf,
50
51 SCPH_SHIFT = 6,
52 SCPH_MASK = 1,
53 SCPH_TOGMID = 0,
54 SCPH_TOGSTA,
55
56 SCOL_SHIFT = 7,
57 SCOL_MASK = 1,
58 SCOL_LOW = 0,
59 SCOL_HIGH,
60
61 CSM_SHIFT = 8,
62 CSM_MASK = 0x3,
63 CSM_KEEP = 0,
64 CSM_HALF,
65 CSM_ONE,
66 CSM_RESV,
67
68 SSN_DELAY_SHIFT = 10,
69 SSN_DELAY_MASK = 1,
70 SSN_DELAY_HALF = 0,
71 SSN_DELAY_ONE = 1,
72
73 SEM_SHIFT = 11,
74 SEM_MASK = 1,
75 SEM_LITTLE = 0,
76 SEM_BIG,
77
78 FBM_SHIFT = 12,
79 FBM_MASK = 1,
80 FBM_MSB = 0,
81 FBM_LSB,
82
83 HALF_WORD_TX_SHIFT = 13,
84 HALF_WORD_MASK = 1,
85 HALF_WORD_ON = 0,
86 HALF_WORD_OFF,
87
88 RXDSD_SHIFT = 14,
89 RXDSD_MASK = 3,
90
91 FRF_SHIFT = 16,
92 FRF_MASK = 3,
93 FRF_SPI = 0,
94 FRF_SSP,
95 FRF_MICROWIRE,
96 FRF_RESV,
97
98 TMOD_SHIFT = 18,
99 TMOD_MASK = 3,
100 TMOD_TR = 0,
101 TMOD_TO,
102 TMOD_RO,
103 TMOD_RESV,
104
105 OMOD_SHIFT = 20,
106 OMOD_MASK = 1,
107 OMOD_MASTER = 0,
108 OMOD_SLAVE,
109};
110
111
112enum {
113 SR_MASK = 0x7f,
114 SR_BUSY = 1 << 0,
115 SR_TF_FULL = 1 << 1,
116 SR_TF_EMPT = 1 << 2,
117 SR_RF_EMPT = 1 << 3,
118 SR_RF_FULL = 1 << 4,
119};
120
121#define ROCKCHIP_SPI_TIMEOUT_MS 1000
122#define ROCKCHIP_SPI_MAX_RATE 48000000
123
124#endif
125