1/* 2 * (C) Copyright 2001-2004 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 21#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ 22#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ 23#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ 24 25#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 26 27#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 28#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 29 30#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 31 32#define CONFIG_BAUDRATE 9600 33 34#undef CONFIG_BOOTARGS 35#undef CONFIG_BOOTCOMMAND 36 37#define CONFIG_PREBOOT /* enable preboot variable */ 38 39#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 40#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 41 42#define CONFIG_PPC4xx_EMAC 43#define CONFIG_MII 1 /* MII PHY management */ 44#define CONFIG_PHY_ADDR 0 /* PHY address */ 45#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 46#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 47 48#undef CONFIG_HAS_ETH1 49 50#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ 51 52/* 53 * BOOTP options 54 */ 55#define CONFIG_BOOTP_SUBNETMASK 56#define CONFIG_BOOTP_GATEWAY 57#define CONFIG_BOOTP_HOSTNAME 58#define CONFIG_BOOTP_BOOTPATH 59#define CONFIG_BOOTP_DNS 60#define CONFIG_BOOTP_DNS2 61#define CONFIG_BOOTP_SEND_HOSTNAME 62 63/* 64 * Command line configuration. 65 */ 66#define CONFIG_CMD_PCI 67#define CONFIG_CMD_IRQ 68#define CONFIG_CMD_IDE 69#define CONFIG_CMD_DATE 70#define CONFIG_CMD_BSP 71#define CONFIG_CMD_EEPROM 72 73#define CONFIG_MAC_PARTITION 74#define CONFIG_DOS_PARTITION 75 76#define CONFIG_SUPPORT_VFAT 77 78#undef CONFIG_WATCHDOG /* watchdog disabled */ 79 80#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 81 82/* 83 * Miscellaneous configurable options 84 */ 85#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 86 87#if defined(CONFIG_CMD_KGDB) 88#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 89#else 90#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 91#endif 92#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 95 96#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 97 98#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 99 100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 102 103#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 104#define CONFIG_SYS_NS16550_SERIAL 105#define CONFIG_SYS_NS16550_REG_SIZE 1 106#define CONFIG_SYS_NS16550_CLK get_serial_clock() 107 108#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 109#define CONFIG_SYS_BASE_BAUD 691200 110 111#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 112#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 113 114#define CONFIG_CMDLINE_EDITING /* add command line history */ 115 116#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 117 118/*----------------------------------------------------------------------- 119 * PCI stuff 120 *----------------------------------------------------------------------- 121 */ 122#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 123#define PCI_HOST_FORCE 1 /* configure as pci host */ 124#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 125 126#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 127#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 128 /* resource configuration */ 129 130#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 131 132#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ 133 134#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ 135 136#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 137#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ 138#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ 139#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 140#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ 141#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ 142#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 143#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 144#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 145#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ 146 147#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ 148 149/*----------------------------------------------------------------------- 150 * IDE/ATA stuff 151 *----------------------------------------------------------------------- 152 */ 153#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 154#undef CONFIG_IDE_LED /* no led for ide supported */ 155#define CONFIG_IDE_RESET 1 /* reset for ide supported */ 156 157#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ 158#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ 159 160#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 161#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 162 163#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 164#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 165#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ 166 167/*----------------------------------------------------------------------- 168 * Start addresses for the final memory configuration 169 * (Set up by the startup code) 170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 171 */ 172#define CONFIG_SYS_SDRAM_BASE 0x00000000 173#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 175#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 176#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 177 178#define CONFIG_PRAM 0 /* use pram variable to overwrite */ 179 180/* 181 * For booting Linux, the board info and command line data 182 * have to be in the first 8 MB of memory, since this is 183 * the maximum mapped by the Linux kernel during initialization. 184 */ 185#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 186 187/*----------------------------------------------------------------------- 188 * FLASH organization 189 */ 190#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 191#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 192 193#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 194#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 195 196#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 197#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 198#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 199/* 200 * The following defines are added for buggy IOP480 byte interface. 201 * All other boards should use the standard values (CPCI405 etc.) 202 */ 203#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 204#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 205#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 206 207#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 208 209#if 0 /* Use NVRAM for environment variables */ 210/*----------------------------------------------------------------------- 211 * NVRAM organization 212 */ 213#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 214#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ 215#define CONFIG_ENV_ADDR \ 216 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ 217 218#else /* Use EEPROM for environment variables */ 219 220#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 221#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 222#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ 223 /* total size of a CAT24WC16 is 2048 bytes */ 224#endif 225 226#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ 227#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 228#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ 229 230/*----------------------------------------------------------------------- 231 * I2C EEPROM (CAT24WC16) for environment 232 */ 233#define CONFIG_SYS_I2C 234#define CONFIG_SYS_I2C_PPC4XX 235#define CONFIG_SYS_I2C_PPC4XX_CH0 236#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 237#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 238 239#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 240#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 241/* mask of address bits that overflow into the "EEPROM chip address" */ 242#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 243#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 244 /* 16 byte page write mode using*/ 245 /* last 4 bits of the address */ 246#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 247 248/* 249 * Init Memory Controller: 250 * 251 * BR0/1 and OR0/1 (FLASH) 252 */ 253 254#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 255#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ 256 257/*----------------------------------------------------------------------- 258 * External Bus Controller (EBC) Setup 259 */ 260 261/* Memory Bank 0 (Flash Bank 0) initialization */ 262#define CONFIG_SYS_EBC_PB0AP 0x92015480 263#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 264 265/* Memory Bank 1 (Flash Bank 1) initialization */ 266#define CONFIG_SYS_EBC_PB1AP 0x92015480 267#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ 268 269/* Memory Bank 2 (CAN0, 1) initialization */ 270#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 271#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 272#define CONFIG_SYS_LED_ADDR 0xF0000380 273 274/* Memory Bank 3 (CompactFlash IDE) initialization */ 275#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 276#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 277 278/* Memory Bank 4 (NVRAM/RTC) initialization */ 279/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ 280#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ 281#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 282 283/* Memory Bank 5 (optional Quart) initialization */ 284#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ 285#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 286 287/* Memory Bank 6 (FPGA internal) initialization */ 288#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 289#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 290#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 291 292/*----------------------------------------------------------------------- 293 * FPGA stuff 294 */ 295/* FPGA internal regs */ 296#define CONFIG_SYS_FPGA_MODE 0x00 297#define CONFIG_SYS_FPGA_STATUS 0x02 298#define CONFIG_SYS_FPGA_TS 0x04 299#define CONFIG_SYS_FPGA_TS_LOW 0x06 300#define CONFIG_SYS_FPGA_TS_CAP0 0x10 301#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 302#define CONFIG_SYS_FPGA_TS_CAP1 0x14 303#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 304#define CONFIG_SYS_FPGA_TS_CAP2 0x18 305#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a 306#define CONFIG_SYS_FPGA_TS_CAP3 0x1c 307#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e 308 309/* FPGA Mode Reg */ 310#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 311#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 312#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ 313#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 314#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 315#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 316 317/* FPGA Status Reg */ 318#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 319#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 320#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 321#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 322#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 323 324#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 325#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ 326 327/* FPGA program pin configuration */ 328#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 329#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 330#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 331#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ 332#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ 333 334/*----------------------------------------------------------------------- 335 * Definitions for initial stack pointer and data area (in data cache) 336 */ 337#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 338 339#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 340#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 341#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 342#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 343 344#endif /* __CONFIG_H */ 345