1
2
3
4
5
6
7
8
9
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <asm/config_mpc85xx.h>
15#define CONFIG_NAND_FSL_IFC
16
17#ifdef CONFIG_SDCARD
18#define CONFIG_SPL_MMC_MINIMAL
19#define CONFIG_SPL_FLUSH_IMAGE
20#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21#define CONFIG_SYS_TEXT_BASE 0x11001000
22#define CONFIG_SPL_TEXT_BASE 0xD0001000
23#define CONFIG_SPL_PAD_TO 0x18000
24#define CONFIG_SPL_MAX_SIZE (96 * 1024)
25#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
26#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
28#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
29#define CONFIG_SYS_MPC85XX_NO_RESETVEC
30#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
31#define CONFIG_SPL_MMC_BOOT
32#ifdef CONFIG_SPL_BUILD
33#define CONFIG_SPL_COMMON_INIT_DDR
34#endif
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#ifdef CONFIG_SECURE_BOOT
39#define CONFIG_RAMBOOT_SPIFLASH
40#define CONFIG_SYS_TEXT_BASE 0x11000000
41#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
42#else
43#define CONFIG_SPL_SPI_FLASH_MINIMAL
44#define CONFIG_SPL_FLUSH_IMAGE
45#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46#define CONFIG_SYS_TEXT_BASE 0x11001000
47#define CONFIG_SPL_TEXT_BASE 0xD0001000
48#define CONFIG_SPL_PAD_TO 0x18000
49#define CONFIG_SPL_MAX_SIZE (96 * 1024)
50#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
51#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
52#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
53#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
54#define CONFIG_SYS_MPC85XX_NO_RESETVEC
55#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
56#define CONFIG_SPL_SPI_BOOT
57#ifdef CONFIG_SPL_BUILD
58#define CONFIG_SPL_COMMON_INIT_DDR
59#endif
60#endif
61#endif
62
63#ifdef CONFIG_NAND
64#ifdef CONFIG_SECURE_BOOT
65#define CONFIG_SPL_INIT_MINIMAL
66#define CONFIG_SPL_NAND_BOOT
67#define CONFIG_SPL_FLUSH_IMAGE
68#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69
70#define CONFIG_SYS_TEXT_BASE 0x00201000
71#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
72#define CONFIG_SPL_MAX_SIZE 8192
73#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
74#define CONFIG_SPL_RELOC_STACK 0x00100000
75#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
76#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
77#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
78#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
79#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
80#else
81#ifdef CONFIG_TPL_BUILD
82#define CONFIG_SPL_NAND_BOOT
83#define CONFIG_SPL_FLUSH_IMAGE
84#define CONFIG_SPL_NAND_INIT
85#define CONFIG_SPL_COMMON_INIT_DDR
86#define CONFIG_SPL_MAX_SIZE (128 << 10)
87#define CONFIG_SPL_TEXT_BASE 0xD0001000
88#define CONFIG_SYS_MPC85XX_NO_RESETVEC
89#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
90#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
91#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
92#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
93#elif defined(CONFIG_SPL_BUILD)
94#define CONFIG_SPL_INIT_MINIMAL
95#define CONFIG_SPL_NAND_MINIMAL
96#define CONFIG_SPL_FLUSH_IMAGE
97#define CONFIG_SPL_TEXT_BASE 0xff800000
98#define CONFIG_SPL_MAX_SIZE 8192
99#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
100#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
101#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
102#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
103#endif
104#define CONFIG_SPL_PAD_TO 0x20000
105#define CONFIG_TPL_PAD_TO 0x20000
106#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
107#define CONFIG_SYS_TEXT_BASE 0x11001000
108#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109#endif
110#endif
111
112#ifdef CONFIG_NAND_SECBOOT
113#define CONFIG_RAMBOOT_NAND
114#define CONFIG_SYS_TEXT_BASE 0x11000000
115#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
116#endif
117
118#ifndef CONFIG_SYS_TEXT_BASE
119#define CONFIG_SYS_TEXT_BASE 0xeff40000
120#endif
121
122#ifndef CONFIG_RESET_VECTOR_ADDRESS
123#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124#endif
125
126#ifdef CONFIG_SPL_BUILD
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
128#else
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
130#endif
131
132
133#define CONFIG_FSL_IFC
134#define CONFIG_FSL_CAAM
135#define CONFIG_SYS_HAS_SERDES
136
137#if defined(CONFIG_PCI)
138#define CONFIG_PCIE1
139#define CONFIG_PCIE2
140#define CONFIG_FSL_PCI_INIT
141#define CONFIG_PCI_INDIRECT_BRIDGE
142#define CONFIG_FSL_PCIE_RESET
143#define CONFIG_SYS_PCI_64BIT
144
145#define CONFIG_CMD_PCI
146
147
148
149
150
151
152#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
153#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
156#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
157#else
158#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
159#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
160#endif
161#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
162#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
163#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
164#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
165#ifdef CONFIG_PHYS_64BIT
166#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
167#else
168#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
169#endif
170
171
172#if defined(CONFIG_TARGET_P1010RDB_PA)
173#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
174#elif defined(CONFIG_TARGET_P1010RDB_PB)
175#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
176#endif
177#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
178#ifdef CONFIG_PHYS_64BIT
179#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
180#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
181#else
182#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
183#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
184#endif
185#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
186#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
187#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
188#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
189#ifdef CONFIG_PHYS_64BIT
190#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
191#else
192#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
193#endif
194
195#define CONFIG_PCI_SCAN_SHOW
196#define CONFIG_DOS_PARTITION
197#endif
198
199#define CONFIG_TSEC_ENET
200#define CONFIG_ENV_OVERWRITE
201
202#define CONFIG_DDR_CLK_FREQ 66666666
203#define CONFIG_SYS_CLK_FREQ 66666666
204
205#define CONFIG_MISC_INIT_R
206#define CONFIG_HWCONFIG
207
208
209
210#define CONFIG_L2_CACHE
211#define CONFIG_BTB
212
213#define CONFIG_ADDR_STREAMING
214
215#define CONFIG_ENABLE_36BIT_PHYS
216
217#ifdef CONFIG_PHYS_64BIT
218#define CONFIG_ADDR_MAP 1
219#define CONFIG_SYS_NUM_ADDR_MAP 16
220#endif
221
222#define CONFIG_SYS_MEMTEST_START 0x00200000
223#define CONFIG_SYS_MEMTEST_END 0x1fffffff
224#define CONFIG_PANIC_HANG
225
226
227#define CONFIG_SYS_DDR_RAW_TIMING
228#define CONFIG_DDR_SPD
229#define CONFIG_SYS_SPD_BUS_NUM 1
230#define SPD_EEPROM_ADDRESS 0x52
231
232#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
233
234#ifndef __ASSEMBLY__
235extern unsigned long get_sdram_size(void);
236#endif
237#define CONFIG_SYS_SDRAM_SIZE get_sdram_size()
238#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
239#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
240
241#define CONFIG_DIMM_SLOTS_PER_CTLR 1
242#define CONFIG_CHIP_SELECTS_PER_CTRL 1
243
244
245#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
246#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
247#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
248#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
249#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
250#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
251#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
252#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
253#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
254#define CONFIG_SYS_DDR_RCW_1 0x00000000
255#define CONFIG_SYS_DDR_RCW_2 0x00000000
256#define CONFIG_SYS_DDR_CONTROL 0xc70c0008
257#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
258#define CONFIG_SYS_DDR_TIMING_4 0x00000001
259#define CONFIG_SYS_DDR_TIMING_5 0x03402400
260
261#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
262#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
263#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
264#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
265#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
266#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
267#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
268#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
269#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
270
271
272#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
273#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
274#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
275#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
276#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
277#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
278#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
279#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
280#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
281
282#define CONFIG_SYS_CCSRBAR 0xffe00000
283#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
284
285
286#ifdef CONFIG_SPL_BUILD
287#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
288#endif
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308#ifdef CONFIG_SPL_BUILD
309#define CONFIG_SYS_NO_FLASH
310#endif
311
312#define CONFIG_SYS_FLASH_BASE 0xee000000
313#define CONFIG_SYS_MAX_FLASH_SECT 256
314
315#ifdef CONFIG_PHYS_64BIT
316#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
317#else
318#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
319#endif
320
321#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
322 CSPR_PORT_SIZE_16 | \
323 CSPR_MSEL_NOR | \
324 CSPR_V)
325#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
326#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
327
328#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
329 FTIM0_NOR_TEADC(0x5) | \
330 FTIM0_NOR_TEAHC(0x5)
331#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
332 FTIM1_NOR_TRAD_NOR(0x0f)
333#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
334 FTIM2_NOR_TCH(0x4) | \
335 FTIM2_NOR_TWP(0x1c)
336#define CONFIG_SYS_NOR_FTIM3 0x0
337
338#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
339#define CONFIG_SYS_FLASH_QUIET_TEST
340#define CONFIG_FLASH_SHOW_PROGRESS 45
341#define CONFIG_SYS_MAX_FLASH_BANKS 1
342
343#undef CONFIG_SYS_FLASH_CHECKSUM
344#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
345#define CONFIG_SYS_FLASH_WRITE_TOUT 500
346
347
348#define CONFIG_FLASH_CFI_DRIVER
349#define CONFIG_SYS_FLASH_CFI
350#define CONFIG_SYS_FLASH_EMPTY_INFO
351#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
352
353
354#define CONFIG_SYS_NAND_BASE 0xff800000
355#ifdef CONFIG_PHYS_64BIT
356#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
357#else
358#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
359#endif
360
361#define CONFIG_MTD_DEVICE
362#define CONFIG_MTD_PARTITION
363#define CONFIG_CMD_MTDPARTS
364#define MTDIDS_DEFAULT "nand0=ff800000.flash"
365#define MTDPARTS_DEFAULT \
366 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
367
368#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
369 | CSPR_PORT_SIZE_8 \
370 | CSPR_MSEL_NAND \
371 | CSPR_V)
372#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
373
374#if defined(CONFIG_TARGET_P1010RDB_PA)
375#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
376 | CSOR_NAND_ECC_DEC_EN \
377 | CSOR_NAND_ECC_MODE_4 \
378 | CSOR_NAND_RAL_2 \
379 | CSOR_NAND_PGS_512 \
380 | CSOR_NAND_SPRZ_16 \
381 | CSOR_NAND_PB(32))
382#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
383
384#elif defined(CONFIG_TARGET_P1010RDB_PB)
385#define CONFIG_SYS_NAND_ONFI_DETECTION
386#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
387 | CSOR_NAND_ECC_DEC_EN \
388 | CSOR_NAND_ECC_MODE_4 \
389 | CSOR_NAND_RAL_3 \
390 | CSOR_NAND_PGS_4K \
391 | CSOR_NAND_SPRZ_224 \
392 | CSOR_NAND_PB(128))
393#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
394#endif
395
396#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
397#define CONFIG_SYS_MAX_NAND_DEVICE 1
398#define CONFIG_CMD_NAND
399
400#if defined(CONFIG_TARGET_P1010RDB_PA)
401
402#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
403 FTIM0_NAND_TWP(0x0C) | \
404 FTIM0_NAND_TWCHT(0x04) | \
405 FTIM0_NAND_TWH(0x05)
406#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
407 FTIM1_NAND_TWBE(0x1d) | \
408 FTIM1_NAND_TRR(0x07) | \
409 FTIM1_NAND_TRP(0x0c)
410#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
411 FTIM2_NAND_TREH(0x05) | \
412 FTIM2_NAND_TWHRE(0x0f)
413#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
414
415#elif defined(CONFIG_TARGET_P1010RDB_PB)
416
417
418#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
419 FTIM0_NAND_TWP(0x18) | \
420 FTIM0_NAND_TWCHT(0x07) | \
421 FTIM0_NAND_TWH(0x0a))
422#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
423 FTIM1_NAND_TWBE(0x39) | \
424 FTIM1_NAND_TRR(0x0e) | \
425 FTIM1_NAND_TRP(0x18))
426#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
427 FTIM2_NAND_TREH(0x0a) | \
428 FTIM2_NAND_TWHRE(0x1e))
429#define CONFIG_SYS_NAND_FTIM3 0x0
430#endif
431
432#define CONFIG_SYS_NAND_DDR_LAW 11
433
434
435#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
436#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
437#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
438#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
439#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
440#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
441#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
442#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
443#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
444#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
445#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
446#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
447#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
448#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
449#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
450#else
451#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
452#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
453#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
454#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
455#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
456#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
457#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
458#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
459#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
460#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
461#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
462#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
463#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
464#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
465#endif
466
467
468#define CONFIG_SYS_CPLD_BASE 0xffb00000
469
470#ifdef CONFIG_PHYS_64BIT
471#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
472#else
473#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
474#endif
475
476#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
477 | CSPR_PORT_SIZE_8 \
478 | CSPR_MSEL_GPCM \
479 | CSPR_V)
480#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
481#define CONFIG_SYS_CSOR3 0x0
482
483#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
484 FTIM0_GPCM_TEADC(0x0e) | \
485 FTIM0_GPCM_TEAHC(0x0e))
486#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
487 FTIM1_GPCM_TRAD(0x1f))
488#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
489 FTIM2_GPCM_TCH(0x8) | \
490 FTIM2_GPCM_TWP(0x1f))
491#define CONFIG_SYS_CS3_FTIM3 0x0
492
493#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
494 defined(CONFIG_RAMBOOT_NAND)
495#define CONFIG_SYS_RAMBOOT
496#define CONFIG_SYS_EXTRA_ENV_RELOC
497#else
498#undef CONFIG_SYS_RAMBOOT
499#endif
500
501#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
502#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
503#define CONFIG_A003399_NOR_WORKAROUND
504#endif
505#endif
506
507#define CONFIG_BOARD_EARLY_INIT_F
508#define CONFIG_BOARD_EARLY_INIT_R
509
510#define CONFIG_SYS_INIT_RAM_LOCK
511#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
512#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
513
514#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
515 - GENERATED_GBL_DATA_SIZE)
516#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
517
518#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
519#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
520
521
522
523
524#if defined(CONFIG_SPL_BUILD)
525#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
526#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
527#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
528#define CONFIG_SYS_L2_SIZE (256 << 10)
529#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
530#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
531#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
532#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
533#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
534#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
535#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
536#elif defined(CONFIG_NAND)
537#ifdef CONFIG_TPL_BUILD
538#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
539#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
540#define CONFIG_SYS_L2_SIZE (256 << 10)
541#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
542#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
543#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
544#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
545#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
546#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
547#else
548#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
549#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
550#define CONFIG_SYS_L2_SIZE (256 << 10)
551#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
552#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
553#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
554#endif
555#endif
556#endif
557
558
559#define CONFIG_CONS_INDEX 1
560#undef CONFIG_SERIAL_SOFTWARE_FIFO
561#define CONFIG_SYS_NS16550_SERIAL
562#define CONFIG_SYS_NS16550_REG_SIZE 1
563#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
564#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
565#define CONFIG_NS16550_MIN_FUNCTIONS
566#endif
567
568#define CONFIG_SYS_BAUDRATE_TABLE \
569 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
570
571#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
572#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
573
574
575#define CONFIG_SYS_I2C
576#define CONFIG_SYS_I2C_FSL
577#define CONFIG_SYS_FSL_I2C_SPEED 400000
578#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
579#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
580#define CONFIG_SYS_FSL_I2C2_SPEED 400000
581#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
582#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
583#define I2C_PCA9557_ADDR1 0x18
584#define I2C_PCA9557_ADDR2 0x19
585#define I2C_PCA9557_BUS_NUM 0
586
587
588#if defined(CONFIG_TARGET_P1010RDB_PB)
589#define CONFIG_ID_EEPROM
590#ifdef CONFIG_ID_EEPROM
591#define CONFIG_SYS_I2C_EEPROM_NXID
592#endif
593#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
594#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
595#define CONFIG_SYS_EEPROM_BUS_NUM 0
596#define MAX_NUM_PORTS 9
597#endif
598
599#define CONFIG_CMD_EEPROM
600#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
601#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
602#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
603
604
605#define CONFIG_RTC_PT7C4338
606#define CONFIG_SYS_I2C_RTC_ADDR 0x68
607
608
609
610
611
612#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
613
614#define CONFIG_SF_DEFAULT_SPEED 10000000
615#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
616#endif
617
618#if defined(CONFIG_TSEC_ENET)
619#define CONFIG_MII
620#define CONFIG_MII_DEFAULT_TSEC 1
621#define CONFIG_TSEC1 1
622#define CONFIG_TSEC1_NAME "eTSEC1"
623#define CONFIG_TSEC2 1
624#define CONFIG_TSEC2_NAME "eTSEC2"
625#define CONFIG_TSEC3 1
626#define CONFIG_TSEC3_NAME "eTSEC3"
627
628#define TSEC1_PHY_ADDR 1
629#define TSEC2_PHY_ADDR 0
630#define TSEC3_PHY_ADDR 2
631
632#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
633#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
634#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
635
636#define TSEC1_PHYIDX 0
637#define TSEC2_PHYIDX 0
638#define TSEC3_PHYIDX 0
639
640#define CONFIG_ETHPRIME "eTSEC1"
641
642#define CONFIG_PHY_GIGE
643
644
645#define CONFIG_TSEC_TBICR_SETTINGS ( \
646 TBICR_PHY_RESET \
647 | TBICR_ANEG_ENABLE \
648 | TBICR_FULL_DUPLEX \
649 | TBICR_SPEED1_SET \
650 )
651
652#endif
653
654
655#define CONFIG_FSL_SATA
656#define CONFIG_FSL_SATA_V2
657#define CONFIG_LIBATA
658
659#ifdef CONFIG_FSL_SATA
660#define CONFIG_SYS_SATA_MAX_DEVICE 2
661#define CONFIG_SATA1
662#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
663#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
664#define CONFIG_SATA2
665#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
666#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
667
668#define CONFIG_CMD_SATA
669#define CONFIG_LBA48
670#endif
671
672#ifdef CONFIG_MMC
673#define CONFIG_DOS_PARTITION
674#define CONFIG_FSL_ESDHC
675#define CONFIG_GENERIC_MMC
676#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
677#endif
678
679#define CONFIG_HAS_FSL_DR_USB
680
681#if defined(CONFIG_HAS_FSL_DR_USB)
682#define CONFIG_USB_EHCI
683
684#ifdef CONFIG_USB_EHCI
685#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
686#define CONFIG_USB_EHCI_FSL
687#endif
688#endif
689
690
691
692
693#if defined(CONFIG_SDCARD)
694#define CONFIG_ENV_IS_IN_MMC
695#define CONFIG_FSL_FIXED_MMC_LOCATION
696#define CONFIG_SYS_MMC_ENV_DEV 0
697#define CONFIG_ENV_SIZE 0x2000
698#elif defined(CONFIG_SPIFLASH)
699#define CONFIG_ENV_IS_IN_SPI_FLASH
700#define CONFIG_ENV_SPI_BUS 0
701#define CONFIG_ENV_SPI_CS 0
702#define CONFIG_ENV_SPI_MAX_HZ 10000000
703#define CONFIG_ENV_SPI_MODE 0
704#define CONFIG_ENV_OFFSET 0x100000
705#define CONFIG_ENV_SECT_SIZE 0x10000
706#define CONFIG_ENV_SIZE 0x2000
707#elif defined(CONFIG_NAND)
708#define CONFIG_ENV_IS_IN_NAND
709#ifdef CONFIG_TPL_BUILD
710#define CONFIG_ENV_SIZE 0x2000
711#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
712#else
713#if defined(CONFIG_TARGET_P1010RDB_PA)
714#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
715#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
716#elif defined(CONFIG_TARGET_P1010RDB_PB)
717#define CONFIG_ENV_SIZE (16 * 1024)
718#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE)
719#endif
720#endif
721#define CONFIG_ENV_OFFSET (1024 * 1024)
722#elif defined(CONFIG_SYS_RAMBOOT)
723#define CONFIG_ENV_IS_NOWHERE
724#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
725#define CONFIG_ENV_SIZE 0x2000
726#else
727#define CONFIG_ENV_IS_IN_FLASH
728#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
729#define CONFIG_ENV_SIZE 0x2000
730#define CONFIG_ENV_SECT_SIZE 0x20000
731#endif
732
733#define CONFIG_LOADS_ECHO
734#define CONFIG_SYS_LOADS_BAUD_CHANGE
735
736
737
738
739#define CONFIG_CMD_DATE
740#define CONFIG_CMD_ERRATA
741#define CONFIG_CMD_IRQ
742#define CONFIG_CMD_REGINFO
743
744#undef CONFIG_WATCHDOG
745
746#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
747 || defined(CONFIG_FSL_SATA)
748#define CONFIG_DOS_PARTITION
749#endif
750
751
752#ifdef CONFIG_FSL_CAAM
753#define CONFIG_CMD_HASH
754#define CONFIG_SHA_HW_ACCEL
755#endif
756
757
758
759
760#define CONFIG_SYS_LONGHELP
761#define CONFIG_CMDLINE_EDITING
762#define CONFIG_AUTO_COMPLETE
763#define CONFIG_SYS_LOAD_ADDR 0x2000000
764
765#if defined(CONFIG_CMD_KGDB)
766#define CONFIG_SYS_CBSIZE 1024
767#else
768#define CONFIG_SYS_CBSIZE 256
769#endif
770#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
771
772#define CONFIG_SYS_MAXARGS 16
773#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
774
775
776
777
778
779
780#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
781#define CONFIG_SYS_BOOTM_LEN (64 << 20)
782
783#if defined(CONFIG_CMD_KGDB)
784#define CONFIG_KGDB_BAUDRATE 230400
785#endif
786
787
788
789
790
791#if defined(CONFIG_TSEC_ENET)
792#define CONFIG_HAS_ETH0
793#define CONFIG_HAS_ETH1
794#define CONFIG_HAS_ETH2
795#endif
796
797#define CONFIG_ROOTPATH "/opt/nfsroot"
798#define CONFIG_BOOTFILE "uImage"
799#define CONFIG_UBOOTPATH u-boot.bin
800
801
802#define CONFIG_LOADADDR 1000000
803
804#undef CONFIG_BOOTARGS
805
806#define CONFIG_BAUDRATE 115200
807
808#define CONFIG_EXTRA_ENV_SETTINGS \
809 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
810 "netdev=eth0\0" \
811 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
812 "loadaddr=1000000\0" \
813 "consoledev=ttyS0\0" \
814 "ramdiskaddr=2000000\0" \
815 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
816 "fdtaddr=1e00000\0" \
817 "fdtfile=p1010rdb.dtb\0" \
818 "bdev=sda1\0" \
819 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
820 "othbootargs=ramdisk_size=600000\0" \
821 "usbfatboot=setenv bootargs root=/dev/ram rw " \
822 "console=$consoledev,$baudrate $othbootargs; " \
823 "usb start;" \
824 "fatload usb 0:2 $loadaddr $bootfile;" \
825 "fatload usb 0:2 $fdtaddr $fdtfile;" \
826 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
827 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
828 "usbext2boot=setenv bootargs root=/dev/ram rw " \
829 "console=$consoledev,$baudrate $othbootargs; " \
830 "usb start;" \
831 "ext2load usb 0:4 $loadaddr $bootfile;" \
832 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
833 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
834 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
835 CONFIG_BOOTMODE
836
837#if defined(CONFIG_TARGET_P1010RDB_PA)
838#define CONFIG_BOOTMODE \
839 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
840 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
841 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
842 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
843 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
844 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
845
846#elif defined(CONFIG_TARGET_P1010RDB_PB)
847#define CONFIG_BOOTMODE \
848 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
849 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
850 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
851 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
852 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
853 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
854 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
855 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
856 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
857 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
858#endif
859
860#define CONFIG_RAMBOOTCOMMAND \
861 "setenv bootargs root=/dev/ram rw " \
862 "console=$consoledev,$baudrate $othbootargs; " \
863 "tftp $ramdiskaddr $ramdiskfile;" \
864 "tftp $loadaddr $bootfile;" \
865 "tftp $fdtaddr $fdtfile;" \
866 "bootm $loadaddr $ramdiskaddr $fdtaddr"
867
868#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
869
870#include <asm/fsl_secure_boot.h>
871
872#endif
873